1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PIC32 RTC driver 4 * 5 * Joshua Henderson <joshua.henderson@microchip.com> 6 * Copyright (C) 2016 Microchip Technology Inc. All rights reserved. 7 * 8 */ 9 #include <linux/init.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/io.h> 14 #include <linux/slab.h> 15 #include <linux/clk.h> 16 #include <linux/rtc.h> 17 #include <linux/bcd.h> 18 #include <linux/platform_data/pic32.h> 19 20 #define PIC32_RTCCON 0x00 21 #define PIC32_RTCCON_ON BIT(15) 22 #define PIC32_RTCCON_SIDL BIT(13) 23 #define PIC32_RTCCON_RTCCLKSEL (3 << 9) 24 #define PIC32_RTCCON_RTCCLKON BIT(6) 25 #define PIC32_RTCCON_RTCWREN BIT(3) 26 #define PIC32_RTCCON_RTCSYNC BIT(2) 27 #define PIC32_RTCCON_HALFSEC BIT(1) 28 #define PIC32_RTCCON_RTCOE BIT(0) 29 30 #define PIC32_RTCALRM 0x10 31 #define PIC32_RTCALRM_ALRMEN BIT(15) 32 #define PIC32_RTCALRM_CHIME BIT(14) 33 #define PIC32_RTCALRM_PIV BIT(13) 34 #define PIC32_RTCALRM_ALARMSYNC BIT(12) 35 #define PIC32_RTCALRM_AMASK 0x0F00 36 #define PIC32_RTCALRM_ARPT 0xFF 37 38 #define PIC32_RTCHOUR 0x23 39 #define PIC32_RTCMIN 0x22 40 #define PIC32_RTCSEC 0x21 41 #define PIC32_RTCYEAR 0x33 42 #define PIC32_RTCMON 0x32 43 #define PIC32_RTCDAY 0x31 44 45 #define PIC32_ALRMTIME 0x40 46 #define PIC32_ALRMDATE 0x50 47 48 #define PIC32_ALRMHOUR 0x43 49 #define PIC32_ALRMMIN 0x42 50 #define PIC32_ALRMSEC 0x41 51 #define PIC32_ALRMYEAR 0x53 52 #define PIC32_ALRMMON 0x52 53 #define PIC32_ALRMDAY 0x51 54 55 struct pic32_rtc_dev { 56 struct rtc_device *rtc; 57 void __iomem *reg_base; 58 struct clk *clk; 59 spinlock_t alarm_lock; 60 int alarm_irq; 61 bool alarm_clk_enabled; 62 }; 63 64 static void pic32_rtc_alarm_clk_enable(struct pic32_rtc_dev *pdata, 65 bool enable) 66 { 67 unsigned long flags; 68 69 spin_lock_irqsave(&pdata->alarm_lock, flags); 70 if (enable) { 71 if (!pdata->alarm_clk_enabled) { 72 clk_enable(pdata->clk); 73 pdata->alarm_clk_enabled = true; 74 } 75 } else { 76 if (pdata->alarm_clk_enabled) { 77 clk_disable(pdata->clk); 78 pdata->alarm_clk_enabled = false; 79 } 80 } 81 spin_unlock_irqrestore(&pdata->alarm_lock, flags); 82 } 83 84 static irqreturn_t pic32_rtc_alarmirq(int irq, void *id) 85 { 86 struct pic32_rtc_dev *pdata = (struct pic32_rtc_dev *)id; 87 88 clk_enable(pdata->clk); 89 rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF); 90 clk_disable(pdata->clk); 91 92 pic32_rtc_alarm_clk_enable(pdata, false); 93 94 return IRQ_HANDLED; 95 } 96 97 static int pic32_rtc_setaie(struct device *dev, unsigned int enabled) 98 { 99 struct pic32_rtc_dev *pdata = dev_get_drvdata(dev); 100 void __iomem *base = pdata->reg_base; 101 102 clk_enable(pdata->clk); 103 104 writel(PIC32_RTCALRM_ALRMEN, 105 base + (enabled ? PIC32_SET(PIC32_RTCALRM) : 106 PIC32_CLR(PIC32_RTCALRM))); 107 108 clk_disable(pdata->clk); 109 110 pic32_rtc_alarm_clk_enable(pdata, enabled); 111 112 return 0; 113 } 114 115 static int pic32_rtc_setfreq(struct device *dev, int freq) 116 { 117 struct pic32_rtc_dev *pdata = dev_get_drvdata(dev); 118 void __iomem *base = pdata->reg_base; 119 120 clk_enable(pdata->clk); 121 122 writel(PIC32_RTCALRM_AMASK, base + PIC32_CLR(PIC32_RTCALRM)); 123 writel(freq << 8, base + PIC32_SET(PIC32_RTCALRM)); 124 writel(PIC32_RTCALRM_CHIME, base + PIC32_SET(PIC32_RTCALRM)); 125 126 clk_disable(pdata->clk); 127 128 return 0; 129 } 130 131 static int pic32_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) 132 { 133 struct pic32_rtc_dev *pdata = dev_get_drvdata(dev); 134 void __iomem *base = pdata->reg_base; 135 unsigned int tries = 0; 136 137 clk_enable(pdata->clk); 138 139 do { 140 rtc_tm->tm_hour = readb(base + PIC32_RTCHOUR); 141 rtc_tm->tm_min = readb(base + PIC32_RTCMIN); 142 rtc_tm->tm_mon = readb(base + PIC32_RTCMON); 143 rtc_tm->tm_mday = readb(base + PIC32_RTCDAY); 144 rtc_tm->tm_year = readb(base + PIC32_RTCYEAR); 145 rtc_tm->tm_sec = readb(base + PIC32_RTCSEC); 146 147 /* 148 * The only way to work out whether the system was mid-update 149 * when we read it is to check the second counter, and if it 150 * is zero, then we re-try the entire read. 151 */ 152 tries += 1; 153 } while (rtc_tm->tm_sec == 0 && tries < 2); 154 155 rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); 156 rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min); 157 rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour); 158 rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday); 159 rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon) - 1; 160 rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year); 161 162 rtc_tm->tm_year += 100; 163 164 dev_dbg(dev, "read time %ptR\n", rtc_tm); 165 166 clk_disable(pdata->clk); 167 return 0; 168 } 169 170 static int pic32_rtc_settime(struct device *dev, struct rtc_time *tm) 171 { 172 struct pic32_rtc_dev *pdata = dev_get_drvdata(dev); 173 void __iomem *base = pdata->reg_base; 174 175 dev_dbg(dev, "set time %ptR\n", tm); 176 177 clk_enable(pdata->clk); 178 writeb(bin2bcd(tm->tm_sec), base + PIC32_RTCSEC); 179 writeb(bin2bcd(tm->tm_min), base + PIC32_RTCMIN); 180 writeb(bin2bcd(tm->tm_hour), base + PIC32_RTCHOUR); 181 writeb(bin2bcd(tm->tm_mday), base + PIC32_RTCDAY); 182 writeb(bin2bcd(tm->tm_mon + 1), base + PIC32_RTCMON); 183 writeb(bin2bcd(tm->tm_year - 100), base + PIC32_RTCYEAR); 184 clk_disable(pdata->clk); 185 186 return 0; 187 } 188 189 static int pic32_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm) 190 { 191 struct pic32_rtc_dev *pdata = dev_get_drvdata(dev); 192 struct rtc_time *alm_tm = &alrm->time; 193 void __iomem *base = pdata->reg_base; 194 unsigned int alm_en; 195 196 clk_enable(pdata->clk); 197 alm_tm->tm_sec = readb(base + PIC32_ALRMSEC); 198 alm_tm->tm_min = readb(base + PIC32_ALRMMIN); 199 alm_tm->tm_hour = readb(base + PIC32_ALRMHOUR); 200 alm_tm->tm_mon = readb(base + PIC32_ALRMMON); 201 alm_tm->tm_mday = readb(base + PIC32_ALRMDAY); 202 alm_tm->tm_year = readb(base + PIC32_ALRMYEAR); 203 204 alm_en = readb(base + PIC32_RTCALRM); 205 206 alrm->enabled = (alm_en & PIC32_RTCALRM_ALRMEN) ? 1 : 0; 207 208 dev_dbg(dev, "getalarm: %d, %ptR\n", alm_en, alm_tm); 209 210 alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec); 211 alm_tm->tm_min = bcd2bin(alm_tm->tm_min); 212 alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour); 213 alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday); 214 alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon) - 1; 215 alm_tm->tm_year = bcd2bin(alm_tm->tm_year); 216 217 clk_disable(pdata->clk); 218 return 0; 219 } 220 221 static int pic32_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) 222 { 223 struct pic32_rtc_dev *pdata = dev_get_drvdata(dev); 224 struct rtc_time *tm = &alrm->time; 225 void __iomem *base = pdata->reg_base; 226 227 clk_enable(pdata->clk); 228 dev_dbg(dev, "setalarm: %d, %ptR\n", alrm->enabled, tm); 229 230 writel(0x00, base + PIC32_ALRMTIME); 231 writel(0x00, base + PIC32_ALRMDATE); 232 233 pic32_rtc_setaie(dev, alrm->enabled); 234 235 clk_disable(pdata->clk); 236 return 0; 237 } 238 239 static int pic32_rtc_proc(struct device *dev, struct seq_file *seq) 240 { 241 struct pic32_rtc_dev *pdata = dev_get_drvdata(dev); 242 void __iomem *base = pdata->reg_base; 243 unsigned int repeat; 244 245 clk_enable(pdata->clk); 246 247 repeat = readw(base + PIC32_RTCALRM); 248 repeat &= PIC32_RTCALRM_ARPT; 249 seq_printf(seq, "periodic_IRQ\t: %s\n", repeat ? "yes" : "no"); 250 251 clk_disable(pdata->clk); 252 return 0; 253 } 254 255 static const struct rtc_class_ops pic32_rtcops = { 256 .read_time = pic32_rtc_gettime, 257 .set_time = pic32_rtc_settime, 258 .read_alarm = pic32_rtc_getalarm, 259 .set_alarm = pic32_rtc_setalarm, 260 .proc = pic32_rtc_proc, 261 .alarm_irq_enable = pic32_rtc_setaie, 262 }; 263 264 static void pic32_rtc_enable(struct pic32_rtc_dev *pdata, int en) 265 { 266 void __iomem *base = pdata->reg_base; 267 268 if (!base) 269 return; 270 271 clk_enable(pdata->clk); 272 if (!en) { 273 writel(PIC32_RTCCON_ON, base + PIC32_CLR(PIC32_RTCCON)); 274 } else { 275 pic32_syskey_unlock(); 276 277 writel(PIC32_RTCCON_RTCWREN, base + PIC32_SET(PIC32_RTCCON)); 278 writel(3 << 9, base + PIC32_CLR(PIC32_RTCCON)); 279 280 if (!(readl(base + PIC32_RTCCON) & PIC32_RTCCON_ON)) 281 writel(PIC32_RTCCON_ON, base + PIC32_SET(PIC32_RTCCON)); 282 } 283 clk_disable(pdata->clk); 284 } 285 286 static void pic32_rtc_remove(struct platform_device *pdev) 287 { 288 struct pic32_rtc_dev *pdata = platform_get_drvdata(pdev); 289 290 pic32_rtc_setaie(&pdev->dev, 0); 291 clk_unprepare(pdata->clk); 292 pdata->clk = NULL; 293 } 294 295 static int pic32_rtc_probe(struct platform_device *pdev) 296 { 297 struct pic32_rtc_dev *pdata; 298 int ret; 299 300 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 301 if (!pdata) 302 return -ENOMEM; 303 304 platform_set_drvdata(pdev, pdata); 305 306 pdata->alarm_irq = platform_get_irq(pdev, 0); 307 if (pdata->alarm_irq < 0) 308 return pdata->alarm_irq; 309 310 pdata->reg_base = devm_platform_ioremap_resource(pdev, 0); 311 if (IS_ERR(pdata->reg_base)) 312 return PTR_ERR(pdata->reg_base); 313 314 pdata->clk = devm_clk_get(&pdev->dev, NULL); 315 if (IS_ERR(pdata->clk)) { 316 dev_err(&pdev->dev, "failed to find rtc clock source\n"); 317 ret = PTR_ERR(pdata->clk); 318 pdata->clk = NULL; 319 return ret; 320 } 321 322 spin_lock_init(&pdata->alarm_lock); 323 324 pdata->rtc = devm_rtc_allocate_device(&pdev->dev); 325 if (IS_ERR(pdata->rtc)) 326 return PTR_ERR(pdata->rtc); 327 328 clk_prepare_enable(pdata->clk); 329 330 pic32_rtc_enable(pdata, 1); 331 332 device_init_wakeup(&pdev->dev, true); 333 334 pdata->rtc->ops = &pic32_rtcops; 335 pdata->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 336 pdata->rtc->range_max = RTC_TIMESTAMP_END_2099; 337 338 ret = devm_rtc_register_device(pdata->rtc); 339 if (ret) 340 goto err_nortc; 341 342 pic32_rtc_setfreq(&pdev->dev, 1); 343 ret = devm_request_irq(&pdev->dev, pdata->alarm_irq, 344 pic32_rtc_alarmirq, 0, 345 dev_name(&pdev->dev), pdata); 346 if (ret) { 347 dev_err(&pdev->dev, 348 "IRQ %d error %d\n", pdata->alarm_irq, ret); 349 goto err_nortc; 350 } 351 352 clk_disable(pdata->clk); 353 354 return 0; 355 356 err_nortc: 357 pic32_rtc_enable(pdata, 0); 358 clk_disable_unprepare(pdata->clk); 359 360 return ret; 361 } 362 363 static const struct of_device_id pic32_rtc_dt_ids[] = { 364 { .compatible = "microchip,pic32mzda-rtc" }, 365 { /* sentinel */ } 366 }; 367 MODULE_DEVICE_TABLE(of, pic32_rtc_dt_ids); 368 369 static struct platform_driver pic32_rtc_driver = { 370 .probe = pic32_rtc_probe, 371 .remove = pic32_rtc_remove, 372 .driver = { 373 .name = "pic32-rtc", 374 .of_match_table = of_match_ptr(pic32_rtc_dt_ids), 375 }, 376 }; 377 module_platform_driver(pic32_rtc_driver); 378 379 MODULE_DESCRIPTION("Microchip PIC32 RTC Driver"); 380 MODULE_AUTHOR("Joshua Henderson <joshua.henderson@microchip.com>"); 381 MODULE_LICENSE("GPL"); 382