1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * An I2C and SPI driver for the NXP PCF2127/29/31 RTC 4 * Copyright 2013 Til-Technologies 5 * 6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr> 7 * 8 * Watchdog and tamper functions 9 * Author: Bruno Thomsen <bruno.thomsen@gmail.com> 10 * 11 * PCF2131 support 12 * Author: Hugo Villeneuve <hvilleneuve@dimonoff.com> 13 * 14 * based on the other drivers in this same directory. 15 * 16 * Datasheets: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf 17 * https://www.nxp.com/docs/en/data-sheet/PCF2131DS.pdf 18 */ 19 20 #include <linux/i2c.h> 21 #include <linux/spi/spi.h> 22 #include <linux/bcd.h> 23 #include <linux/rtc.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_device.h> 29 #include <linux/regmap.h> 30 #include <linux/watchdog.h> 31 32 /* Control register 1 */ 33 #define PCF2127_REG_CTRL1 0x00 34 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 35 #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 36 #define PCF2127_BIT_CTRL1_STOP BIT(5) 37 /* Control register 2 */ 38 #define PCF2127_REG_CTRL2 0x01 39 #define PCF2127_BIT_CTRL2_AIE BIT(1) 40 #define PCF2127_BIT_CTRL2_TSIE BIT(2) 41 #define PCF2127_BIT_CTRL2_AF BIT(4) 42 #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 43 #define PCF2127_BIT_CTRL2_WDTF BIT(6) 44 /* Control register 3 */ 45 #define PCF2127_REG_CTRL3 0x02 46 #define PCF2127_BIT_CTRL3_BLIE BIT(0) 47 #define PCF2127_BIT_CTRL3_BIE BIT(1) 48 #define PCF2127_BIT_CTRL3_BLF BIT(2) 49 #define PCF2127_BIT_CTRL3_BF BIT(3) 50 #define PCF2127_BIT_CTRL3_BTSE BIT(4) 51 /* Time and date registers */ 52 #define PCF2127_REG_TIME_BASE 0x03 53 #define PCF2127_BIT_SC_OSF BIT(7) 54 /* Alarm registers */ 55 #define PCF2127_REG_ALARM_BASE 0x0A 56 #define PCF2127_BIT_ALARM_AE BIT(7) 57 /* CLKOUT control register */ 58 #define PCF2127_REG_CLKOUT 0x0f 59 #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 60 /* Watchdog registers */ 61 #define PCF2127_REG_WD_CTL 0x10 62 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 63 #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 64 #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 65 #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 66 #define PCF2127_REG_WD_VAL 0x11 67 /* Tamper timestamp1 registers */ 68 #define PCF2127_REG_TS1_BASE 0x12 69 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 70 #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 71 /* 72 * RAM registers 73 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 74 * battery backed and can survive a power outage. 75 * PCF2129/31 doesn't have this feature. 76 */ 77 #define PCF2127_REG_RAM_ADDR_MSB 0x1A 78 #define PCF2127_REG_RAM_WRT_CMD 0x1C 79 #define PCF2127_REG_RAM_RD_CMD 0x1D 80 81 /* Watchdog timer value constants */ 82 #define PCF2127_WD_VAL_STOP 0 83 /* PCF2127/29 watchdog timer value constants */ 84 #define PCF2127_WD_CLOCK_HZ_X1000 1000 /* 1Hz */ 85 #define PCF2127_WD_MIN_HW_HEARTBEAT_MS 500 86 /* PCF2131 watchdog timer value constants */ 87 #define PCF2131_WD_CLOCK_HZ_X1000 250 /* 1/4Hz */ 88 #define PCF2131_WD_MIN_HW_HEARTBEAT_MS 4000 89 90 #define PCF2127_WD_DEFAULT_TIMEOUT_S 60 91 92 /* Mask for currently enabled interrupts */ 93 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) 94 #define PCF2127_CTRL2_IRQ_MASK ( \ 95 PCF2127_BIT_CTRL2_AF | \ 96 PCF2127_BIT_CTRL2_WDTF | \ 97 PCF2127_BIT_CTRL2_TSF2) 98 99 #define PCF2127_MAX_TS_SUPPORTED 4 100 101 /* Control register 4 */ 102 #define PCF2131_REG_CTRL4 0x03 103 #define PCF2131_BIT_CTRL4_TSF4 BIT(4) 104 #define PCF2131_BIT_CTRL4_TSF3 BIT(5) 105 #define PCF2131_BIT_CTRL4_TSF2 BIT(6) 106 #define PCF2131_BIT_CTRL4_TSF1 BIT(7) 107 /* Control register 5 */ 108 #define PCF2131_REG_CTRL5 0x04 109 #define PCF2131_BIT_CTRL5_TSIE4 BIT(4) 110 #define PCF2131_BIT_CTRL5_TSIE3 BIT(5) 111 #define PCF2131_BIT_CTRL5_TSIE2 BIT(6) 112 #define PCF2131_BIT_CTRL5_TSIE1 BIT(7) 113 /* Software reset register */ 114 #define PCF2131_REG_SR_RESET 0x05 115 #define PCF2131_SR_RESET_READ_PATTERN (BIT(2) | BIT(5)) 116 #define PCF2131_SR_RESET_CPR_CMD (PCF2131_SR_RESET_READ_PATTERN | BIT(7)) 117 /* Time and date registers */ 118 #define PCF2131_REG_TIME_BASE 0x07 119 /* Alarm registers */ 120 #define PCF2131_REG_ALARM_BASE 0x0E 121 /* CLKOUT control register */ 122 #define PCF2131_REG_CLKOUT 0x13 123 /* Watchdog registers */ 124 #define PCF2131_REG_WD_CTL 0x35 125 #define PCF2131_REG_WD_VAL 0x36 126 /* Tamper timestamp1 registers */ 127 #define PCF2131_REG_TS1_BASE 0x14 128 /* Tamper timestamp2 registers */ 129 #define PCF2131_REG_TS2_BASE 0x1B 130 /* Tamper timestamp3 registers */ 131 #define PCF2131_REG_TS3_BASE 0x22 132 /* Tamper timestamp4 registers */ 133 #define PCF2131_REG_TS4_BASE 0x29 134 /* Interrupt mask registers */ 135 #define PCF2131_REG_INT_A_MASK1 0x31 136 #define PCF2131_REG_INT_A_MASK2 0x32 137 #define PCF2131_REG_INT_B_MASK1 0x33 138 #define PCF2131_REG_INT_B_MASK2 0x34 139 #define PCF2131_BIT_INT_BLIE BIT(0) 140 #define PCF2131_BIT_INT_BIE BIT(1) 141 #define PCF2131_BIT_INT_AIE BIT(2) 142 #define PCF2131_BIT_INT_WD_CD BIT(3) 143 #define PCF2131_BIT_INT_SI BIT(4) 144 #define PCF2131_BIT_INT_MI BIT(5) 145 #define PCF2131_CTRL2_IRQ_MASK ( \ 146 PCF2127_BIT_CTRL2_AF | \ 147 PCF2127_BIT_CTRL2_WDTF) 148 #define PCF2131_CTRL4_IRQ_MASK ( \ 149 PCF2131_BIT_CTRL4_TSF4 | \ 150 PCF2131_BIT_CTRL4_TSF3 | \ 151 PCF2131_BIT_CTRL4_TSF2 | \ 152 PCF2131_BIT_CTRL4_TSF1) 153 154 enum pcf21xx_type { 155 PCF2127, 156 PCF2129, 157 PCF2131, 158 PCF21XX_LAST_ID 159 }; 160 161 struct pcf21xx_ts_config { 162 u8 reg_base; /* Base register to read timestamp values. */ 163 164 /* 165 * If the TS input pin is driven to GND, an interrupt can be generated 166 * (supported by all variants). 167 */ 168 u8 gnd_detect_reg; /* Interrupt control register address. */ 169 u8 gnd_detect_bit; /* Interrupt bit. */ 170 171 /* 172 * If the TS input pin is driven to an intermediate level between GND 173 * and supply, an interrupt can be generated (optional feature depending 174 * on variant). 175 */ 176 u8 inter_detect_reg; /* Interrupt control register address. */ 177 u8 inter_detect_bit; /* Interrupt bit. */ 178 179 u8 ie_reg; /* Interrupt enable control register. */ 180 u8 ie_bit; /* Interrupt enable bit. */ 181 }; 182 183 struct pcf21xx_config { 184 int type; /* IC variant */ 185 int max_register; 186 unsigned int has_nvmem:1; 187 unsigned int has_bit_wd_ctl_cd0:1; 188 unsigned int has_int_a_b:1; /* PCF2131 supports two interrupt outputs. */ 189 u8 reg_time_base; /* Time/date base register. */ 190 u8 regs_alarm_base; /* Alarm function base registers. */ 191 u8 reg_wd_ctl; /* Watchdog control register. */ 192 u8 reg_wd_val; /* Watchdog value register. */ 193 u8 reg_clkout; /* Clkout register. */ 194 int wdd_clock_hz_x1000; /* Watchdog clock in Hz multiplicated by 1000 */ 195 int wdd_min_hw_heartbeat_ms; 196 unsigned int ts_count; 197 struct pcf21xx_ts_config ts[PCF2127_MAX_TS_SUPPORTED]; 198 struct attribute_group attribute_group; 199 }; 200 201 struct pcf2127 { 202 struct rtc_device *rtc; 203 struct watchdog_device wdd; 204 struct regmap *regmap; 205 const struct pcf21xx_config *cfg; 206 bool irq_enabled; 207 time64_t ts[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp values. */ 208 bool ts_valid[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp valid indication. */ 209 }; 210 211 /* 212 * In the routines that deal directly with the pcf2127 hardware, we use 213 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 214 */ 215 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 216 { 217 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 218 unsigned char buf[7]; 219 int ret; 220 221 /* 222 * Avoid reading CTRL2 register as it causes WD_VAL register 223 * value to reset to 0 which means watchdog is stopped. 224 */ 225 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->reg_time_base, 226 buf, sizeof(buf)); 227 if (ret) { 228 dev_err(dev, "%s: read error\n", __func__); 229 return ret; 230 } 231 232 /* Clock integrity is not guaranteed when OSF flag is set. */ 233 if (buf[0] & PCF2127_BIT_SC_OSF) { 234 /* 235 * no need clear the flag here, 236 * it will be cleared once the new date is saved 237 */ 238 dev_warn(dev, 239 "oscillator stop detected, date/time is not reliable\n"); 240 return -EINVAL; 241 } 242 243 dev_dbg(dev, 244 "%s: raw data is sec=%02x, min=%02x, hr=%02x, " 245 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 246 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); 247 248 tm->tm_sec = bcd2bin(buf[0] & 0x7F); 249 tm->tm_min = bcd2bin(buf[1] & 0x7F); 250 tm->tm_hour = bcd2bin(buf[2] & 0x3F); 251 tm->tm_mday = bcd2bin(buf[3] & 0x3F); 252 tm->tm_wday = buf[4] & 0x07; 253 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; 254 tm->tm_year = bcd2bin(buf[6]); 255 tm->tm_year += 100; 256 257 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 258 "mday=%d, mon=%d, year=%d, wday=%d\n", 259 __func__, 260 tm->tm_sec, tm->tm_min, tm->tm_hour, 261 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 262 263 return 0; 264 } 265 266 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 267 { 268 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 269 unsigned char buf[7]; 270 int i = 0, err; 271 272 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 273 "mday=%d, mon=%d, year=%d, wday=%d\n", 274 __func__, 275 tm->tm_sec, tm->tm_min, tm->tm_hour, 276 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 277 278 /* hours, minutes and seconds */ 279 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 280 buf[i++] = bin2bcd(tm->tm_min); 281 buf[i++] = bin2bcd(tm->tm_hour); 282 buf[i++] = bin2bcd(tm->tm_mday); 283 buf[i++] = tm->tm_wday & 0x07; 284 285 /* month, 1 - 12 */ 286 buf[i++] = bin2bcd(tm->tm_mon + 1); 287 288 /* year */ 289 buf[i++] = bin2bcd(tm->tm_year - 100); 290 291 /* Write access to time registers: 292 * PCF2127/29: no special action required. 293 * PCF2131: requires setting the STOP and CPR bits. STOP bit needs to 294 * be cleared after time registers are updated. 295 */ 296 if (pcf2127->cfg->type == PCF2131) { 297 err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 298 PCF2127_BIT_CTRL1_STOP, 299 PCF2127_BIT_CTRL1_STOP); 300 if (err) { 301 dev_dbg(dev, "setting STOP bit failed\n"); 302 return err; 303 } 304 305 err = regmap_write(pcf2127->regmap, PCF2131_REG_SR_RESET, 306 PCF2131_SR_RESET_CPR_CMD); 307 if (err) { 308 dev_dbg(dev, "sending CPR cmd failed\n"); 309 return err; 310 } 311 } 312 313 /* write time register's data */ 314 err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i); 315 if (err) { 316 dev_dbg(dev, "%s: err=%d", __func__, err); 317 return err; 318 } 319 320 if (pcf2127->cfg->type == PCF2131) { 321 /* Clear STOP bit (PCF2131 only) after write is completed. */ 322 err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 323 PCF2127_BIT_CTRL1_STOP, 0); 324 if (err) { 325 dev_dbg(dev, "clearing STOP bit failed\n"); 326 return err; 327 } 328 } 329 330 return 0; 331 } 332 333 static int pcf2127_rtc_ioctl(struct device *dev, 334 unsigned int cmd, unsigned long arg) 335 { 336 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 337 int val, touser = 0; 338 int ret; 339 340 switch (cmd) { 341 case RTC_VL_READ: 342 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 343 if (ret) 344 return ret; 345 346 if (val & PCF2127_BIT_CTRL3_BLF) 347 touser |= RTC_VL_BACKUP_LOW; 348 349 if (val & PCF2127_BIT_CTRL3_BF) 350 touser |= RTC_VL_BACKUP_SWITCH; 351 352 return put_user(touser, (unsigned int __user *)arg); 353 354 case RTC_VL_CLR: 355 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 356 PCF2127_BIT_CTRL3_BF, 0); 357 358 default: 359 return -ENOIOCTLCMD; 360 } 361 } 362 363 static int pcf2127_nvmem_read(void *priv, unsigned int offset, 364 void *val, size_t bytes) 365 { 366 struct pcf2127 *pcf2127 = priv; 367 int ret; 368 unsigned char offsetbuf[] = { offset >> 8, offset }; 369 370 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 371 offsetbuf, 2); 372 if (ret) 373 return ret; 374 375 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 376 val, bytes); 377 } 378 379 static int pcf2127_nvmem_write(void *priv, unsigned int offset, 380 void *val, size_t bytes) 381 { 382 struct pcf2127 *pcf2127 = priv; 383 int ret; 384 unsigned char offsetbuf[] = { offset >> 8, offset }; 385 386 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 387 offsetbuf, 2); 388 if (ret) 389 return ret; 390 391 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 392 val, bytes); 393 } 394 395 /* watchdog driver */ 396 397 static int pcf2127_wdt_ping(struct watchdog_device *wdd) 398 { 399 int wd_val; 400 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 401 402 /* 403 * Compute counter value of WATCHDG_TIM_VAL to obtain desired period 404 * in seconds, depending on the source clock frequency. 405 */ 406 wd_val = ((wdd->timeout * pcf2127->cfg->wdd_clock_hz_x1000) / 1000) + 1; 407 408 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wd_val); 409 } 410 411 /* 412 * Restart watchdog timer if feature is active. 413 * 414 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 415 * since register also contain control/status flags for other features. 416 * Always call this function after reading CTRL2 register. 417 */ 418 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 419 { 420 int ret = 0; 421 422 if (watchdog_active(wdd)) { 423 ret = pcf2127_wdt_ping(wdd); 424 if (ret) 425 dev_err(wdd->parent, 426 "%s: watchdog restart failed, ret=%d\n", 427 __func__, ret); 428 } 429 430 return ret; 431 } 432 433 static int pcf2127_wdt_start(struct watchdog_device *wdd) 434 { 435 return pcf2127_wdt_ping(wdd); 436 } 437 438 static int pcf2127_wdt_stop(struct watchdog_device *wdd) 439 { 440 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 441 442 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, 443 PCF2127_WD_VAL_STOP); 444 } 445 446 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 447 unsigned int new_timeout) 448 { 449 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 450 new_timeout, wdd->timeout); 451 452 wdd->timeout = new_timeout; 453 454 return pcf2127_wdt_active_ping(wdd); 455 } 456 457 static const struct watchdog_info pcf2127_wdt_info = { 458 .identity = "NXP PCF2127/PCF2129 Watchdog", 459 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 460 }; 461 462 static const struct watchdog_ops pcf2127_watchdog_ops = { 463 .owner = THIS_MODULE, 464 .start = pcf2127_wdt_start, 465 .stop = pcf2127_wdt_stop, 466 .ping = pcf2127_wdt_ping, 467 .set_timeout = pcf2127_wdt_set_timeout, 468 }; 469 470 /* 471 * Compute watchdog period, t, in seconds, from the WATCHDG_TIM_VAL register 472 * value, n, and the clock frequency, f1000, in Hz x 1000. 473 * 474 * The PCF2127/29 datasheet gives t as: 475 * t = n / f 476 * The PCF2131 datasheet gives t as: 477 * t = (n - 1) / f 478 * For both variants, the watchdog is triggered when the WATCHDG_TIM_VAL reaches 479 * the value 1, and not zero. Consequently, the equation from the PCF2131 480 * datasheet seems to be the correct one for both variants. 481 */ 482 static int pcf2127_watchdog_get_period(int n, int f1000) 483 { 484 return (1000 * (n - 1)) / f1000; 485 } 486 487 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127) 488 { 489 u32 wdd_timeout; 490 int ret; 491 492 if (!IS_ENABLED(CONFIG_WATCHDOG) || 493 !device_property_read_bool(dev, "reset-source")) 494 return 0; 495 496 pcf2127->wdd.parent = dev; 497 pcf2127->wdd.info = &pcf2127_wdt_info; 498 pcf2127->wdd.ops = &pcf2127_watchdog_ops; 499 500 pcf2127->wdd.min_timeout = 501 pcf2127_watchdog_get_period( 502 2, pcf2127->cfg->wdd_clock_hz_x1000); 503 pcf2127->wdd.max_timeout = 504 pcf2127_watchdog_get_period( 505 255, pcf2127->cfg->wdd_clock_hz_x1000); 506 pcf2127->wdd.timeout = PCF2127_WD_DEFAULT_TIMEOUT_S; 507 508 dev_dbg(dev, "%s clock = %d Hz / 1000\n", __func__, 509 pcf2127->cfg->wdd_clock_hz_x1000); 510 511 pcf2127->wdd.min_hw_heartbeat_ms = pcf2127->cfg->wdd_min_hw_heartbeat_ms; 512 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 513 514 watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 515 516 /* Test if watchdog timer is started by bootloader */ 517 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, &wdd_timeout); 518 if (ret) 519 return ret; 520 521 if (wdd_timeout) 522 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 523 524 return devm_watchdog_register_device(dev, &pcf2127->wdd); 525 } 526 527 /* Alarm */ 528 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 529 { 530 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 531 u8 buf[5]; 532 unsigned int ctrl2; 533 int ret; 534 535 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 536 if (ret) 537 return ret; 538 539 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 540 if (ret) 541 return ret; 542 543 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 544 buf, sizeof(buf)); 545 if (ret) 546 return ret; 547 548 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 549 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 550 551 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 552 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 553 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 554 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 555 556 return 0; 557 } 558 559 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 560 { 561 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 562 int ret; 563 564 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 565 PCF2127_BIT_CTRL2_AIE, 566 enable ? PCF2127_BIT_CTRL2_AIE : 0); 567 if (ret) 568 return ret; 569 570 return pcf2127_wdt_active_ping(&pcf2127->wdd); 571 } 572 573 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 574 { 575 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 576 uint8_t buf[5]; 577 int ret; 578 579 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 580 PCF2127_BIT_CTRL2_AF, 0); 581 if (ret) 582 return ret; 583 584 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 585 if (ret) 586 return ret; 587 588 buf[0] = bin2bcd(alrm->time.tm_sec); 589 buf[1] = bin2bcd(alrm->time.tm_min); 590 buf[2] = bin2bcd(alrm->time.tm_hour); 591 buf[3] = bin2bcd(alrm->time.tm_mday); 592 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 593 594 ret = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 595 buf, sizeof(buf)); 596 if (ret) 597 return ret; 598 599 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 600 } 601 602 /* 603 * This function reads one timestamp function data, caller is responsible for 604 * calling pcf2127_wdt_active_ping() 605 */ 606 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts, 607 int ts_id) 608 { 609 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 610 struct rtc_time tm; 611 int ret; 612 unsigned char data[7]; 613 614 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->ts[ts_id].reg_base, 615 data, sizeof(data)); 616 if (ret) { 617 dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 618 return ret; 619 } 620 621 dev_dbg(dev, 622 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 623 __func__, data[1], data[2], data[3], data[4], data[5], data[6]); 624 625 tm.tm_sec = bcd2bin(data[1] & 0x7F); 626 tm.tm_min = bcd2bin(data[2] & 0x7F); 627 tm.tm_hour = bcd2bin(data[3] & 0x3F); 628 tm.tm_mday = bcd2bin(data[4] & 0x3F); 629 /* TS_MO register (month) value range: 1-12 */ 630 tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1; 631 tm.tm_year = bcd2bin(data[6]); 632 if (tm.tm_year < 70) 633 tm.tm_year += 100; /* assume we are in 1970...2069 */ 634 635 ret = rtc_valid_tm(&tm); 636 if (ret) { 637 dev_err(dev, "Invalid timestamp. ret=%d\n", ret); 638 return ret; 639 } 640 641 *ts = rtc_tm_to_time64(&tm); 642 return 0; 643 }; 644 645 static void pcf2127_rtc_ts_snapshot(struct device *dev, int ts_id) 646 { 647 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 648 int ret; 649 650 if (ts_id >= pcf2127->cfg->ts_count) 651 return; 652 653 /* Let userspace read the first timestamp */ 654 if (pcf2127->ts_valid[ts_id]) 655 return; 656 657 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id); 658 if (!ret) 659 pcf2127->ts_valid[ts_id] = true; 660 } 661 662 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 663 { 664 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 665 unsigned int ctrl2; 666 int ret = 0; 667 668 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 669 if (ret) 670 return IRQ_NONE; 671 672 if (pcf2127->cfg->ts_count == 1) { 673 /* PCF2127/29 */ 674 unsigned int ctrl1; 675 676 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 677 if (ret) 678 return IRQ_NONE; 679 680 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) 681 return IRQ_NONE; 682 683 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) 684 pcf2127_rtc_ts_snapshot(dev, 0); 685 686 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) 687 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, 688 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); 689 690 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) 691 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 692 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); 693 } else { 694 /* PCF2131. */ 695 unsigned int ctrl4; 696 697 ret = regmap_read(pcf2127->regmap, PCF2131_REG_CTRL4, &ctrl4); 698 if (ret) 699 return IRQ_NONE; 700 701 if (!(ctrl4 & PCF2131_CTRL4_IRQ_MASK || ctrl2 & PCF2131_CTRL2_IRQ_MASK)) 702 return IRQ_NONE; 703 704 if (ctrl4 & PCF2131_CTRL4_IRQ_MASK) { 705 int i; 706 int tsf_bit = PCF2131_BIT_CTRL4_TSF1; /* Start at bit 7. */ 707 708 for (i = 0; i < pcf2127->cfg->ts_count; i++) { 709 if (ctrl4 & tsf_bit) 710 pcf2127_rtc_ts_snapshot(dev, i); 711 712 tsf_bit = tsf_bit >> 1; 713 } 714 715 regmap_write(pcf2127->regmap, PCF2131_REG_CTRL4, 716 ctrl4 & ~PCF2131_CTRL4_IRQ_MASK); 717 } 718 719 if (ctrl2 & PCF2131_CTRL2_IRQ_MASK) 720 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 721 ctrl2 & ~PCF2131_CTRL2_IRQ_MASK); 722 } 723 724 if (ctrl2 & PCF2127_BIT_CTRL2_AF) 725 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 726 727 pcf2127_wdt_active_ping(&pcf2127->wdd); 728 729 return IRQ_HANDLED; 730 } 731 732 static const struct rtc_class_ops pcf2127_rtc_ops = { 733 .ioctl = pcf2127_rtc_ioctl, 734 .read_time = pcf2127_rtc_read_time, 735 .set_time = pcf2127_rtc_set_time, 736 .read_alarm = pcf2127_rtc_read_alarm, 737 .set_alarm = pcf2127_rtc_set_alarm, 738 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 739 }; 740 741 /* sysfs interface */ 742 743 static ssize_t timestamp_store(struct device *dev, 744 struct device_attribute *attr, 745 const char *buf, size_t count, int ts_id) 746 { 747 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 748 int ret; 749 750 if (ts_id >= pcf2127->cfg->ts_count) 751 return 0; 752 753 if (pcf2127->irq_enabled) { 754 pcf2127->ts_valid[ts_id] = false; 755 } else { 756 /* Always clear GND interrupt bit. */ 757 ret = regmap_update_bits(pcf2127->regmap, 758 pcf2127->cfg->ts[ts_id].gnd_detect_reg, 759 pcf2127->cfg->ts[ts_id].gnd_detect_bit, 760 0); 761 762 if (ret) { 763 dev_err(dev, "%s: update TS gnd detect ret=%d\n", __func__, ret); 764 return ret; 765 } 766 767 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) { 768 /* Clear intermediate level interrupt bit if supported. */ 769 ret = regmap_update_bits(pcf2127->regmap, 770 pcf2127->cfg->ts[ts_id].inter_detect_reg, 771 pcf2127->cfg->ts[ts_id].inter_detect_bit, 772 0); 773 if (ret) { 774 dev_err(dev, "%s: update TS intermediate level detect ret=%d\n", 775 __func__, ret); 776 return ret; 777 } 778 } 779 780 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 781 if (ret) 782 return ret; 783 } 784 785 return count; 786 } 787 788 static ssize_t timestamp0_store(struct device *dev, 789 struct device_attribute *attr, 790 const char *buf, size_t count) 791 { 792 return timestamp_store(dev, attr, buf, count, 0); 793 }; 794 795 static ssize_t timestamp1_store(struct device *dev, 796 struct device_attribute *attr, 797 const char *buf, size_t count) 798 { 799 return timestamp_store(dev, attr, buf, count, 1); 800 }; 801 802 static ssize_t timestamp2_store(struct device *dev, 803 struct device_attribute *attr, 804 const char *buf, size_t count) 805 { 806 return timestamp_store(dev, attr, buf, count, 2); 807 }; 808 809 static ssize_t timestamp3_store(struct device *dev, 810 struct device_attribute *attr, 811 const char *buf, size_t count) 812 { 813 return timestamp_store(dev, attr, buf, count, 3); 814 }; 815 816 static ssize_t timestamp_show(struct device *dev, 817 struct device_attribute *attr, char *buf, 818 int ts_id) 819 { 820 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 821 int ret; 822 time64_t ts; 823 824 if (ts_id >= pcf2127->cfg->ts_count) 825 return 0; 826 827 if (pcf2127->irq_enabled) { 828 if (!pcf2127->ts_valid[ts_id]) 829 return 0; 830 ts = pcf2127->ts[ts_id]; 831 } else { 832 u8 valid_low = 0; 833 u8 valid_inter = 0; 834 unsigned int ctrl; 835 836 /* Check if TS input pin is driven to GND, supported by all 837 * variants. 838 */ 839 ret = regmap_read(pcf2127->regmap, 840 pcf2127->cfg->ts[ts_id].gnd_detect_reg, 841 &ctrl); 842 if (ret) 843 return 0; 844 845 valid_low = ctrl & pcf2127->cfg->ts[ts_id].gnd_detect_bit; 846 847 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) { 848 /* Check if TS input pin is driven to intermediate level 849 * between GND and supply, if supported by variant. 850 */ 851 ret = regmap_read(pcf2127->regmap, 852 pcf2127->cfg->ts[ts_id].inter_detect_reg, 853 &ctrl); 854 if (ret) 855 return 0; 856 857 valid_inter = ctrl & pcf2127->cfg->ts[ts_id].inter_detect_bit; 858 } 859 860 if (!valid_low && !valid_inter) 861 return 0; 862 863 ret = pcf2127_rtc_ts_read(dev->parent, &ts, ts_id); 864 if (ret) 865 return 0; 866 867 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 868 if (ret) 869 return ret; 870 } 871 return sprintf(buf, "%llu\n", (unsigned long long)ts); 872 } 873 874 static ssize_t timestamp0_show(struct device *dev, 875 struct device_attribute *attr, char *buf) 876 { 877 return timestamp_show(dev, attr, buf, 0); 878 }; 879 880 static ssize_t timestamp1_show(struct device *dev, 881 struct device_attribute *attr, char *buf) 882 { 883 return timestamp_show(dev, attr, buf, 1); 884 }; 885 886 static ssize_t timestamp2_show(struct device *dev, 887 struct device_attribute *attr, char *buf) 888 { 889 return timestamp_show(dev, attr, buf, 2); 890 }; 891 892 static ssize_t timestamp3_show(struct device *dev, 893 struct device_attribute *attr, char *buf) 894 { 895 return timestamp_show(dev, attr, buf, 3); 896 }; 897 898 static DEVICE_ATTR_RW(timestamp0); 899 static DEVICE_ATTR_RW(timestamp1); 900 static DEVICE_ATTR_RW(timestamp2); 901 static DEVICE_ATTR_RW(timestamp3); 902 903 static struct attribute *pcf2127_attrs[] = { 904 &dev_attr_timestamp0.attr, 905 NULL 906 }; 907 908 static struct attribute *pcf2131_attrs[] = { 909 &dev_attr_timestamp0.attr, 910 &dev_attr_timestamp1.attr, 911 &dev_attr_timestamp2.attr, 912 &dev_attr_timestamp3.attr, 913 NULL 914 }; 915 916 static struct pcf21xx_config pcf21xx_cfg[] = { 917 [PCF2127] = { 918 .type = PCF2127, 919 .max_register = 0x1d, 920 .has_nvmem = 1, 921 .has_bit_wd_ctl_cd0 = 1, 922 .has_int_a_b = 0, 923 .reg_time_base = PCF2127_REG_TIME_BASE, 924 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 925 .reg_wd_ctl = PCF2127_REG_WD_CTL, 926 .reg_wd_val = PCF2127_REG_WD_VAL, 927 .reg_clkout = PCF2127_REG_CLKOUT, 928 .wdd_clock_hz_x1000 = PCF2127_WD_CLOCK_HZ_X1000, 929 .wdd_min_hw_heartbeat_ms = PCF2127_WD_MIN_HW_HEARTBEAT_MS, 930 .ts_count = 1, 931 .ts[0] = { 932 .reg_base = PCF2127_REG_TS1_BASE, 933 .gnd_detect_reg = PCF2127_REG_CTRL1, 934 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1, 935 .inter_detect_reg = PCF2127_REG_CTRL2, 936 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2, 937 .ie_reg = PCF2127_REG_CTRL2, 938 .ie_bit = PCF2127_BIT_CTRL2_TSIE, 939 }, 940 .attribute_group = { 941 .attrs = pcf2127_attrs, 942 }, 943 }, 944 [PCF2129] = { 945 .type = PCF2129, 946 .max_register = 0x19, 947 .has_nvmem = 0, 948 .has_bit_wd_ctl_cd0 = 0, 949 .has_int_a_b = 0, 950 .reg_time_base = PCF2127_REG_TIME_BASE, 951 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 952 .reg_wd_ctl = PCF2127_REG_WD_CTL, 953 .reg_wd_val = PCF2127_REG_WD_VAL, 954 .reg_clkout = PCF2127_REG_CLKOUT, 955 .wdd_clock_hz_x1000 = PCF2127_WD_CLOCK_HZ_X1000, 956 .wdd_min_hw_heartbeat_ms = PCF2127_WD_MIN_HW_HEARTBEAT_MS, 957 .ts_count = 1, 958 .ts[0] = { 959 .reg_base = PCF2127_REG_TS1_BASE, 960 .gnd_detect_reg = PCF2127_REG_CTRL1, 961 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1, 962 .inter_detect_reg = PCF2127_REG_CTRL2, 963 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2, 964 .ie_reg = PCF2127_REG_CTRL2, 965 .ie_bit = PCF2127_BIT_CTRL2_TSIE, 966 }, 967 .attribute_group = { 968 .attrs = pcf2127_attrs, 969 }, 970 }, 971 [PCF2131] = { 972 .type = PCF2131, 973 .max_register = 0x36, 974 .has_nvmem = 0, 975 .has_bit_wd_ctl_cd0 = 0, 976 .has_int_a_b = 1, 977 .reg_time_base = PCF2131_REG_TIME_BASE, 978 .regs_alarm_base = PCF2131_REG_ALARM_BASE, 979 .reg_wd_ctl = PCF2131_REG_WD_CTL, 980 .reg_wd_val = PCF2131_REG_WD_VAL, 981 .reg_clkout = PCF2131_REG_CLKOUT, 982 .wdd_clock_hz_x1000 = PCF2131_WD_CLOCK_HZ_X1000, 983 .wdd_min_hw_heartbeat_ms = PCF2131_WD_MIN_HW_HEARTBEAT_MS, 984 .ts_count = 4, 985 .ts[0] = { 986 .reg_base = PCF2131_REG_TS1_BASE, 987 .gnd_detect_reg = PCF2131_REG_CTRL4, 988 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF1, 989 .inter_detect_bit = 0, 990 .ie_reg = PCF2131_REG_CTRL5, 991 .ie_bit = PCF2131_BIT_CTRL5_TSIE1, 992 }, 993 .ts[1] = { 994 .reg_base = PCF2131_REG_TS2_BASE, 995 .gnd_detect_reg = PCF2131_REG_CTRL4, 996 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF2, 997 .inter_detect_bit = 0, 998 .ie_reg = PCF2131_REG_CTRL5, 999 .ie_bit = PCF2131_BIT_CTRL5_TSIE2, 1000 }, 1001 .ts[2] = { 1002 .reg_base = PCF2131_REG_TS3_BASE, 1003 .gnd_detect_reg = PCF2131_REG_CTRL4, 1004 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF3, 1005 .inter_detect_bit = 0, 1006 .ie_reg = PCF2131_REG_CTRL5, 1007 .ie_bit = PCF2131_BIT_CTRL5_TSIE3, 1008 }, 1009 .ts[3] = { 1010 .reg_base = PCF2131_REG_TS4_BASE, 1011 .gnd_detect_reg = PCF2131_REG_CTRL4, 1012 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF4, 1013 .inter_detect_bit = 0, 1014 .ie_reg = PCF2131_REG_CTRL5, 1015 .ie_bit = PCF2131_BIT_CTRL5_TSIE4, 1016 }, 1017 .attribute_group = { 1018 .attrs = pcf2131_attrs, 1019 }, 1020 }, 1021 }; 1022 1023 /* 1024 * Enable timestamp function and corresponding interrupt(s). 1025 */ 1026 static int pcf2127_enable_ts(struct device *dev, int ts_id) 1027 { 1028 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 1029 int ret; 1030 1031 if (ts_id >= pcf2127->cfg->ts_count) { 1032 dev_err(dev, "%s: invalid tamper detection ID (%d)\n", 1033 __func__, ts_id); 1034 return -EINVAL; 1035 } 1036 1037 /* Enable timestamp function. */ 1038 ret = regmap_update_bits(pcf2127->regmap, 1039 pcf2127->cfg->ts[ts_id].reg_base, 1040 PCF2127_BIT_TS_CTRL_TSOFF | 1041 PCF2127_BIT_TS_CTRL_TSM, 1042 PCF2127_BIT_TS_CTRL_TSM); 1043 if (ret) { 1044 dev_err(dev, "%s: tamper detection config (ts%d_ctrl) failed\n", 1045 __func__, ts_id); 1046 return ret; 1047 } 1048 1049 /* TS input pin driven to GND detection is supported by all variants. 1050 * Make sure that interrupt bit is defined. 1051 */ 1052 if (pcf2127->cfg->ts[ts_id].gnd_detect_bit == 0) { 1053 dev_err(dev, "%s: tamper detection to GND configuration invalid\n", 1054 __func__); 1055 return ret; 1056 } 1057 1058 /* 1059 * Enable interrupt generation when TSF timestamp flag is set. 1060 * Interrupt signals are open-drain outputs and can be left floating if 1061 * unused. 1062 */ 1063 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->ts[ts_id].ie_reg, 1064 pcf2127->cfg->ts[ts_id].ie_bit, 1065 pcf2127->cfg->ts[ts_id].ie_bit); 1066 if (ret) { 1067 dev_err(dev, "%s: tamper detection TSIE%d config failed\n", 1068 __func__, ts_id); 1069 return ret; 1070 } 1071 1072 return ret; 1073 } 1074 1075 /* Route all interrupt sources to INT A pin. */ 1076 static int pcf2127_configure_interrupt_pins(struct device *dev) 1077 { 1078 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 1079 int ret; 1080 1081 /* Mask bits need to be cleared to enable corresponding 1082 * interrupt source. 1083 */ 1084 ret = regmap_write(pcf2127->regmap, 1085 PCF2131_REG_INT_A_MASK1, 0); 1086 if (ret) 1087 return ret; 1088 1089 ret = regmap_write(pcf2127->regmap, 1090 PCF2131_REG_INT_A_MASK2, 0); 1091 if (ret) 1092 return ret; 1093 1094 return ret; 1095 } 1096 1097 static int pcf2127_probe(struct device *dev, struct regmap *regmap, 1098 int alarm_irq, const char *name, const struct pcf21xx_config *config) 1099 { 1100 struct pcf2127 *pcf2127; 1101 int ret = 0; 1102 unsigned int val; 1103 1104 dev_dbg(dev, "%s\n", __func__); 1105 1106 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 1107 if (!pcf2127) 1108 return -ENOMEM; 1109 1110 pcf2127->regmap = regmap; 1111 pcf2127->cfg = config; 1112 1113 dev_set_drvdata(dev, pcf2127); 1114 1115 pcf2127->rtc = devm_rtc_allocate_device(dev); 1116 if (IS_ERR(pcf2127->rtc)) 1117 return PTR_ERR(pcf2127->rtc); 1118 1119 pcf2127->rtc->ops = &pcf2127_rtc_ops; 1120 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 1121 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 1122 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 1123 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features); 1124 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features); 1125 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 1126 1127 if (alarm_irq > 0) { 1128 unsigned long flags; 1129 1130 /* 1131 * If flags = 0, devm_request_threaded_irq() will use IRQ flags 1132 * obtained from device tree. 1133 */ 1134 if (dev_fwnode(dev)) 1135 flags = 0; 1136 else 1137 flags = IRQF_TRIGGER_LOW; 1138 1139 ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 1140 pcf2127_rtc_irq, 1141 flags | IRQF_ONESHOT, 1142 dev_name(dev), dev); 1143 if (ret) { 1144 dev_err(dev, "failed to request alarm irq\n"); 1145 return ret; 1146 } 1147 pcf2127->irq_enabled = true; 1148 } 1149 1150 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 1151 device_init_wakeup(dev, true); 1152 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 1153 } 1154 1155 if (pcf2127->cfg->has_int_a_b) { 1156 /* Configure int A/B pins, independently of alarm_irq. */ 1157 ret = pcf2127_configure_interrupt_pins(dev); 1158 if (ret) { 1159 dev_err(dev, "failed to configure interrupt pins\n"); 1160 return ret; 1161 } 1162 } 1163 1164 if (pcf2127->cfg->has_nvmem) { 1165 struct nvmem_config nvmem_cfg = { 1166 .priv = pcf2127, 1167 .reg_read = pcf2127_nvmem_read, 1168 .reg_write = pcf2127_nvmem_write, 1169 .size = 512, 1170 }; 1171 1172 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 1173 } 1174 1175 /* 1176 * The "Power-On Reset Override" facility prevents the RTC to do a reset 1177 * after power on. For normal operation the PORO must be disabled. 1178 */ 1179 regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 1180 PCF2127_BIT_CTRL1_POR_OVRD); 1181 1182 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_clkout, &val); 1183 if (ret < 0) 1184 return ret; 1185 1186 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 1187 ret = regmap_set_bits(pcf2127->regmap, pcf2127->cfg->reg_clkout, 1188 PCF2127_BIT_CLKOUT_OTPR); 1189 if (ret < 0) 1190 return ret; 1191 1192 msleep(100); 1193 } 1194 1195 /* 1196 * Watchdog timer enabled and reset pin /RST activated when timed out. 1197 * Select 1Hz clock source for watchdog timer (1/4Hz for PCF2131). 1198 * Note: Countdown timer disabled and not available. 1199 * For pca2129, pcf2129 and pcf2131, only bit[7] is for Symbol WD_CD 1200 * of register watchdg_tim_ctl. The bit[6] is labeled 1201 * as T. Bits labeled as T must always be written with 1202 * logic 0. 1203 */ 1204 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl, 1205 PCF2127_BIT_WD_CTL_CD1 | 1206 PCF2127_BIT_WD_CTL_CD0 | 1207 PCF2127_BIT_WD_CTL_TF1 | 1208 PCF2127_BIT_WD_CTL_TF0, 1209 PCF2127_BIT_WD_CTL_CD1 | 1210 (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 1211 PCF2127_BIT_WD_CTL_TF1); 1212 if (ret) { 1213 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 1214 return ret; 1215 } 1216 1217 pcf2127_watchdog_init(dev, pcf2127); 1218 1219 /* 1220 * Disable battery low/switch-over timestamp and interrupts. 1221 * Clear battery interrupt flags which can block new trigger events. 1222 * Note: This is the default chip behaviour but added to ensure 1223 * correct tamper timestamp and interrupt function. 1224 */ 1225 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 1226 PCF2127_BIT_CTRL3_BTSE | 1227 PCF2127_BIT_CTRL3_BIE | 1228 PCF2127_BIT_CTRL3_BLIE, 0); 1229 if (ret) { 1230 dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 1231 __func__); 1232 return ret; 1233 } 1234 1235 /* 1236 * Enable timestamp functions 1 to 4. 1237 */ 1238 for (int i = 0; i < pcf2127->cfg->ts_count; i++) { 1239 ret = pcf2127_enable_ts(dev, i); 1240 if (ret) 1241 return ret; 1242 } 1243 1244 ret = rtc_add_group(pcf2127->rtc, &pcf2127->cfg->attribute_group); 1245 if (ret) { 1246 dev_err(dev, "%s: tamper sysfs registering failed\n", 1247 __func__); 1248 return ret; 1249 } 1250 1251 return devm_rtc_register_device(pcf2127->rtc); 1252 } 1253 1254 #ifdef CONFIG_OF 1255 static const struct of_device_id pcf2127_of_match[] = { 1256 { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] }, 1257 { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] }, 1258 { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] }, 1259 { .compatible = "nxp,pcf2131", .data = &pcf21xx_cfg[PCF2131] }, 1260 {} 1261 }; 1262 MODULE_DEVICE_TABLE(of, pcf2127_of_match); 1263 #endif 1264 1265 #if IS_ENABLED(CONFIG_I2C) 1266 1267 static int pcf2127_i2c_write(void *context, const void *data, size_t count) 1268 { 1269 struct device *dev = context; 1270 struct i2c_client *client = to_i2c_client(dev); 1271 int ret; 1272 1273 ret = i2c_master_send(client, data, count); 1274 if (ret != count) 1275 return ret < 0 ? ret : -EIO; 1276 1277 return 0; 1278 } 1279 1280 static int pcf2127_i2c_gather_write(void *context, 1281 const void *reg, size_t reg_size, 1282 const void *val, size_t val_size) 1283 { 1284 struct device *dev = context; 1285 struct i2c_client *client = to_i2c_client(dev); 1286 int ret; 1287 void *buf; 1288 1289 if (WARN_ON(reg_size != 1)) 1290 return -EINVAL; 1291 1292 buf = kmalloc(val_size + 1, GFP_KERNEL); 1293 if (!buf) 1294 return -ENOMEM; 1295 1296 memcpy(buf, reg, 1); 1297 memcpy(buf + 1, val, val_size); 1298 1299 ret = i2c_master_send(client, buf, val_size + 1); 1300 1301 kfree(buf); 1302 1303 if (ret != val_size + 1) 1304 return ret < 0 ? ret : -EIO; 1305 1306 return 0; 1307 } 1308 1309 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 1310 void *val, size_t val_size) 1311 { 1312 struct device *dev = context; 1313 struct i2c_client *client = to_i2c_client(dev); 1314 int ret; 1315 1316 if (WARN_ON(reg_size != 1)) 1317 return -EINVAL; 1318 1319 ret = i2c_master_send(client, reg, 1); 1320 if (ret != 1) 1321 return ret < 0 ? ret : -EIO; 1322 1323 ret = i2c_master_recv(client, val, val_size); 1324 if (ret != val_size) 1325 return ret < 0 ? ret : -EIO; 1326 1327 return 0; 1328 } 1329 1330 /* 1331 * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 1332 * is that the STOP condition is required between set register address and 1333 * read register data when reading from registers. 1334 */ 1335 static const struct regmap_bus pcf2127_i2c_regmap = { 1336 .write = pcf2127_i2c_write, 1337 .gather_write = pcf2127_i2c_gather_write, 1338 .read = pcf2127_i2c_read, 1339 }; 1340 1341 static struct i2c_driver pcf2127_i2c_driver; 1342 1343 static const struct i2c_device_id pcf2127_i2c_id[] = { 1344 { "pcf2127", PCF2127 }, 1345 { "pcf2129", PCF2129 }, 1346 { "pca2129", PCF2129 }, 1347 { "pcf2131", PCF2131 }, 1348 { } 1349 }; 1350 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 1351 1352 static int pcf2127_i2c_probe(struct i2c_client *client) 1353 { 1354 struct regmap *regmap; 1355 static struct regmap_config config = { 1356 .reg_bits = 8, 1357 .val_bits = 8, 1358 }; 1359 const struct pcf21xx_config *variant; 1360 1361 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 1362 return -ENODEV; 1363 1364 if (client->dev.of_node) { 1365 variant = of_device_get_match_data(&client->dev); 1366 if (!variant) 1367 return -ENODEV; 1368 } else { 1369 enum pcf21xx_type type = 1370 i2c_match_id(pcf2127_i2c_id, client)->driver_data; 1371 1372 if (type >= PCF21XX_LAST_ID) 1373 return -ENODEV; 1374 variant = &pcf21xx_cfg[type]; 1375 } 1376 1377 config.max_register = variant->max_register, 1378 1379 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 1380 &client->dev, &config); 1381 if (IS_ERR(regmap)) { 1382 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 1383 __func__, PTR_ERR(regmap)); 1384 return PTR_ERR(regmap); 1385 } 1386 1387 return pcf2127_probe(&client->dev, regmap, client->irq, 1388 pcf2127_i2c_driver.driver.name, variant); 1389 } 1390 1391 static struct i2c_driver pcf2127_i2c_driver = { 1392 .driver = { 1393 .name = "rtc-pcf2127-i2c", 1394 .of_match_table = of_match_ptr(pcf2127_of_match), 1395 }, 1396 .probe = pcf2127_i2c_probe, 1397 .id_table = pcf2127_i2c_id, 1398 }; 1399 1400 static int pcf2127_i2c_register_driver(void) 1401 { 1402 return i2c_add_driver(&pcf2127_i2c_driver); 1403 } 1404 1405 static void pcf2127_i2c_unregister_driver(void) 1406 { 1407 i2c_del_driver(&pcf2127_i2c_driver); 1408 } 1409 1410 #else 1411 1412 static int pcf2127_i2c_register_driver(void) 1413 { 1414 return 0; 1415 } 1416 1417 static void pcf2127_i2c_unregister_driver(void) 1418 { 1419 } 1420 1421 #endif 1422 1423 #if IS_ENABLED(CONFIG_SPI_MASTER) 1424 1425 static struct spi_driver pcf2127_spi_driver; 1426 static const struct spi_device_id pcf2127_spi_id[]; 1427 1428 static int pcf2127_spi_probe(struct spi_device *spi) 1429 { 1430 static struct regmap_config config = { 1431 .reg_bits = 8, 1432 .val_bits = 8, 1433 .read_flag_mask = 0xa0, 1434 .write_flag_mask = 0x20, 1435 }; 1436 struct regmap *regmap; 1437 const struct pcf21xx_config *variant; 1438 1439 if (spi->dev.of_node) { 1440 variant = of_device_get_match_data(&spi->dev); 1441 if (!variant) 1442 return -ENODEV; 1443 } else { 1444 enum pcf21xx_type type = spi_get_device_id(spi)->driver_data; 1445 1446 if (type >= PCF21XX_LAST_ID) 1447 return -ENODEV; 1448 variant = &pcf21xx_cfg[type]; 1449 } 1450 1451 config.max_register = variant->max_register, 1452 1453 regmap = devm_regmap_init_spi(spi, &config); 1454 if (IS_ERR(regmap)) { 1455 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 1456 __func__, PTR_ERR(regmap)); 1457 return PTR_ERR(regmap); 1458 } 1459 1460 return pcf2127_probe(&spi->dev, regmap, spi->irq, 1461 pcf2127_spi_driver.driver.name, 1462 variant); 1463 } 1464 1465 static const struct spi_device_id pcf2127_spi_id[] = { 1466 { "pcf2127", PCF2127 }, 1467 { "pcf2129", PCF2129 }, 1468 { "pca2129", PCF2129 }, 1469 { "pcf2131", PCF2131 }, 1470 { } 1471 }; 1472 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 1473 1474 static struct spi_driver pcf2127_spi_driver = { 1475 .driver = { 1476 .name = "rtc-pcf2127-spi", 1477 .of_match_table = of_match_ptr(pcf2127_of_match), 1478 }, 1479 .probe = pcf2127_spi_probe, 1480 .id_table = pcf2127_spi_id, 1481 }; 1482 1483 static int pcf2127_spi_register_driver(void) 1484 { 1485 return spi_register_driver(&pcf2127_spi_driver); 1486 } 1487 1488 static void pcf2127_spi_unregister_driver(void) 1489 { 1490 spi_unregister_driver(&pcf2127_spi_driver); 1491 } 1492 1493 #else 1494 1495 static int pcf2127_spi_register_driver(void) 1496 { 1497 return 0; 1498 } 1499 1500 static void pcf2127_spi_unregister_driver(void) 1501 { 1502 } 1503 1504 #endif 1505 1506 static int __init pcf2127_init(void) 1507 { 1508 int ret; 1509 1510 ret = pcf2127_i2c_register_driver(); 1511 if (ret) { 1512 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 1513 return ret; 1514 } 1515 1516 ret = pcf2127_spi_register_driver(); 1517 if (ret) { 1518 pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 1519 pcf2127_i2c_unregister_driver(); 1520 } 1521 1522 return ret; 1523 } 1524 module_init(pcf2127_init) 1525 1526 static void __exit pcf2127_exit(void) 1527 { 1528 pcf2127_spi_unregister_driver(); 1529 pcf2127_i2c_unregister_driver(); 1530 } 1531 module_exit(pcf2127_exit) 1532 1533 MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>"); 1534 MODULE_DESCRIPTION("NXP PCF2127/29/31 RTC driver"); 1535 MODULE_LICENSE("GPL v2"); 1536