1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * NVIDIA Voltage Regulator Specification RTC 4 * 5 * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. 6 * All rights reserved. 7 */ 8 9 #include <linux/bits.h> 10 #include <linux/err.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/module.h> 14 #include <linux/rtc.h> 15 16 #define NVVRS_REG_VENDOR_ID 0x00 17 #define NVVRS_REG_MODEL_REV 0x01 18 19 /* Interrupts registers */ 20 #define NVVRS_REG_INT_SRC1 0x10 21 #define NVVRS_REG_INT_SRC2 0x11 22 #define NVVRS_REG_INT_VENDOR 0x12 23 24 /* Control Registers */ 25 #define NVVRS_REG_CTL_1 0x28 26 #define NVVRS_REG_CTL_2 0x29 27 28 /* RTC Registers */ 29 #define NVVRS_REG_RTC_T3 0x70 30 #define NVVRS_REG_RTC_T2 0x71 31 #define NVVRS_REG_RTC_T1 0x72 32 #define NVVRS_REG_RTC_T0 0x73 33 #define NVVRS_REG_RTC_A3 0x74 34 #define NVVRS_REG_RTC_A2 0x75 35 #define NVVRS_REG_RTC_A1 0x76 36 #define NVVRS_REG_RTC_A0 0x77 37 38 /* Interrupt Mask */ 39 #define NVVRS_INT_SRC1_RSTIRQ_MASK BIT(0) 40 #define NVVRS_INT_SRC1_OSC_MASK BIT(1) 41 #define NVVRS_INT_SRC1_EN_MASK BIT(2) 42 #define NVVRS_INT_SRC1_RTC_MASK BIT(3) 43 #define NVVRS_INT_SRC1_PEC_MASK BIT(4) 44 #define NVVRS_INT_SRC1_WDT_MASK BIT(5) 45 #define NVVRS_INT_SRC1_EM_PD_MASK BIT(6) 46 #define NVVRS_INT_SRC1_INTERNAL_MASK BIT(7) 47 #define NVVRS_INT_SRC2_PBSP_MASK BIT(0) 48 #define NVVRS_INT_SRC2_ECC_DED_MASK BIT(1) 49 #define NVVRS_INT_SRC2_TSD_MASK BIT(2) 50 #define NVVRS_INT_SRC2_LDO_MASK BIT(3) 51 #define NVVRS_INT_SRC2_BIST_MASK BIT(4) 52 #define NVVRS_INT_SRC2_RT_CRC_MASK BIT(5) 53 #define NVVRS_INT_SRC2_VENDOR_MASK BIT(7) 54 #define NVVRS_INT_VENDOR0_MASK BIT(0) 55 #define NVVRS_INT_VENDOR1_MASK BIT(1) 56 #define NVVRS_INT_VENDOR2_MASK BIT(2) 57 #define NVVRS_INT_VENDOR3_MASK BIT(3) 58 #define NVVRS_INT_VENDOR4_MASK BIT(4) 59 #define NVVRS_INT_VENDOR5_MASK BIT(5) 60 #define NVVRS_INT_VENDOR6_MASK BIT(6) 61 #define NVVRS_INT_VENDOR7_MASK BIT(7) 62 63 /* Controller Register Mask */ 64 #define NVVRS_REG_CTL_1_FORCE_SHDN (BIT(0) | BIT(1)) 65 #define NVVRS_REG_CTL_1_FORCE_ACT BIT(2) 66 #define NVVRS_REG_CTL_1_FORCE_INT BIT(3) 67 #define NVVRS_REG_CTL_2_EN_PEC BIT(0) 68 #define NVVRS_REG_CTL_2_REQ_PEC BIT(1) 69 #define NVVRS_REG_CTL_2_RTC_PU BIT(2) 70 #define NVVRS_REG_CTL_2_RTC_WAKE BIT(3) 71 #define NVVRS_REG_CTL_2_RST_DLY 0xF0 72 73 #define ALARM_RESET_VAL 0xffffffff 74 #define NVVRS_MIN_MODEL_REV 0x40 75 76 enum nvvrs_irq_regs { 77 NVVRS_IRQ_REG_INT_SRC1 = 0, 78 NVVRS_IRQ_REG_INT_SRC2 = 1, 79 NVVRS_IRQ_REG_INT_VENDOR = 2, 80 NVVRS_IRQ_REG_COUNT = 3, 81 }; 82 83 struct nvvrs_rtc_info { 84 struct device *dev; 85 struct i2c_client *client; 86 struct rtc_device *rtc; 87 unsigned int irq; 88 }; 89 90 static int nvvrs_update_bits(struct nvvrs_rtc_info *info, u8 reg, 91 u8 mask, u8 value) 92 { 93 int ret; 94 u8 val; 95 96 ret = i2c_smbus_read_byte_data(info->client, reg); 97 if (ret < 0) 98 return ret; 99 100 val = (u8)ret; 101 val &= ~mask; 102 val |= (value & mask); 103 104 return i2c_smbus_write_byte_data(info->client, reg, val); 105 } 106 107 static int nvvrs_rtc_write_alarm(struct i2c_client *client, u8 *time) 108 { 109 int ret; 110 111 ret = i2c_smbus_write_byte_data(client, NVVRS_REG_RTC_A3, time[3]); 112 if (ret < 0) 113 return ret; 114 115 ret = i2c_smbus_write_byte_data(client, NVVRS_REG_RTC_A2, time[2]); 116 if (ret < 0) 117 return ret; 118 119 ret = i2c_smbus_write_byte_data(client, NVVRS_REG_RTC_A1, time[1]); 120 if (ret < 0) 121 return ret; 122 123 return i2c_smbus_write_byte_data(client, NVVRS_REG_RTC_A0, time[0]); 124 } 125 126 static int nvvrs_rtc_enable_alarm(struct nvvrs_rtc_info *info) 127 { 128 int ret; 129 130 /* Set RTC_WAKE bit for autonomous wake from sleep */ 131 ret = nvvrs_update_bits(info, NVVRS_REG_CTL_2, NVVRS_REG_CTL_2_RTC_WAKE, 132 NVVRS_REG_CTL_2_RTC_WAKE); 133 if (ret < 0) 134 return ret; 135 136 /* Set RTC_PU bit for autonomous wake from shutdown */ 137 ret = nvvrs_update_bits(info, NVVRS_REG_CTL_2, NVVRS_REG_CTL_2_RTC_PU, 138 NVVRS_REG_CTL_2_RTC_PU); 139 if (ret < 0) 140 return ret; 141 142 return 0; 143 } 144 145 static int nvvrs_rtc_disable_alarm(struct nvvrs_rtc_info *info) 146 { 147 struct i2c_client *client = info->client; 148 u8 val[4]; 149 int ret; 150 151 /* Clear RTC_WAKE bit */ 152 ret = nvvrs_update_bits(info, NVVRS_REG_CTL_2, NVVRS_REG_CTL_2_RTC_WAKE, 153 0); 154 if (ret < 0) 155 return ret; 156 157 /* Clear RTC_PU bit */ 158 ret = nvvrs_update_bits(info, NVVRS_REG_CTL_2, NVVRS_REG_CTL_2_RTC_PU, 159 0); 160 if (ret < 0) 161 return ret; 162 163 /* Write ALARM_RESET_VAL in RTC Alarm register to disable alarm */ 164 val[0] = 0xff; 165 val[1] = 0xff; 166 val[2] = 0xff; 167 val[3] = 0xff; 168 169 ret = nvvrs_rtc_write_alarm(client, val); 170 if (ret < 0) 171 return ret; 172 173 return 0; 174 } 175 176 static int nvvrs_rtc_read_time(struct device *dev, struct rtc_time *tm) 177 { 178 struct nvvrs_rtc_info *info = dev_get_drvdata(dev); 179 time64_t secs = 0; 180 int ret; 181 u8 val; 182 183 /* 184 * Multi-byte transfers are not supported with PEC enabled 185 * Read MSB first to avoid coherency issues 186 */ 187 ret = i2c_smbus_read_byte_data(info->client, NVVRS_REG_RTC_T3); 188 if (ret < 0) 189 return ret; 190 191 val = (u8)ret; 192 secs |= (time64_t)val << 24; 193 194 ret = i2c_smbus_read_byte_data(info->client, NVVRS_REG_RTC_T2); 195 if (ret < 0) 196 return ret; 197 198 val = (u8)ret; 199 secs |= (time64_t)val << 16; 200 201 ret = i2c_smbus_read_byte_data(info->client, NVVRS_REG_RTC_T1); 202 if (ret < 0) 203 return ret; 204 205 val = (u8)ret; 206 secs |= (time64_t)val << 8; 207 208 ret = i2c_smbus_read_byte_data(info->client, NVVRS_REG_RTC_T0); 209 if (ret < 0) 210 return ret; 211 212 val = (u8)ret; 213 secs |= val; 214 215 rtc_time64_to_tm(secs, tm); 216 217 return 0; 218 } 219 220 static int nvvrs_rtc_set_time(struct device *dev, struct rtc_time *tm) 221 { 222 struct nvvrs_rtc_info *info = dev_get_drvdata(dev); 223 time64_t secs; 224 u8 time[4]; 225 int ret; 226 227 secs = rtc_tm_to_time64(tm); 228 time[0] = secs & 0xff; 229 time[1] = (secs >> 8) & 0xff; 230 time[2] = (secs >> 16) & 0xff; 231 time[3] = (secs >> 24) & 0xff; 232 233 ret = i2c_smbus_write_byte_data(info->client, NVVRS_REG_RTC_T3, time[3]); 234 if (ret < 0) 235 return ret; 236 237 ret = i2c_smbus_write_byte_data(info->client, NVVRS_REG_RTC_T2, time[2]); 238 if (ret < 0) 239 return ret; 240 241 ret = i2c_smbus_write_byte_data(info->client, NVVRS_REG_RTC_T1, time[1]); 242 if (ret < 0) 243 return ret; 244 245 ret = i2c_smbus_write_byte_data(info->client, NVVRS_REG_RTC_T0, time[0]); 246 247 return ret; 248 } 249 250 static int nvvrs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 251 { 252 struct nvvrs_rtc_info *info = dev_get_drvdata(dev); 253 time64_t alarm_val = 0; 254 int ret; 255 u8 val; 256 257 /* Multi-byte transfers are not supported with PEC enabled */ 258 ret = i2c_smbus_read_byte_data(info->client, NVVRS_REG_RTC_A3); 259 if (ret < 0) 260 return ret; 261 262 val = (u8)ret; 263 alarm_val |= (time64_t)val << 24; 264 265 ret = i2c_smbus_read_byte_data(info->client, NVVRS_REG_RTC_A2); 266 if (ret < 0) 267 return ret; 268 269 val = (u8)ret; 270 alarm_val |= (time64_t)val << 16; 271 272 ret = i2c_smbus_read_byte_data(info->client, NVVRS_REG_RTC_A1); 273 if (ret < 0) 274 return ret; 275 276 val = (u8)ret; 277 alarm_val |= (time64_t)val << 8; 278 279 ret = i2c_smbus_read_byte_data(info->client, NVVRS_REG_RTC_A0); 280 if (ret < 0) 281 return ret; 282 283 val = (u8)ret; 284 alarm_val |= val; 285 286 if (alarm_val == ALARM_RESET_VAL) 287 alrm->enabled = 0; 288 else 289 alrm->enabled = 1; 290 291 rtc_time64_to_tm(alarm_val, &alrm->time); 292 293 return 0; 294 } 295 296 static int nvvrs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 297 { 298 struct nvvrs_rtc_info *info = dev_get_drvdata(dev); 299 time64_t secs; 300 u8 time[4]; 301 int ret; 302 303 if (!alrm->enabled) { 304 ret = nvvrs_rtc_disable_alarm(info); 305 if (ret < 0) 306 return ret; 307 } 308 309 ret = nvvrs_rtc_enable_alarm(info); 310 if (ret < 0) 311 return ret; 312 313 secs = rtc_tm_to_time64(&alrm->time); 314 time[0] = secs & 0xff; 315 time[1] = (secs >> 8) & 0xff; 316 time[2] = (secs >> 16) & 0xff; 317 time[3] = (secs >> 24) & 0xff; 318 319 ret = nvvrs_rtc_write_alarm(info->client, time); 320 321 return ret; 322 } 323 324 static int nvvrs_pseq_irq_clear(struct nvvrs_rtc_info *info) 325 { 326 unsigned int i; 327 int ret; 328 329 for (i = 0; i < NVVRS_IRQ_REG_COUNT; i++) { 330 ret = i2c_smbus_read_byte_data(info->client, 331 NVVRS_REG_INT_SRC1 + i); 332 if (ret < 0) { 333 dev_err(info->dev, "Failed to read INT_SRC%d : %d\n", 334 i + 1, ret); 335 return ret; 336 } 337 338 ret = i2c_smbus_write_byte_data(info->client, 339 NVVRS_REG_INT_SRC1 + i, 340 (u8)ret); 341 if (ret < 0) { 342 dev_err(info->dev, "Failed to clear INT_SRC%d : %d\n", 343 i + 1, ret); 344 return ret; 345 } 346 } 347 348 return 0; 349 } 350 351 static irqreturn_t nvvrs_rtc_irq_handler(int irq, void *data) 352 { 353 struct nvvrs_rtc_info *info = data; 354 int ret; 355 356 /* Check for RTC alarm interrupt */ 357 ret = i2c_smbus_read_byte_data(info->client, NVVRS_REG_INT_SRC1); 358 if (ret < 0) 359 return IRQ_NONE; 360 361 if (ret & NVVRS_INT_SRC1_RTC_MASK) { 362 rtc_lock(info->rtc); 363 rtc_update_irq(info->rtc, 1, RTC_IRQF | RTC_AF); 364 rtc_unlock(info->rtc); 365 } 366 367 /* Clear all interrupts */ 368 if (nvvrs_pseq_irq_clear(info) < 0) 369 return IRQ_NONE; 370 371 return IRQ_HANDLED; 372 } 373 374 static int nvvrs_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 375 { 376 /* 377 * This hardware does not support enabling/disabling the alarm IRQ 378 * independently. The alarm is disabled by clearing the alarm time 379 * via set_alarm(). 380 */ 381 return 0; 382 } 383 384 static const struct rtc_class_ops nvvrs_rtc_ops = { 385 .read_time = nvvrs_rtc_read_time, 386 .set_time = nvvrs_rtc_set_time, 387 .read_alarm = nvvrs_rtc_read_alarm, 388 .set_alarm = nvvrs_rtc_set_alarm, 389 .alarm_irq_enable = nvvrs_rtc_alarm_irq_enable, 390 }; 391 392 static int nvvrs_pseq_vendor_info(struct nvvrs_rtc_info *info) 393 { 394 struct i2c_client *client = info->client; 395 u8 vendor_id, model_rev; 396 int ret; 397 398 ret = i2c_smbus_read_byte_data(client, NVVRS_REG_VENDOR_ID); 399 if (ret < 0) 400 return dev_err_probe(&client->dev, ret, 401 "Failed to read Vendor ID\n"); 402 403 vendor_id = (u8)ret; 404 405 ret = i2c_smbus_read_byte_data(client, NVVRS_REG_MODEL_REV); 406 if (ret < 0) 407 return dev_err_probe(&client->dev, ret, 408 "Failed to read Model Revision\n"); 409 410 model_rev = (u8)ret; 411 412 if (model_rev < NVVRS_MIN_MODEL_REV) { 413 return dev_err_probe(&client->dev, -ENODEV, 414 "Chip revision 0x%02x is not supported!\n", 415 model_rev); 416 } 417 418 dev_dbg(&client->dev, "NVVRS Vendor ID: 0x%02x, Model Rev: 0x%02x\n", 419 vendor_id, model_rev); 420 421 return 0; 422 } 423 424 static int nvvrs_rtc_probe(struct i2c_client *client) 425 { 426 struct nvvrs_rtc_info *info; 427 int ret; 428 429 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL); 430 if (!info) 431 return -ENOMEM; 432 433 if (client->irq <= 0) 434 return dev_err_probe(&client->dev, -EINVAL, "No IRQ specified\n"); 435 436 info->irq = client->irq; 437 info->dev = &client->dev; 438 client->flags |= I2C_CLIENT_PEC; 439 i2c_set_clientdata(client, info); 440 info->client = client; 441 442 /* Check vendor info */ 443 if (nvvrs_pseq_vendor_info(info) < 0) 444 return dev_err_probe(&client->dev, -EINVAL, 445 "Failed to get vendor info\n"); 446 447 /* Clear any pending IRQs before requesting IRQ handler */ 448 if (nvvrs_pseq_irq_clear(info) < 0) 449 return dev_err_probe(&client->dev, -EINVAL, 450 "Failed to clear interrupts\n"); 451 452 /* Allocate RTC device */ 453 info->rtc = devm_rtc_allocate_device(info->dev); 454 if (IS_ERR(info->rtc)) 455 return PTR_ERR(info->rtc); 456 457 info->rtc->ops = &nvvrs_rtc_ops; 458 info->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 459 info->rtc->range_max = RTC_TIMESTAMP_END_2099; 460 461 /* Request RTC IRQ */ 462 ret = devm_request_threaded_irq(info->dev, info->irq, NULL, 463 nvvrs_rtc_irq_handler, IRQF_ONESHOT, 464 "nvvrs-rtc", info); 465 if (ret < 0) { 466 dev_err_probe(info->dev, ret, "Failed to request RTC IRQ\n"); 467 return ret; 468 } 469 470 /* RTC as a wakeup source */ 471 devm_device_init_wakeup(info->dev); 472 473 return devm_rtc_register_device(info->rtc); 474 } 475 476 #ifdef CONFIG_PM_SLEEP 477 static int nvvrs_rtc_suspend(struct device *dev) 478 { 479 struct nvvrs_rtc_info *info = dev_get_drvdata(dev); 480 int ret; 481 482 if (device_may_wakeup(dev)) { 483 /* Set RTC_WAKE bit for auto wake system from suspend state */ 484 ret = nvvrs_update_bits(info, NVVRS_REG_CTL_2, 485 NVVRS_REG_CTL_2_RTC_WAKE, 486 NVVRS_REG_CTL_2_RTC_WAKE); 487 if (ret < 0) { 488 dev_err(info->dev, "Failed to set RTC_WAKE bit (%d)\n", 489 ret); 490 return ret; 491 } 492 493 return enable_irq_wake(info->irq); 494 } 495 496 return 0; 497 } 498 499 static int nvvrs_rtc_resume(struct device *dev) 500 { 501 struct nvvrs_rtc_info *info = dev_get_drvdata(dev); 502 int ret; 503 504 if (device_may_wakeup(dev)) { 505 /* Clear FORCE_ACT bit */ 506 ret = nvvrs_update_bits(info, NVVRS_REG_CTL_1, 507 NVVRS_REG_CTL_1_FORCE_ACT, 0); 508 if (ret < 0) { 509 dev_err(info->dev, "Failed to clear FORCE_ACT bit (%d)\n", 510 ret); 511 return ret; 512 } 513 514 return disable_irq_wake(info->irq); 515 } 516 517 return 0; 518 } 519 520 #endif 521 static SIMPLE_DEV_PM_OPS(nvvrs_rtc_pm_ops, nvvrs_rtc_suspend, nvvrs_rtc_resume); 522 523 static const struct of_device_id nvvrs_rtc_of_match[] = { 524 { .compatible = "nvidia,vrs-10" }, 525 { }, 526 }; 527 MODULE_DEVICE_TABLE(of, nvvrs_rtc_of_match); 528 529 static struct i2c_driver nvvrs_rtc_driver = { 530 .driver = { 531 .name = "rtc-nvidia-vrs10", 532 .pm = &nvvrs_rtc_pm_ops, 533 .of_match_table = nvvrs_rtc_of_match, 534 }, 535 .probe = nvvrs_rtc_probe, 536 }; 537 538 module_i2c_driver(nvvrs_rtc_driver); 539 540 MODULE_AUTHOR("Shubhi Garg <shgarg@nvidia.com>"); 541 MODULE_DESCRIPTION("NVIDIA Voltage Regulator Specification RTC driver"); 542 MODULE_LICENSE("GPL"); 543