1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Tianping.Fang <tianping.fang@mediatek.com> 5 */ 6 7 #include <linux/err.h> 8 #include <linux/interrupt.h> 9 #include <linux/mfd/mt6397/core.h> 10 #include <linux/module.h> 11 #include <linux/mutex.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 #include <linux/rtc.h> 16 #include <linux/mfd/mt6397/rtc.h> 17 #include <linux/mod_devicetable.h> 18 19 static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc) 20 { 21 int ret; 22 u32 data; 23 24 ret = regmap_write(rtc->regmap, rtc->addr_base + rtc->data->wrtgr, 1); 25 if (ret < 0) 26 return ret; 27 28 ret = regmap_read_poll_timeout(rtc->regmap, 29 rtc->addr_base + RTC_BBPU, data, 30 !(data & RTC_BBPU_CBUSY), 31 MTK_RTC_POLL_DELAY_US, 32 MTK_RTC_POLL_TIMEOUT); 33 if (ret < 0) 34 dev_err(rtc->rtc_dev->dev.parent, 35 "failed to write WRTGR: %d\n", ret); 36 37 return ret; 38 } 39 40 static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data) 41 { 42 struct mt6397_rtc *rtc = data; 43 u32 irqsta, irqen; 44 int ret; 45 46 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_STA, &irqsta); 47 if ((ret >= 0) && (irqsta & RTC_IRQ_STA_AL)) { 48 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF); 49 irqen = irqsta & ~RTC_IRQ_EN_AL; 50 mutex_lock(&rtc->lock); 51 if (regmap_write(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, 52 irqen) == 0) 53 mtk_rtc_write_trigger(rtc); 54 mutex_unlock(&rtc->lock); 55 56 return IRQ_HANDLED; 57 } 58 59 return IRQ_NONE; 60 } 61 62 static int __mtk_rtc_read_time(struct mt6397_rtc *rtc, 63 struct rtc_time *tm, int *sec) 64 { 65 int ret; 66 u16 data[RTC_OFFSET_COUNT]; 67 68 mutex_lock(&rtc->lock); 69 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, 70 data, RTC_OFFSET_COUNT); 71 if (ret < 0) 72 goto exit; 73 74 tm->tm_sec = data[RTC_OFFSET_SEC]; 75 tm->tm_min = data[RTC_OFFSET_MIN]; 76 tm->tm_hour = data[RTC_OFFSET_HOUR]; 77 tm->tm_mday = data[RTC_OFFSET_DOM]; 78 tm->tm_wday = data[RTC_OFFSET_DOW]; 79 tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_TC_MTH_MASK; 80 tm->tm_year = data[RTC_OFFSET_YEAR]; 81 82 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec); 83 exit: 84 mutex_unlock(&rtc->lock); 85 return ret; 86 } 87 88 static int mtk_rtc_read_time(struct device *dev, struct rtc_time *tm) 89 { 90 struct mt6397_rtc *rtc = dev_get_drvdata(dev); 91 int sec, ret; 92 93 do { 94 ret = __mtk_rtc_read_time(rtc, tm, &sec); 95 if (ret < 0) 96 goto exit; 97 } while (sec < tm->tm_sec); 98 99 /* HW register start mon/wday from one, but tm_mon/tm_wday start from zero. */ 100 tm->tm_mon--; 101 tm->tm_wday--; 102 103 exit: 104 return ret; 105 } 106 107 static int mtk_rtc_set_time(struct device *dev, struct rtc_time *tm) 108 { 109 struct mt6397_rtc *rtc = dev_get_drvdata(dev); 110 int ret; 111 u16 data[RTC_OFFSET_COUNT]; 112 113 tm->tm_mon++; 114 tm->tm_wday++; 115 116 data[RTC_OFFSET_SEC] = tm->tm_sec; 117 data[RTC_OFFSET_MIN] = tm->tm_min; 118 data[RTC_OFFSET_HOUR] = tm->tm_hour; 119 data[RTC_OFFSET_DOM] = tm->tm_mday; 120 data[RTC_OFFSET_DOW] = tm->tm_wday; 121 data[RTC_OFFSET_MTH] = tm->tm_mon; 122 data[RTC_OFFSET_YEAR] = tm->tm_year; 123 124 mutex_lock(&rtc->lock); 125 ret = regmap_bulk_write(rtc->regmap, rtc->addr_base + RTC_TC_SEC, 126 data, RTC_OFFSET_COUNT); 127 if (ret < 0) 128 goto exit; 129 130 /* Time register write to hardware after call trigger function */ 131 ret = mtk_rtc_write_trigger(rtc); 132 133 exit: 134 mutex_unlock(&rtc->lock); 135 return ret; 136 } 137 138 static int mtk_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) 139 { 140 struct rtc_time *tm = &alm->time; 141 struct mt6397_rtc *rtc = dev_get_drvdata(dev); 142 u32 irqen, pdn2; 143 int ret; 144 u16 data[RTC_OFFSET_COUNT]; 145 146 mutex_lock(&rtc->lock); 147 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, &irqen); 148 if (ret < 0) 149 goto err_exit; 150 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_PDN2, &pdn2); 151 if (ret < 0) 152 goto err_exit; 153 154 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC, 155 data, RTC_OFFSET_COUNT); 156 if (ret < 0) 157 goto err_exit; 158 159 alm->enabled = !!(irqen & RTC_IRQ_EN_AL); 160 alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM); 161 mutex_unlock(&rtc->lock); 162 163 tm->tm_sec = data[RTC_OFFSET_SEC] & RTC_AL_SEC_MASK; 164 tm->tm_min = data[RTC_OFFSET_MIN] & RTC_AL_MIN_MASK; 165 tm->tm_hour = data[RTC_OFFSET_HOUR] & RTC_AL_HOU_MASK; 166 tm->tm_mday = data[RTC_OFFSET_DOM] & RTC_AL_DOM_MASK; 167 tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_AL_MTH_MASK; 168 tm->tm_year = data[RTC_OFFSET_YEAR] & RTC_AL_YEA_MASK; 169 170 tm->tm_mon--; 171 172 return 0; 173 err_exit: 174 mutex_unlock(&rtc->lock); 175 return ret; 176 } 177 178 static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) 179 { 180 struct rtc_time *tm = &alm->time; 181 struct mt6397_rtc *rtc = dev_get_drvdata(dev); 182 int ret; 183 u16 data[RTC_OFFSET_COUNT]; 184 185 tm->tm_mon++; 186 187 mutex_lock(&rtc->lock); 188 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC, 189 data, RTC_OFFSET_COUNT); 190 if (ret < 0) 191 goto exit; 192 193 data[RTC_OFFSET_SEC] = ((data[RTC_OFFSET_SEC] & ~(RTC_AL_SEC_MASK)) | 194 (tm->tm_sec & RTC_AL_SEC_MASK)); 195 data[RTC_OFFSET_MIN] = ((data[RTC_OFFSET_MIN] & ~(RTC_AL_MIN_MASK)) | 196 (tm->tm_min & RTC_AL_MIN_MASK)); 197 data[RTC_OFFSET_HOUR] = ((data[RTC_OFFSET_HOUR] & ~(RTC_AL_HOU_MASK)) | 198 (tm->tm_hour & RTC_AL_HOU_MASK)); 199 data[RTC_OFFSET_DOM] = ((data[RTC_OFFSET_DOM] & ~(RTC_AL_DOM_MASK)) | 200 (tm->tm_mday & RTC_AL_DOM_MASK)); 201 data[RTC_OFFSET_MTH] = ((data[RTC_OFFSET_MTH] & ~(RTC_AL_MTH_MASK)) | 202 (tm->tm_mon & RTC_AL_MTH_MASK)); 203 data[RTC_OFFSET_YEAR] = ((data[RTC_OFFSET_YEAR] & ~(RTC_AL_YEA_MASK)) | 204 (tm->tm_year & RTC_AL_YEA_MASK)); 205 206 if (alm->enabled) { 207 ret = regmap_bulk_write(rtc->regmap, 208 rtc->addr_base + RTC_AL_SEC, 209 data, RTC_OFFSET_COUNT); 210 if (ret < 0) 211 goto exit; 212 ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_AL_MASK, 213 RTC_AL_MASK_DOW); 214 if (ret < 0) 215 goto exit; 216 ret = regmap_update_bits(rtc->regmap, 217 rtc->addr_base + RTC_IRQ_EN, 218 RTC_IRQ_EN_ONESHOT_AL, 219 RTC_IRQ_EN_ONESHOT_AL); 220 if (ret < 0) 221 goto exit; 222 } else { 223 ret = regmap_update_bits(rtc->regmap, 224 rtc->addr_base + RTC_IRQ_EN, 225 RTC_IRQ_EN_ONESHOT_AL, 0); 226 if (ret < 0) 227 goto exit; 228 } 229 230 /* All alarm time register write to hardware after calling 231 * mtk_rtc_write_trigger. This can avoid race condition if alarm 232 * occur happen during writing alarm time register. 233 */ 234 ret = mtk_rtc_write_trigger(rtc); 235 exit: 236 mutex_unlock(&rtc->lock); 237 return ret; 238 } 239 240 static const struct rtc_class_ops mtk_rtc_ops = { 241 .read_time = mtk_rtc_read_time, 242 .set_time = mtk_rtc_set_time, 243 .read_alarm = mtk_rtc_read_alarm, 244 .set_alarm = mtk_rtc_set_alarm, 245 }; 246 247 static int mtk_rtc_probe(struct platform_device *pdev) 248 { 249 struct resource *res; 250 struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent); 251 struct mt6397_rtc *rtc; 252 int ret; 253 254 rtc = devm_kzalloc(&pdev->dev, sizeof(struct mt6397_rtc), GFP_KERNEL); 255 if (!rtc) 256 return -ENOMEM; 257 258 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 259 if (!res) 260 return -EINVAL; 261 rtc->addr_base = res->start; 262 263 rtc->data = of_device_get_match_data(&pdev->dev); 264 265 rtc->irq = platform_get_irq(pdev, 0); 266 if (rtc->irq < 0) 267 return rtc->irq; 268 269 rtc->regmap = mt6397_chip->regmap; 270 mutex_init(&rtc->lock); 271 272 platform_set_drvdata(pdev, rtc); 273 274 rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev); 275 if (IS_ERR(rtc->rtc_dev)) 276 return PTR_ERR(rtc->rtc_dev); 277 278 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL, 279 mtk_rtc_irq_handler_thread, 280 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 281 "mt6397-rtc", rtc); 282 283 if (ret) { 284 dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n", 285 rtc->irq, ret); 286 return ret; 287 } 288 289 device_init_wakeup(&pdev->dev, 1); 290 291 rtc->rtc_dev->ops = &mtk_rtc_ops; 292 rtc->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_1900; 293 rtc->rtc_dev->range_max = mktime64(2027, 12, 31, 23, 59, 59); 294 rtc->rtc_dev->start_secs = mktime64(1968, 1, 2, 0, 0, 0); 295 rtc->rtc_dev->set_start_time = true; 296 297 return devm_rtc_register_device(rtc->rtc_dev); 298 } 299 300 #ifdef CONFIG_PM_SLEEP 301 static int mt6397_rtc_suspend(struct device *dev) 302 { 303 struct mt6397_rtc *rtc = dev_get_drvdata(dev); 304 305 if (device_may_wakeup(dev)) 306 enable_irq_wake(rtc->irq); 307 308 return 0; 309 } 310 311 static int mt6397_rtc_resume(struct device *dev) 312 { 313 struct mt6397_rtc *rtc = dev_get_drvdata(dev); 314 315 if (device_may_wakeup(dev)) 316 disable_irq_wake(rtc->irq); 317 318 return 0; 319 } 320 #endif 321 322 static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend, 323 mt6397_rtc_resume); 324 325 static const struct mtk_rtc_data mt6358_rtc_data = { 326 .wrtgr = RTC_WRTGR_MT6358, 327 }; 328 329 static const struct mtk_rtc_data mt6397_rtc_data = { 330 .wrtgr = RTC_WRTGR_MT6397, 331 }; 332 333 static const struct of_device_id mt6397_rtc_of_match[] = { 334 { .compatible = "mediatek,mt6323-rtc", .data = &mt6397_rtc_data }, 335 { .compatible = "mediatek,mt6358-rtc", .data = &mt6358_rtc_data }, 336 { .compatible = "mediatek,mt6397-rtc", .data = &mt6397_rtc_data }, 337 { } 338 }; 339 MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match); 340 341 static struct platform_driver mtk_rtc_driver = { 342 .driver = { 343 .name = "mt6397-rtc", 344 .of_match_table = mt6397_rtc_of_match, 345 .pm = &mt6397_pm_ops, 346 }, 347 .probe = mtk_rtc_probe, 348 }; 349 350 module_platform_driver(mtk_rtc_driver); 351 352 MODULE_LICENSE("GPL v2"); 353 MODULE_AUTHOR("Tianping Fang <tianping.fang@mediatek.com>"); 354 MODULE_DESCRIPTION("RTC Driver for MediaTek MT6397 PMIC"); 355