1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Tianping.Fang <tianping.fang@mediatek.com> 5 */ 6 7 #include <linux/array_size.h> 8 #include <linux/bitfield.h> 9 #include <linux/err.h> 10 #include <linux/interrupt.h> 11 #include <linux/mfd/mt6397/core.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/rtc.h> 18 #include <linux/mfd/mt6397/rtc.h> 19 20 static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc) 21 { 22 int ret; 23 u32 data; 24 25 ret = regmap_write(rtc->regmap, rtc->addr_base + rtc->data->wrtgr, 1); 26 if (ret < 0) 27 return ret; 28 29 ret = regmap_read_poll_timeout(rtc->regmap, 30 rtc->addr_base + RTC_BBPU, data, 31 !(data & RTC_BBPU_CBUSY), 32 MTK_RTC_POLL_DELAY_US, 33 MTK_RTC_POLL_TIMEOUT); 34 if (ret < 0) 35 dev_err(rtc->rtc_dev->dev.parent, 36 "failed to write WRTGR: %d\n", ret); 37 38 return ret; 39 } 40 41 static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data) 42 { 43 struct mt6397_rtc *rtc = data; 44 u32 irqsta, irqen; 45 int ret; 46 47 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_STA, &irqsta); 48 if ((ret >= 0) && (irqsta & RTC_IRQ_STA_AL)) { 49 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF); 50 irqen = irqsta & ~RTC_IRQ_EN_AL; 51 mutex_lock(&rtc->lock); 52 if (regmap_write(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, 53 irqen) == 0) 54 mtk_rtc_write_trigger(rtc); 55 mutex_unlock(&rtc->lock); 56 57 return IRQ_HANDLED; 58 } 59 60 return IRQ_NONE; 61 } 62 63 static int __mtk_rtc_read_time(struct mt6397_rtc *rtc, 64 struct rtc_time *tm, int *sec) 65 { 66 int ret; 67 u16 data[RTC_OFFSET_COUNT]; 68 69 mutex_lock(&rtc->lock); 70 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, 71 data, RTC_OFFSET_COUNT); 72 if (ret < 0) 73 goto exit; 74 75 tm->tm_sec = data[RTC_OFFSET_SEC]; 76 tm->tm_min = data[RTC_OFFSET_MIN]; 77 tm->tm_hour = data[RTC_OFFSET_HOUR]; 78 tm->tm_mday = data[RTC_OFFSET_DOM]; 79 tm->tm_wday = data[RTC_OFFSET_DOW]; 80 tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_TC_MTH_MASK; 81 tm->tm_year = data[RTC_OFFSET_YEAR]; 82 83 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec); 84 exit: 85 mutex_unlock(&rtc->lock); 86 return ret; 87 } 88 89 static int mtk_rtc_read_time(struct device *dev, struct rtc_time *tm) 90 { 91 struct mt6397_rtc *rtc = dev_get_drvdata(dev); 92 int sec, ret; 93 94 do { 95 ret = __mtk_rtc_read_time(rtc, tm, &sec); 96 if (ret < 0) 97 goto exit; 98 } while (sec < tm->tm_sec); 99 100 /* HW register start mon/wday from one, but tm_mon/tm_wday start from zero. */ 101 tm->tm_mon--; 102 tm->tm_wday--; 103 104 exit: 105 return ret; 106 } 107 108 static int mtk_rtc_set_time(struct device *dev, struct rtc_time *tm) 109 { 110 struct mt6397_rtc *rtc = dev_get_drvdata(dev); 111 int ret; 112 u16 data[RTC_OFFSET_COUNT]; 113 114 tm->tm_mon++; 115 tm->tm_wday++; 116 117 data[RTC_OFFSET_SEC] = tm->tm_sec; 118 data[RTC_OFFSET_MIN] = tm->tm_min; 119 data[RTC_OFFSET_HOUR] = tm->tm_hour; 120 data[RTC_OFFSET_DOM] = tm->tm_mday; 121 data[RTC_OFFSET_DOW] = tm->tm_wday; 122 data[RTC_OFFSET_MTH] = tm->tm_mon; 123 data[RTC_OFFSET_YEAR] = tm->tm_year; 124 125 mutex_lock(&rtc->lock); 126 ret = regmap_bulk_write(rtc->regmap, rtc->addr_base + RTC_TC_SEC, 127 data, RTC_OFFSET_COUNT); 128 if (ret < 0) 129 goto exit; 130 131 /* Time register write to hardware after call trigger function */ 132 ret = mtk_rtc_write_trigger(rtc); 133 134 exit: 135 mutex_unlock(&rtc->lock); 136 return ret; 137 } 138 139 static int mtk_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) 140 { 141 struct rtc_time *tm = &alm->time; 142 struct mt6397_rtc *rtc = dev_get_drvdata(dev); 143 u32 irqen, pdn2; 144 int ret; 145 u16 data[RTC_OFFSET_COUNT]; 146 147 mutex_lock(&rtc->lock); 148 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, &irqen); 149 if (ret < 0) 150 goto err_exit; 151 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_PDN2, &pdn2); 152 if (ret < 0) 153 goto err_exit; 154 155 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC, 156 data, RTC_OFFSET_COUNT); 157 if (ret < 0) 158 goto err_exit; 159 160 alm->enabled = !!(irqen & RTC_IRQ_EN_AL); 161 alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM); 162 mutex_unlock(&rtc->lock); 163 164 tm->tm_sec = data[RTC_OFFSET_SEC] & RTC_AL_SEC_MASK; 165 tm->tm_min = data[RTC_OFFSET_MIN] & RTC_AL_MIN_MASK; 166 tm->tm_hour = data[RTC_OFFSET_HOUR] & RTC_AL_HOU_MASK; 167 tm->tm_mday = data[RTC_OFFSET_DOM] & RTC_AL_DOM_MASK; 168 tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_AL_MTH_MASK; 169 tm->tm_year = data[RTC_OFFSET_YEAR] & RTC_AL_YEA_MASK; 170 171 tm->tm_mon--; 172 173 return 0; 174 err_exit: 175 mutex_unlock(&rtc->lock); 176 return ret; 177 } 178 179 static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) 180 { 181 struct rtc_time *tm = &alm->time; 182 struct mt6397_rtc *rtc = dev_get_drvdata(dev); 183 int ret; 184 u16 data[RTC_OFFSET_COUNT]; 185 186 tm->tm_mon++; 187 188 mutex_lock(&rtc->lock); 189 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC, 190 data, RTC_OFFSET_COUNT); 191 if (ret < 0) 192 goto exit; 193 194 data[RTC_OFFSET_SEC] = ((data[RTC_OFFSET_SEC] & ~(RTC_AL_SEC_MASK)) | 195 (tm->tm_sec & RTC_AL_SEC_MASK)); 196 data[RTC_OFFSET_MIN] = ((data[RTC_OFFSET_MIN] & ~(RTC_AL_MIN_MASK)) | 197 (tm->tm_min & RTC_AL_MIN_MASK)); 198 data[RTC_OFFSET_HOUR] = ((data[RTC_OFFSET_HOUR] & ~(RTC_AL_HOU_MASK)) | 199 (tm->tm_hour & RTC_AL_HOU_MASK)); 200 data[RTC_OFFSET_DOM] = ((data[RTC_OFFSET_DOM] & ~(RTC_AL_DOM_MASK)) | 201 (tm->tm_mday & RTC_AL_DOM_MASK)); 202 data[RTC_OFFSET_MTH] = ((data[RTC_OFFSET_MTH] & ~(RTC_AL_MTH_MASK)) | 203 (tm->tm_mon & RTC_AL_MTH_MASK)); 204 data[RTC_OFFSET_YEAR] = ((data[RTC_OFFSET_YEAR] & ~(RTC_AL_YEA_MASK)) | 205 (tm->tm_year & RTC_AL_YEA_MASK)); 206 207 if (alm->enabled) { 208 ret = regmap_bulk_write(rtc->regmap, 209 rtc->addr_base + RTC_AL_SEC, 210 data, RTC_OFFSET_COUNT); 211 if (ret < 0) 212 goto exit; 213 ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_AL_MASK, 214 RTC_AL_MASK_DOW); 215 if (ret < 0) 216 goto exit; 217 ret = regmap_update_bits(rtc->regmap, 218 rtc->addr_base + RTC_IRQ_EN, 219 RTC_IRQ_EN_ONESHOT_AL, 220 RTC_IRQ_EN_ONESHOT_AL); 221 if (ret < 0) 222 goto exit; 223 } else { 224 ret = regmap_update_bits(rtc->regmap, 225 rtc->addr_base + RTC_IRQ_EN, 226 RTC_IRQ_EN_ONESHOT_AL, 0); 227 if (ret < 0) 228 goto exit; 229 } 230 231 /* All alarm time register write to hardware after calling 232 * mtk_rtc_write_trigger. This can avoid race condition if alarm 233 * occur happen during writing alarm time register. 234 */ 235 ret = mtk_rtc_write_trigger(rtc); 236 exit: 237 mutex_unlock(&rtc->lock); 238 return ret; 239 } 240 241 static const struct rtc_class_ops mtk_rtc_ops = { 242 .read_time = mtk_rtc_read_time, 243 .set_time = mtk_rtc_set_time, 244 .read_alarm = mtk_rtc_read_alarm, 245 .set_alarm = mtk_rtc_set_alarm, 246 }; 247 248 /* 249 * The spare byte of each of these registers, in the order a board addresses 250 * them as RTC_NEW_SPARE0 to RTC_NEW_SPARE3. 251 */ 252 static const u32 mtk_rtc_spare_reg[] = { 253 RTC_AL_HOU, RTC_AL_DOM, RTC_AL_DOW, RTC_AL_MTH, 254 }; 255 256 static int mtk_rtc_nvram_read(void *priv, unsigned int offset, void *val, 257 size_t bytes) 258 { 259 struct mt6397_rtc *rtc = priv; 260 u8 *buf = val; 261 u32 data; 262 int ret = 0; 263 264 if (offset >= ARRAY_SIZE(mtk_rtc_spare_reg) || 265 bytes > ARRAY_SIZE(mtk_rtc_spare_reg) - offset) 266 return -EINVAL; 267 268 mutex_lock(&rtc->lock); 269 270 while (bytes--) { 271 ret = regmap_read(rtc->regmap, 272 rtc->addr_base + mtk_rtc_spare_reg[offset++], 273 &data); 274 if (ret) 275 break; 276 277 *buf++ = FIELD_GET(RTC_SPARE_MASK, data); 278 } 279 280 mutex_unlock(&rtc->lock); 281 282 return ret; 283 } 284 285 static int mtk_rtc_nvram_write(void *priv, unsigned int offset, void *val, 286 size_t bytes) 287 { 288 struct mt6397_rtc *rtc = priv; 289 u8 *buf = val; 290 int ret = 0; 291 292 if (offset >= ARRAY_SIZE(mtk_rtc_spare_reg) || 293 bytes > ARRAY_SIZE(mtk_rtc_spare_reg) - offset) 294 return -EINVAL; 295 296 mutex_lock(&rtc->lock); 297 298 while (bytes--) { 299 ret = regmap_update_bits(rtc->regmap, 300 rtc->addr_base + mtk_rtc_spare_reg[offset++], 301 RTC_SPARE_MASK, 302 FIELD_PREP(RTC_SPARE_MASK, *buf++)); 303 if (ret) 304 goto out; 305 } 306 307 /* 308 * None of it reaches the always-on domain until the write trigger, 309 * which commits every pending alarm register at once -- so this runs 310 * under the same lock the alarm paths take, rather than landing in 311 * the middle of one of them. 312 */ 313 ret = mtk_rtc_write_trigger(rtc); 314 out: 315 mutex_unlock(&rtc->lock); 316 317 return ret; 318 } 319 320 static int mtk_rtc_probe(struct platform_device *pdev) 321 { 322 struct resource *res; 323 struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent); 324 struct nvmem_config nvmem_cfg = { 325 .name = "mt6397_rtc_spare", 326 .word_size = 1, 327 .stride = 1, 328 .size = ARRAY_SIZE(mtk_rtc_spare_reg), 329 .type = NVMEM_TYPE_BATTERY_BACKED, 330 .reg_read = mtk_rtc_nvram_read, 331 .reg_write = mtk_rtc_nvram_write, 332 }; 333 struct mt6397_rtc *rtc; 334 int ret; 335 336 rtc = devm_kzalloc_obj(&pdev->dev, struct mt6397_rtc); 337 if (!rtc) 338 return -ENOMEM; 339 340 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 341 if (!res) 342 return -EINVAL; 343 rtc->addr_base = res->start; 344 345 rtc->data = of_device_get_match_data(&pdev->dev); 346 347 rtc->irq = platform_get_irq(pdev, 0); 348 if (rtc->irq < 0) 349 return rtc->irq; 350 351 rtc->regmap = mt6397_chip->regmap; 352 mutex_init(&rtc->lock); 353 354 platform_set_drvdata(pdev, rtc); 355 356 rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev); 357 if (IS_ERR(rtc->rtc_dev)) 358 return PTR_ERR(rtc->rtc_dev); 359 360 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL, 361 mtk_rtc_irq_handler_thread, 362 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 363 "mt6397-rtc", rtc); 364 365 if (ret) { 366 dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n", 367 rtc->irq, ret); 368 return ret; 369 } 370 371 device_init_wakeup(&pdev->dev, true); 372 373 rtc->rtc_dev->ops = &mtk_rtc_ops; 374 rtc->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_1900; 375 rtc->rtc_dev->range_max = mktime64(2027, 12, 31, 23, 59, 59); 376 rtc->rtc_dev->start_secs = mktime64(1968, 1, 2, 0, 0, 0); 377 rtc->rtc_dev->set_start_time = true; 378 379 ret = devm_rtc_register_device(rtc->rtc_dev); 380 if (ret) 381 return ret; 382 383 nvmem_cfg.priv = rtc; 384 385 return devm_rtc_nvmem_register(rtc->rtc_dev, &nvmem_cfg); 386 } 387 388 #ifdef CONFIG_PM_SLEEP 389 static int mt6397_rtc_suspend(struct device *dev) 390 { 391 struct mt6397_rtc *rtc = dev_get_drvdata(dev); 392 393 if (device_may_wakeup(dev)) 394 enable_irq_wake(rtc->irq); 395 396 return 0; 397 } 398 399 static int mt6397_rtc_resume(struct device *dev) 400 { 401 struct mt6397_rtc *rtc = dev_get_drvdata(dev); 402 403 if (device_may_wakeup(dev)) 404 disable_irq_wake(rtc->irq); 405 406 return 0; 407 } 408 #endif 409 410 static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend, 411 mt6397_rtc_resume); 412 413 static const struct mtk_rtc_data mt6358_rtc_data = { 414 .wrtgr = RTC_WRTGR_MT6358, 415 }; 416 417 static const struct mtk_rtc_data mt6397_rtc_data = { 418 .wrtgr = RTC_WRTGR_MT6397, 419 }; 420 421 static const struct of_device_id mt6397_rtc_of_match[] = { 422 { .compatible = "mediatek,mt6323-rtc", .data = &mt6397_rtc_data }, 423 { .compatible = "mediatek,mt6357-rtc", .data = &mt6358_rtc_data }, 424 { .compatible = "mediatek,mt6358-rtc", .data = &mt6358_rtc_data }, 425 { .compatible = "mediatek,mt6397-rtc", .data = &mt6397_rtc_data }, 426 { } 427 }; 428 MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match); 429 430 static struct platform_driver mtk_rtc_driver = { 431 .driver = { 432 .name = "mt6397-rtc", 433 .of_match_table = mt6397_rtc_of_match, 434 .pm = &mt6397_pm_ops, 435 }, 436 .probe = mtk_rtc_probe, 437 }; 438 439 module_platform_driver(mtk_rtc_driver); 440 441 MODULE_LICENSE("GPL v2"); 442 MODULE_AUTHOR("Tianping Fang <tianping.fang@mediatek.com>"); 443 MODULE_DESCRIPTION("RTC Driver for MediaTek MT6397 PMIC"); 444