1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * RTC driver for the MAX31335
4 *
5 * Copyright (C) 2023 Analog Devices
6 *
7 * Antoniu Miclaus <antoniu.miclaus@analog.com>
8 *
9 */
10
11 #include <linux/unaligned.h>
12 #include <linux/bcd.h>
13 #include <linux/bitfield.h>
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/hwmon.h>
18 #include <linux/i2c.h>
19 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/regmap.h>
24 #include <linux/rtc.h>
25 #include <linux/util_macros.h>
26
27 /* MAX31335 Register Map */
28 #define MAX31335_STATUS1 0x00
29 #define MAX31335_INT_EN1 0x01
30 #define MAX31335_STATUS2 0x02
31 #define MAX31335_INT_EN2 0x03
32 #define MAX31335_RTC_RESET 0x04
33 #define MAX31335_RTC_CONFIG 0x05
34 #define MAX31335_RTC_CONFIG2 0x06
35 #define MAX31335_TIMESTAMP_CONFIG 0x07
36 #define MAX31335_TIMER_CONFIG 0x08
37 #define MAX31335_SECONDS_1_128 0x09
38 #define MAX31335_SECONDS 0x0A
39 #define MAX31335_MINUTES 0x0B
40 #define MAX31335_HOURS 0x0C
41 #define MAX31335_DAY 0x0D
42 #define MAX31335_DATE 0x0E
43 #define MAX31335_MONTH 0x0F
44 #define MAX31335_YEAR 0x0F
45 #define MAX31335_ALM1_SEC 0x11
46 #define MAX31335_ALM1_MIN 0x12
47 #define MAX31335_ALM1_HRS 0x13
48 #define MAX31335_ALM1_DAY_DATE 0x14
49 #define MAX31335_ALM1_MON 0x15
50 #define MAX31335_ALM1_YEAR 0x16
51 #define MAX31335_ALM2_MIN 0x17
52 #define MAX31335_ALM2_HRS 0x18
53 #define MAX31335_ALM2_DAY_DATE 0x19
54 #define MAX31335_TIMER_COUNT 0x1A
55 #define MAX31335_TIMER_INIT 0x1B
56 #define MAX31335_PWR_MGMT 0x1C
57 #define MAX31335_TRICKLE_REG 0x1D
58 #define MAX31335_AGING_OFFSET 0x1E
59 #define MAX31335_TS_CONFIG 0x30
60 #define MAX31335_TEMP_ALARM_HIGH_MSB 0x31
61 #define MAX31335_TEMP_ALARM_HIGH_LSB 0x32
62 #define MAX31335_TEMP_ALARM_LOW_MSB 0x33
63 #define MAX31335_TEMP_ALARM_LOW_LSB 0x34
64 #define MAX31335_TEMP_DATA_MSB 0x35
65 #define MAX31335_TEMP_DATA_LSB 0x36
66 #define MAX31335_TS0_SEC_1_128 0x40
67 #define MAX31335_TS0_SEC 0x41
68 #define MAX31335_TS0_MIN 0x42
69 #define MAX31335_TS0_HOUR 0x43
70 #define MAX31335_TS0_DATE 0x44
71 #define MAX31335_TS0_MONTH 0x45
72 #define MAX31335_TS0_YEAR 0x46
73 #define MAX31335_TS0_FLAGS 0x47
74 #define MAX31335_TS1_SEC_1_128 0x48
75 #define MAX31335_TS1_SEC 0x49
76 #define MAX31335_TS1_MIN 0x4A
77 #define MAX31335_TS1_HOUR 0x4B
78 #define MAX31335_TS1_DATE 0x4C
79 #define MAX31335_TS1_MONTH 0x4D
80 #define MAX31335_TS1_YEAR 0x4E
81 #define MAX31335_TS1_FLAGS 0x4F
82 #define MAX31335_TS2_SEC_1_128 0x50
83 #define MAX31335_TS2_SEC 0x51
84 #define MAX31335_TS2_MIN 0x52
85 #define MAX31335_TS2_HOUR 0x53
86 #define MAX31335_TS2_DATE 0x54
87 #define MAX31335_TS2_MONTH 0x55
88 #define MAX31335_TS2_YEAR 0x56
89 #define MAX31335_TS2_FLAGS 0x57
90 #define MAX31335_TS3_SEC_1_128 0x58
91 #define MAX31335_TS3_SEC 0x59
92 #define MAX31335_TS3_MIN 0x5A
93 #define MAX31335_TS3_HOUR 0x5B
94 #define MAX31335_TS3_DATE 0x5C
95 #define MAX31335_TS3_MONTH 0x5D
96 #define MAX31335_TS3_YEAR 0x5E
97 #define MAX31335_TS3_FLAGS 0x5F
98
99 /* MAX31335_STATUS1 Bit Definitions */
100 #define MAX31335_STATUS1_PSDECT BIT(7)
101 #define MAX31335_STATUS1_OSF BIT(6)
102 #define MAX31335_STATUS1_PFAIL BIT(5)
103 #define MAX31335_STATUS1_VBATLOW BIT(4)
104 #define MAX31335_STATUS1_DIF BIT(3)
105 #define MAX31335_STATUS1_TIF BIT(2)
106 #define MAX31335_STATUS1_A2F BIT(1)
107 #define MAX31335_STATUS1_A1F BIT(0)
108
109 /* MAX31335_INT_EN1 Bit Definitions */
110 #define MAX31335_INT_EN1_DOSF BIT(6)
111 #define MAX31335_INT_EN1_PFAILE BIT(5)
112 #define MAX31335_INT_EN1_VBATLOWE BIT(4)
113 #define MAX31335_INT_EN1_DIE BIT(3)
114 #define MAX31335_INT_EN1_TIE BIT(2)
115 #define MAX31335_INT_EN1_A2IE BIT(1)
116 #define MAX31335_INT_EN1_A1IE BIT(0)
117
118 /* MAX31335_STATUS2 Bit Definitions */
119 #define MAX31335_STATUS2_TEMP_RDY BIT(2)
120 #define MAX31335_STATUS2_OTF BIT(1)
121 #define MAX31335_STATUS2_UTF BIT(0)
122
123 /* MAX31335_INT_EN2 Bit Definitions */
124 #define MAX31335_INT_EN2_TEMP_RDY_EN BIT(2)
125 #define MAX31335_INT_EN2_OTIE BIT(1)
126 #define MAX31335_INT_EN2_UTIE BIT(0)
127
128 /* MAX31335_RTC_RESET Bit Definitions */
129 #define MAX31335_RTC_RESET_SWRST BIT(0)
130
131 /* MAX31335_RTC_CONFIG1 Bit Definitions */
132 #define MAX31335_RTC_CONFIG1_EN_IO BIT(6)
133 #define MAX31335_RTC_CONFIG1_A1AC GENMASK(5, 4)
134 #define MAX31335_RTC_CONFIG1_DIP BIT(3)
135 #define MAX31335_RTC_CONFIG1_I2C_TIMEOUT BIT(1)
136 #define MAX31335_RTC_CONFIG1_EN_OSC BIT(0)
137
138 /* MAX31335_RTC_CONFIG2 Bit Definitions */
139 #define MAX31335_RTC_CONFIG2_ENCLKO BIT(2)
140 #define MAX31335_RTC_CONFIG2_CLKO_HZ GENMASK(1, 0)
141
142 /* MAX31335_TIMESTAMP_CONFIG Bit Definitions */
143 #define MAX31335_TIMESTAMP_CONFIG_TSVLOW BIT(5)
144 #define MAX31335_TIMESTAMP_CONFIG_TSPWM BIT(4)
145 #define MAX31335_TIMESTAMP_CONFIG_TSDIN BIT(3)
146 #define MAX31335_TIMESTAMP_CONFIG_TSOW BIT(2)
147 #define MAX31335_TIMESTAMP_CONFIG_TSR BIT(1)
148 #define MAX31335_TIMESTAMP_CONFIG_TSE BIT(0)
149
150 /* MAX31335_TIMER_CONFIG Bit Definitions */
151 #define MAX31335_TIMER_CONFIG_TE BIT(4)
152 #define MAX31335_TIMER_CONFIG_TPAUSE BIT(3)
153 #define MAX31335_TIMER_CONFIG_TRPT BIT(2)
154 #define MAX31335_TIMER_CONFIG_TFS GENMASK(1, 0)
155
156 /* MAX31335_HOURS Bit Definitions */
157 #define MAX31335_HOURS_F_24_12 BIT(6)
158 #define MAX31335_HOURS_HR_20_AM_PM BIT(5)
159
160 /* MAX31335_MONTH Bit Definitions */
161 #define MAX31335_MONTH_CENTURY BIT(7)
162
163 /* MAX31335_PWR_MGMT Bit Definitions */
164 #define MAX31335_PWR_MGMT_PFVT BIT(0)
165
166 /* MAX31335_TRICKLE_REG Bit Definitions */
167 #define MAX31335_TRICKLE_REG_TRICKLE GENMASK(3, 1)
168 #define MAX31335_TRICKLE_REG_EN_TRICKLE BIT(0)
169
170 /* MAX31335_TS_CONFIG Bit Definitions */
171 #define MAX31335_TS_CONFIG_AUTO BIT(4)
172 #define MAX31335_TS_CONFIG_CONVERT_T BIT(3)
173 #define MAX31335_TS_CONFIG_TSINT GENMASK(2, 0)
174
175 /* MAX31335_TS_FLAGS Bit Definitions */
176 #define MAX31335_TS_FLAGS_VLOWF BIT(3)
177 #define MAX31335_TS_FLAGS_VBATF BIT(2)
178 #define MAX31335_TS_FLAGS_VCCF BIT(1)
179 #define MAX31335_TS_FLAGS_DINF BIT(0)
180
181 /* MAX31335 Miscellaneous Definitions */
182 #define MAX31335_TRICKLE_SCHOTTKY_DIODE 1
183 #define MAX31335_TRICKLE_STANDARD_DIODE 4
184 #define MAX31335_RAM_SIZE 32
185 #define MAX31335_TIME_SIZE 0x07
186
187 #define clk_hw_to_max31335(_hw) container_of(_hw, struct max31335_data, clkout)
188
189 struct max31335_data {
190 struct regmap *regmap;
191 struct rtc_device *rtc;
192 struct clk_hw clkout;
193 };
194
195 static const int max31335_clkout_freq[] = { 1, 64, 1024, 32768 };
196
197 static const u16 max31335_trickle_resistors[] = {3000, 6000, 11000};
198
max31335_volatile_reg(struct device * dev,unsigned int reg)199 static bool max31335_volatile_reg(struct device *dev, unsigned int reg)
200 {
201 /* time keeping registers */
202 if (reg >= MAX31335_SECONDS &&
203 reg < MAX31335_SECONDS + MAX31335_TIME_SIZE)
204 return true;
205
206 /* interrupt status register */
207 if (reg == MAX31335_STATUS1)
208 return true;
209
210 /* temperature registers */
211 if (reg == MAX31335_TEMP_DATA_MSB || reg == MAX31335_TEMP_DATA_LSB)
212 return true;
213
214 return false;
215 }
216
217 static const struct regmap_config regmap_config = {
218 .reg_bits = 8,
219 .val_bits = 8,
220 .max_register = 0x5F,
221 .volatile_reg = max31335_volatile_reg,
222 };
223
max31335_read_time(struct device * dev,struct rtc_time * tm)224 static int max31335_read_time(struct device *dev, struct rtc_time *tm)
225 {
226 struct max31335_data *max31335 = dev_get_drvdata(dev);
227 u8 date[7];
228 int ret;
229
230 ret = regmap_bulk_read(max31335->regmap, MAX31335_SECONDS, date,
231 sizeof(date));
232 if (ret)
233 return ret;
234
235 tm->tm_sec = bcd2bin(date[0] & 0x7f);
236 tm->tm_min = bcd2bin(date[1] & 0x7f);
237 tm->tm_hour = bcd2bin(date[2] & 0x3f);
238 tm->tm_wday = bcd2bin(date[3] & 0x7) - 1;
239 tm->tm_mday = bcd2bin(date[4] & 0x3f);
240 tm->tm_mon = bcd2bin(date[5] & 0x1f) - 1;
241 tm->tm_year = bcd2bin(date[6]) + 100;
242
243 if (FIELD_GET(MAX31335_MONTH_CENTURY, date[5]))
244 tm->tm_year += 100;
245
246 return 0;
247 }
248
max31335_set_time(struct device * dev,struct rtc_time * tm)249 static int max31335_set_time(struct device *dev, struct rtc_time *tm)
250 {
251 struct max31335_data *max31335 = dev_get_drvdata(dev);
252 u8 date[7];
253
254 date[0] = bin2bcd(tm->tm_sec);
255 date[1] = bin2bcd(tm->tm_min);
256 date[2] = bin2bcd(tm->tm_hour);
257 date[3] = bin2bcd(tm->tm_wday + 1);
258 date[4] = bin2bcd(tm->tm_mday);
259 date[5] = bin2bcd(tm->tm_mon + 1);
260 date[6] = bin2bcd(tm->tm_year % 100);
261
262 if (tm->tm_year >= 200)
263 date[5] |= FIELD_PREP(MAX31335_MONTH_CENTURY, 1);
264
265 return regmap_bulk_write(max31335->regmap, MAX31335_SECONDS, date,
266 sizeof(date));
267 }
268
max31335_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)269 static int max31335_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
270 {
271 struct max31335_data *max31335 = dev_get_drvdata(dev);
272 int ret, ctrl, status;
273 struct rtc_time time;
274 u8 regs[6];
275
276 ret = regmap_bulk_read(max31335->regmap, MAX31335_ALM1_SEC, regs,
277 sizeof(regs));
278 if (ret)
279 return ret;
280
281 alrm->time.tm_sec = bcd2bin(regs[0] & 0x7f);
282 alrm->time.tm_min = bcd2bin(regs[1] & 0x7f);
283 alrm->time.tm_hour = bcd2bin(regs[2] & 0x3f);
284 alrm->time.tm_mday = bcd2bin(regs[3] & 0x3f);
285 alrm->time.tm_mon = bcd2bin(regs[4] & 0x1f) - 1;
286 alrm->time.tm_year = bcd2bin(regs[5]) + 100;
287
288 ret = max31335_read_time(dev, &time);
289 if (ret)
290 return ret;
291
292 if (time.tm_year >= 200)
293 alrm->time.tm_year += 100;
294
295 ret = regmap_read(max31335->regmap, MAX31335_INT_EN1, &ctrl);
296 if (ret)
297 return ret;
298
299 ret = regmap_read(max31335->regmap, MAX31335_STATUS1, &status);
300 if (ret)
301 return ret;
302
303 alrm->enabled = FIELD_GET(MAX31335_INT_EN1_A1IE, ctrl);
304 alrm->pending = FIELD_GET(MAX31335_STATUS1_A1F, status);
305
306 return 0;
307 }
308
max31335_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)309 static int max31335_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
310 {
311 struct max31335_data *max31335 = dev_get_drvdata(dev);
312 unsigned int reg;
313 u8 regs[6];
314 int ret;
315
316 regs[0] = bin2bcd(alrm->time.tm_sec);
317 regs[1] = bin2bcd(alrm->time.tm_min);
318 regs[2] = bin2bcd(alrm->time.tm_hour);
319 regs[3] = bin2bcd(alrm->time.tm_mday);
320 regs[4] = bin2bcd(alrm->time.tm_mon + 1);
321 regs[5] = bin2bcd(alrm->time.tm_year % 100);
322
323 ret = regmap_bulk_write(max31335->regmap, MAX31335_ALM1_SEC,
324 regs, sizeof(regs));
325 if (ret)
326 return ret;
327
328 reg = FIELD_PREP(MAX31335_INT_EN1_A1IE, alrm->enabled);
329 ret = regmap_update_bits(max31335->regmap, MAX31335_INT_EN1,
330 MAX31335_INT_EN1_A1IE, reg);
331 if (ret)
332 return ret;
333
334 ret = regmap_update_bits(max31335->regmap, MAX31335_STATUS1,
335 MAX31335_STATUS1_A1F, 0);
336
337 return 0;
338 }
339
max31335_alarm_irq_enable(struct device * dev,unsigned int enabled)340 static int max31335_alarm_irq_enable(struct device *dev, unsigned int enabled)
341 {
342 struct max31335_data *max31335 = dev_get_drvdata(dev);
343
344 return regmap_update_bits(max31335->regmap, MAX31335_INT_EN1,
345 MAX31335_INT_EN1_A1IE, enabled);
346 }
347
max31335_handle_irq(int irq,void * dev_id)348 static irqreturn_t max31335_handle_irq(int irq, void *dev_id)
349 {
350 struct max31335_data *max31335 = dev_id;
351 bool status;
352 int ret;
353
354 ret = regmap_update_bits_check(max31335->regmap, MAX31335_STATUS1,
355 MAX31335_STATUS1_A1F, 0, &status);
356 if (ret)
357 return IRQ_HANDLED;
358
359 if (status)
360 rtc_update_irq(max31335->rtc, 1, RTC_AF | RTC_IRQF);
361
362 return IRQ_HANDLED;
363 }
364
365 static const struct rtc_class_ops max31335_rtc_ops = {
366 .read_time = max31335_read_time,
367 .set_time = max31335_set_time,
368 .read_alarm = max31335_read_alarm,
369 .set_alarm = max31335_set_alarm,
370 .alarm_irq_enable = max31335_alarm_irq_enable,
371 };
372
max31335_trickle_charger_setup(struct device * dev,struct max31335_data * max31335)373 static int max31335_trickle_charger_setup(struct device *dev,
374 struct max31335_data *max31335)
375 {
376 u32 ohms, chargeable;
377 int i, trickle_cfg;
378 const char *diode;
379
380 if (device_property_read_u32(dev, "aux-voltage-chargeable",
381 &chargeable))
382 return 0;
383
384 if (device_property_read_u32(dev, "trickle-resistor-ohms", &ohms))
385 return 0;
386
387 if (device_property_read_string(dev, "adi,tc-diode", &diode))
388 return 0;
389
390 if (!strcmp(diode, "schottky"))
391 trickle_cfg = MAX31335_TRICKLE_SCHOTTKY_DIODE;
392 else if (!strcmp(diode, "standard+schottky"))
393 trickle_cfg = MAX31335_TRICKLE_STANDARD_DIODE;
394 else
395 return dev_err_probe(dev, -EINVAL,
396 "Invalid tc-diode value: %s\n", diode);
397
398 for (i = 0; i < ARRAY_SIZE(max31335_trickle_resistors); i++)
399 if (ohms == max31335_trickle_resistors[i])
400 break;
401
402 if (i >= ARRAY_SIZE(max31335_trickle_resistors))
403 return 0;
404
405 i = i + trickle_cfg;
406
407 return regmap_write(max31335->regmap, MAX31335_TRICKLE_REG,
408 FIELD_PREP(MAX31335_TRICKLE_REG_TRICKLE, i) |
409 FIELD_PREP(MAX31335_TRICKLE_REG_EN_TRICKLE,
410 chargeable));
411 }
412
max31335_clkout_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)413 static unsigned long max31335_clkout_recalc_rate(struct clk_hw *hw,
414 unsigned long parent_rate)
415 {
416 struct max31335_data *max31335 = clk_hw_to_max31335(hw);
417 unsigned int freq_mask;
418 unsigned int reg;
419 int ret;
420
421 ret = regmap_read(max31335->regmap, MAX31335_RTC_CONFIG2, ®);
422 if (ret)
423 return 0;
424
425 freq_mask = __roundup_pow_of_two(ARRAY_SIZE(max31335_clkout_freq)) - 1;
426
427 return max31335_clkout_freq[reg & freq_mask];
428 }
429
max31335_clkout_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)430 static long max31335_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
431 unsigned long *prate)
432 {
433 int index;
434
435 index = find_closest(rate, max31335_clkout_freq,
436 ARRAY_SIZE(max31335_clkout_freq));
437
438 return max31335_clkout_freq[index];
439 }
440
max31335_clkout_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)441 static int max31335_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
442 unsigned long parent_rate)
443 {
444 struct max31335_data *max31335 = clk_hw_to_max31335(hw);
445 unsigned int freq_mask;
446 int index;
447
448 index = find_closest(rate, max31335_clkout_freq,
449 ARRAY_SIZE(max31335_clkout_freq));
450 freq_mask = __roundup_pow_of_two(ARRAY_SIZE(max31335_clkout_freq)) - 1;
451
452 return regmap_update_bits(max31335->regmap, MAX31335_RTC_CONFIG2,
453 freq_mask, index);
454 }
455
max31335_clkout_enable(struct clk_hw * hw)456 static int max31335_clkout_enable(struct clk_hw *hw)
457 {
458 struct max31335_data *max31335 = clk_hw_to_max31335(hw);
459
460 return regmap_set_bits(max31335->regmap, MAX31335_RTC_CONFIG2,
461 MAX31335_RTC_CONFIG2_ENCLKO);
462 }
463
max31335_clkout_disable(struct clk_hw * hw)464 static void max31335_clkout_disable(struct clk_hw *hw)
465 {
466 struct max31335_data *max31335 = clk_hw_to_max31335(hw);
467
468 regmap_clear_bits(max31335->regmap, MAX31335_RTC_CONFIG2,
469 MAX31335_RTC_CONFIG2_ENCLKO);
470 }
471
max31335_clkout_is_enabled(struct clk_hw * hw)472 static int max31335_clkout_is_enabled(struct clk_hw *hw)
473 {
474 struct max31335_data *max31335 = clk_hw_to_max31335(hw);
475 unsigned int reg;
476 int ret;
477
478 ret = regmap_read(max31335->regmap, MAX31335_RTC_CONFIG2, ®);
479 if (ret)
480 return ret;
481
482 return !!(reg & MAX31335_RTC_CONFIG2_ENCLKO);
483 }
484
485 static const struct clk_ops max31335_clkout_ops = {
486 .recalc_rate = max31335_clkout_recalc_rate,
487 .round_rate = max31335_clkout_round_rate,
488 .set_rate = max31335_clkout_set_rate,
489 .enable = max31335_clkout_enable,
490 .disable = max31335_clkout_disable,
491 .is_enabled = max31335_clkout_is_enabled,
492 };
493
494 static struct clk_init_data max31335_clk_init = {
495 .name = "max31335-clkout",
496 .ops = &max31335_clkout_ops,
497 };
498
max31335_nvmem_reg_read(void * priv,unsigned int offset,void * val,size_t bytes)499 static int max31335_nvmem_reg_read(void *priv, unsigned int offset,
500 void *val, size_t bytes)
501 {
502 struct max31335_data *max31335 = priv;
503 unsigned int reg = MAX31335_TS0_SEC_1_128 + offset;
504
505 return regmap_bulk_read(max31335->regmap, reg, val, bytes);
506 }
507
max31335_nvmem_reg_write(void * priv,unsigned int offset,void * val,size_t bytes)508 static int max31335_nvmem_reg_write(void *priv, unsigned int offset,
509 void *val, size_t bytes)
510 {
511 struct max31335_data *max31335 = priv;
512 unsigned int reg = MAX31335_TS0_SEC_1_128 + offset;
513
514 return regmap_bulk_write(max31335->regmap, reg, val, bytes);
515 }
516
517 static struct nvmem_config max31335_nvmem_cfg = {
518 .reg_read = max31335_nvmem_reg_read,
519 .reg_write = max31335_nvmem_reg_write,
520 .word_size = 8,
521 .size = MAX31335_RAM_SIZE,
522 };
523
524 #if IS_REACHABLE(HWMON)
max31335_read_temp(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)525 static int max31335_read_temp(struct device *dev, enum hwmon_sensor_types type,
526 u32 attr, int channel, long *val)
527 {
528 struct max31335_data *max31335 = dev_get_drvdata(dev);
529 u8 reg[2];
530 s16 temp;
531 int ret;
532
533 if (type != hwmon_temp || attr != hwmon_temp_input)
534 return -EOPNOTSUPP;
535
536 ret = regmap_bulk_read(max31335->regmap, MAX31335_TEMP_DATA_MSB,
537 reg, 2);
538 if (ret)
539 return ret;
540
541 temp = get_unaligned_be16(reg);
542
543 *val = (temp / 64) * 250;
544
545 return 0;
546 }
547
max31335_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)548 static umode_t max31335_is_visible(const void *data,
549 enum hwmon_sensor_types type,
550 u32 attr, int channel)
551 {
552 if (type == hwmon_temp && attr == hwmon_temp_input)
553 return 0444;
554
555 return 0;
556 }
557
558 static const struct hwmon_channel_info *max31335_info[] = {
559 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
560 NULL
561 };
562
563 static const struct hwmon_ops max31335_hwmon_ops = {
564 .is_visible = max31335_is_visible,
565 .read = max31335_read_temp,
566 };
567
568 static const struct hwmon_chip_info max31335_chip_info = {
569 .ops = &max31335_hwmon_ops,
570 .info = max31335_info,
571 };
572 #endif
573
max31335_clkout_register(struct device * dev)574 static int max31335_clkout_register(struct device *dev)
575 {
576 struct max31335_data *max31335 = dev_get_drvdata(dev);
577 int ret;
578
579 if (!device_property_present(dev, "#clock-cells"))
580 return regmap_clear_bits(max31335->regmap, MAX31335_RTC_CONFIG2,
581 MAX31335_RTC_CONFIG2_ENCLKO);
582
583 max31335->clkout.init = &max31335_clk_init;
584
585 ret = devm_clk_hw_register(dev, &max31335->clkout);
586 if (ret)
587 return dev_err_probe(dev, ret, "cannot register clock\n");
588
589 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
590 &max31335->clkout);
591 if (ret)
592 return dev_err_probe(dev, ret, "cannot add hw provider\n");
593
594 max31335->clkout.clk = devm_clk_get_enabled(dev, NULL);
595 if (IS_ERR(max31335->clkout.clk))
596 return dev_err_probe(dev, PTR_ERR(max31335->clkout.clk),
597 "cannot enable clkout\n");
598
599 return 0;
600 }
601
max31335_probe(struct i2c_client * client)602 static int max31335_probe(struct i2c_client *client)
603 {
604 struct max31335_data *max31335;
605 #if IS_REACHABLE(HWMON)
606 struct device *hwmon;
607 #endif
608 int ret;
609
610 max31335 = devm_kzalloc(&client->dev, sizeof(*max31335), GFP_KERNEL);
611 if (!max31335)
612 return -ENOMEM;
613
614 max31335->regmap = devm_regmap_init_i2c(client, ®map_config);
615 if (IS_ERR(max31335->regmap))
616 return PTR_ERR(max31335->regmap);
617
618 i2c_set_clientdata(client, max31335);
619
620 max31335->rtc = devm_rtc_allocate_device(&client->dev);
621 if (IS_ERR(max31335->rtc))
622 return PTR_ERR(max31335->rtc);
623
624 max31335->rtc->ops = &max31335_rtc_ops;
625 max31335->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
626 max31335->rtc->range_max = RTC_TIMESTAMP_END_2199;
627 max31335->rtc->alarm_offset_max = 24 * 60 * 60;
628
629 ret = max31335_clkout_register(&client->dev);
630 if (ret)
631 return ret;
632
633 if (client->irq > 0) {
634 ret = devm_request_threaded_irq(&client->dev, client->irq,
635 NULL, max31335_handle_irq,
636 IRQF_ONESHOT,
637 "max31335", max31335);
638 if (ret) {
639 dev_warn(&client->dev,
640 "unable to request IRQ, alarm max31335 disabled\n");
641 client->irq = 0;
642 }
643 }
644
645 if (!client->irq)
646 clear_bit(RTC_FEATURE_ALARM, max31335->rtc->features);
647
648 max31335_nvmem_cfg.priv = max31335;
649 ret = devm_rtc_nvmem_register(max31335->rtc, &max31335_nvmem_cfg);
650 if (ret)
651 return dev_err_probe(&client->dev, ret,
652 "cannot register rtc nvmem\n");
653
654 #if IS_REACHABLE(HWMON)
655 hwmon = devm_hwmon_device_register_with_info(&client->dev, client->name,
656 max31335,
657 &max31335_chip_info,
658 NULL);
659 if (IS_ERR(hwmon))
660 return dev_err_probe(&client->dev, PTR_ERR(hwmon),
661 "cannot register hwmon device\n");
662 #endif
663
664 ret = max31335_trickle_charger_setup(&client->dev, max31335);
665 if (ret)
666 return ret;
667
668 return devm_rtc_register_device(max31335->rtc);
669 }
670
671 static const struct i2c_device_id max31335_id[] = {
672 { "max31335" },
673 { }
674 };
675
676 MODULE_DEVICE_TABLE(i2c, max31335_id);
677
678 static const struct of_device_id max31335_of_match[] = {
679 { .compatible = "adi,max31335" },
680 { }
681 };
682
683 MODULE_DEVICE_TABLE(of, max31335_of_match);
684
685 static struct i2c_driver max31335_driver = {
686 .driver = {
687 .name = "rtc-max31335",
688 .of_match_table = max31335_of_match,
689 },
690 .probe = max31335_probe,
691 .id_table = max31335_id,
692 };
693 module_i2c_driver(max31335_driver);
694
695 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>");
696 MODULE_DESCRIPTION("MAX31335 RTC driver");
697 MODULE_LICENSE("GPL");
698