1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ST M48T59 RTC driver 4 * 5 * Copyright (c) 2007 Wind River Systems, Inc. 6 * 7 * Author: Mark Zhan <rongkai.zhan@windriver.com> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/init.h> 13 #include <linux/io.h> 14 #include <linux/device.h> 15 #include <linux/platform_device.h> 16 #include <linux/rtc.h> 17 #include <linux/rtc/m48t59.h> 18 #include <linux/bcd.h> 19 #include <linux/slab.h> 20 21 #ifndef NO_IRQ 22 #define NO_IRQ (-1) 23 #endif 24 25 #define M48T59_READ(reg) (pdata->read_byte(dev, pdata->offset + reg)) 26 #define M48T59_WRITE(val, reg) \ 27 (pdata->write_byte(dev, pdata->offset + reg, val)) 28 29 #define M48T59_SET_BITS(mask, reg) \ 30 M48T59_WRITE((M48T59_READ(reg) | (mask)), (reg)) 31 #define M48T59_CLEAR_BITS(mask, reg) \ 32 M48T59_WRITE((M48T59_READ(reg) & ~(mask)), (reg)) 33 34 struct m48t59_private { 35 void __iomem *ioaddr; 36 int irq; 37 struct rtc_device *rtc; 38 spinlock_t lock; /* serialize the NVRAM and RTC access */ 39 }; 40 41 /* 42 * This is the generic access method when the chip is memory-mapped 43 */ 44 static void 45 m48t59_mem_writeb(struct device *dev, u32 ofs, u8 val) 46 { 47 struct m48t59_private *m48t59 = dev_get_drvdata(dev); 48 49 writeb(val, m48t59->ioaddr+ofs); 50 } 51 52 static u8 53 m48t59_mem_readb(struct device *dev, u32 ofs) 54 { 55 struct m48t59_private *m48t59 = dev_get_drvdata(dev); 56 57 return readb(m48t59->ioaddr+ofs); 58 } 59 60 /* 61 * NOTE: M48T59 only uses BCD mode 62 */ 63 static int m48t59_rtc_read_time(struct device *dev, struct rtc_time *tm) 64 { 65 struct m48t59_plat_data *pdata = dev_get_platdata(dev); 66 struct m48t59_private *m48t59 = dev_get_drvdata(dev); 67 unsigned long flags; 68 u8 val; 69 70 spin_lock_irqsave(&m48t59->lock, flags); 71 /* Issue the READ command */ 72 M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL); 73 74 tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR)) + pdata->yy_offset; 75 /* tm_mon is 0-11 */ 76 tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1; 77 tm->tm_mday = bcd2bin(M48T59_READ(M48T59_MDAY)); 78 79 val = M48T59_READ(M48T59_WDAY); 80 if ((pdata->type == M48T59RTC_TYPE_M48T59) && 81 (val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB)) { 82 dev_dbg(dev, "Century bit is enabled\n"); 83 tm->tm_year += 100; /* one century */ 84 } 85 86 tm->tm_wday = bcd2bin(val & 0x07); 87 tm->tm_hour = bcd2bin(M48T59_READ(M48T59_HOUR) & 0x3F); 88 tm->tm_min = bcd2bin(M48T59_READ(M48T59_MIN) & 0x7F); 89 tm->tm_sec = bcd2bin(M48T59_READ(M48T59_SEC) & 0x7F); 90 91 /* Clear the READ bit */ 92 M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL); 93 spin_unlock_irqrestore(&m48t59->lock, flags); 94 95 dev_dbg(dev, "RTC read time %ptR\n", tm); 96 return 0; 97 } 98 99 static int m48t59_rtc_set_time(struct device *dev, struct rtc_time *tm) 100 { 101 struct m48t59_plat_data *pdata = dev_get_platdata(dev); 102 struct m48t59_private *m48t59 = dev_get_drvdata(dev); 103 unsigned long flags; 104 u8 val = 0; 105 int year = tm->tm_year - pdata->yy_offset; 106 107 dev_dbg(dev, "RTC set time %04d-%02d-%02d %02d/%02d/%02d\n", 108 year + 1900, tm->tm_mon, tm->tm_mday, 109 tm->tm_hour, tm->tm_min, tm->tm_sec); 110 111 if (year < 0) 112 return -EINVAL; 113 114 spin_lock_irqsave(&m48t59->lock, flags); 115 /* Issue the WRITE command */ 116 M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL); 117 118 M48T59_WRITE((bin2bcd(tm->tm_sec) & 0x7F), M48T59_SEC); 119 M48T59_WRITE((bin2bcd(tm->tm_min) & 0x7F), M48T59_MIN); 120 M48T59_WRITE((bin2bcd(tm->tm_hour) & 0x3F), M48T59_HOUR); 121 M48T59_WRITE((bin2bcd(tm->tm_mday) & 0x3F), M48T59_MDAY); 122 /* tm_mon is 0-11 */ 123 M48T59_WRITE((bin2bcd(tm->tm_mon + 1) & 0x1F), M48T59_MONTH); 124 M48T59_WRITE(bin2bcd(year % 100), M48T59_YEAR); 125 126 if (pdata->type == M48T59RTC_TYPE_M48T59 && (year >= 100)) 127 val = (M48T59_WDAY_CEB | M48T59_WDAY_CB); 128 val |= (bin2bcd(tm->tm_wday) & 0x07); 129 M48T59_WRITE(val, M48T59_WDAY); 130 131 /* Clear the WRITE bit */ 132 M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL); 133 spin_unlock_irqrestore(&m48t59->lock, flags); 134 return 0; 135 } 136 137 /* 138 * Read alarm time and date in RTC 139 */ 140 static int m48t59_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) 141 { 142 struct m48t59_plat_data *pdata = dev_get_platdata(dev); 143 struct m48t59_private *m48t59 = dev_get_drvdata(dev); 144 struct rtc_time *tm = &alrm->time; 145 unsigned long flags; 146 u8 val; 147 148 /* If no irq, we don't support ALARM */ 149 if (m48t59->irq == NO_IRQ) 150 return -EIO; 151 152 spin_lock_irqsave(&m48t59->lock, flags); 153 /* Issue the READ command */ 154 M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL); 155 156 tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR)) + pdata->yy_offset; 157 /* tm_mon is 0-11 */ 158 tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1; 159 160 val = M48T59_READ(M48T59_WDAY); 161 if ((val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB)) 162 tm->tm_year += 100; /* one century */ 163 164 tm->tm_mday = bcd2bin(M48T59_READ(M48T59_ALARM_DATE)); 165 tm->tm_hour = bcd2bin(M48T59_READ(M48T59_ALARM_HOUR)); 166 tm->tm_min = bcd2bin(M48T59_READ(M48T59_ALARM_MIN)); 167 tm->tm_sec = bcd2bin(M48T59_READ(M48T59_ALARM_SEC)); 168 169 /* Clear the READ bit */ 170 M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL); 171 spin_unlock_irqrestore(&m48t59->lock, flags); 172 173 dev_dbg(dev, "RTC read alarm time %ptR\n", tm); 174 return rtc_valid_tm(tm); 175 } 176 177 /* 178 * Set alarm time and date in RTC 179 */ 180 static int m48t59_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) 181 { 182 struct m48t59_plat_data *pdata = dev_get_platdata(dev); 183 struct m48t59_private *m48t59 = dev_get_drvdata(dev); 184 struct rtc_time *tm = &alrm->time; 185 u8 mday, hour, min, sec; 186 unsigned long flags; 187 int year = tm->tm_year - pdata->yy_offset; 188 189 /* If no irq, we don't support ALARM */ 190 if (m48t59->irq == NO_IRQ) 191 return -EIO; 192 193 if (year < 0) 194 return -EINVAL; 195 196 /* 197 * 0xff means "always match" 198 */ 199 mday = tm->tm_mday; 200 mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff; 201 if (mday == 0xff) 202 mday = M48T59_READ(M48T59_MDAY); 203 204 hour = tm->tm_hour; 205 hour = (hour < 24) ? bin2bcd(hour) : 0x00; 206 207 min = tm->tm_min; 208 min = (min < 60) ? bin2bcd(min) : 0x00; 209 210 sec = tm->tm_sec; 211 sec = (sec < 60) ? bin2bcd(sec) : 0x00; 212 213 spin_lock_irqsave(&m48t59->lock, flags); 214 /* Issue the WRITE command */ 215 M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL); 216 217 M48T59_WRITE(mday, M48T59_ALARM_DATE); 218 M48T59_WRITE(hour, M48T59_ALARM_HOUR); 219 M48T59_WRITE(min, M48T59_ALARM_MIN); 220 M48T59_WRITE(sec, M48T59_ALARM_SEC); 221 222 /* Clear the WRITE bit */ 223 M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL); 224 spin_unlock_irqrestore(&m48t59->lock, flags); 225 226 dev_dbg(dev, "RTC set alarm time %04d-%02d-%02d %02d/%02d/%02d\n", 227 year + 1900, tm->tm_mon, tm->tm_mday, 228 tm->tm_hour, tm->tm_min, tm->tm_sec); 229 return 0; 230 } 231 232 /* 233 * Handle commands from user-space 234 */ 235 static int m48t59_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 236 { 237 struct m48t59_plat_data *pdata = dev_get_platdata(dev); 238 struct m48t59_private *m48t59 = dev_get_drvdata(dev); 239 unsigned long flags; 240 241 spin_lock_irqsave(&m48t59->lock, flags); 242 if (enabled) 243 M48T59_WRITE(M48T59_INTR_AFE, M48T59_INTR); 244 else 245 M48T59_WRITE(0x00, M48T59_INTR); 246 spin_unlock_irqrestore(&m48t59->lock, flags); 247 248 return 0; 249 } 250 251 static int m48t59_rtc_proc(struct device *dev, struct seq_file *seq) 252 { 253 struct m48t59_plat_data *pdata = dev_get_platdata(dev); 254 struct m48t59_private *m48t59 = dev_get_drvdata(dev); 255 unsigned long flags; 256 u8 val; 257 258 spin_lock_irqsave(&m48t59->lock, flags); 259 val = M48T59_READ(M48T59_FLAGS); 260 spin_unlock_irqrestore(&m48t59->lock, flags); 261 262 seq_printf(seq, "battery\t\t: %s\n", 263 (val & M48T59_FLAGS_BF) ? "low" : "normal"); 264 return 0; 265 } 266 267 /* 268 * IRQ handler for the RTC 269 */ 270 static irqreturn_t m48t59_rtc_interrupt(int irq, void *dev_id) 271 { 272 struct device *dev = (struct device *)dev_id; 273 struct m48t59_plat_data *pdata = dev_get_platdata(dev); 274 struct m48t59_private *m48t59 = dev_get_drvdata(dev); 275 u8 event; 276 277 spin_lock(&m48t59->lock); 278 event = M48T59_READ(M48T59_FLAGS); 279 spin_unlock(&m48t59->lock); 280 281 if (event & M48T59_FLAGS_AF) { 282 rtc_update_irq(m48t59->rtc, 1, (RTC_AF | RTC_IRQF)); 283 return IRQ_HANDLED; 284 } 285 286 return IRQ_NONE; 287 } 288 289 static const struct rtc_class_ops m48t59_rtc_ops = { 290 .read_time = m48t59_rtc_read_time, 291 .set_time = m48t59_rtc_set_time, 292 .read_alarm = m48t59_rtc_readalarm, 293 .set_alarm = m48t59_rtc_setalarm, 294 .proc = m48t59_rtc_proc, 295 .alarm_irq_enable = m48t59_rtc_alarm_irq_enable, 296 }; 297 298 static int m48t59_nvram_read(void *priv, unsigned int offset, void *val, 299 size_t size) 300 { 301 struct platform_device *pdev = priv; 302 struct device *dev = &pdev->dev; 303 struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev); 304 struct m48t59_private *m48t59 = platform_get_drvdata(pdev); 305 ssize_t cnt = 0; 306 unsigned long flags; 307 u8 *buf = val; 308 309 spin_lock_irqsave(&m48t59->lock, flags); 310 311 for (; cnt < size; cnt++) 312 *buf++ = M48T59_READ(cnt); 313 314 spin_unlock_irqrestore(&m48t59->lock, flags); 315 316 return 0; 317 } 318 319 static int m48t59_nvram_write(void *priv, unsigned int offset, void *val, 320 size_t size) 321 { 322 struct platform_device *pdev = priv; 323 struct device *dev = &pdev->dev; 324 struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev); 325 struct m48t59_private *m48t59 = platform_get_drvdata(pdev); 326 ssize_t cnt = 0; 327 unsigned long flags; 328 u8 *buf = val; 329 330 spin_lock_irqsave(&m48t59->lock, flags); 331 332 for (; cnt < size; cnt++) 333 M48T59_WRITE(*buf++, cnt); 334 335 spin_unlock_irqrestore(&m48t59->lock, flags); 336 337 return 0; 338 } 339 340 static int m48t59_rtc_probe(struct platform_device *pdev) 341 { 342 struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev); 343 struct m48t59_private *m48t59 = NULL; 344 struct resource *res; 345 int ret = -ENOMEM; 346 struct nvmem_config nvmem_cfg = { 347 .name = "m48t59-", 348 .word_size = 1, 349 .stride = 1, 350 .reg_read = m48t59_nvram_read, 351 .reg_write = m48t59_nvram_write, 352 .priv = pdev, 353 }; 354 355 /* This chip could be memory-mapped or I/O-mapped */ 356 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 357 if (!res) { 358 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 359 if (!res) 360 return -EINVAL; 361 } 362 363 if (res->flags & IORESOURCE_IO) { 364 /* If we are I/O-mapped, the platform should provide 365 * the operations accessing chip registers. 366 */ 367 if (!pdata || !pdata->write_byte || !pdata->read_byte) 368 return -EINVAL; 369 } else if (res->flags & IORESOURCE_MEM) { 370 /* we are memory-mapped */ 371 if (!pdata) { 372 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), 373 GFP_KERNEL); 374 if (!pdata) 375 return -ENOMEM; 376 /* Ensure we only kmalloc platform data once */ 377 pdev->dev.platform_data = pdata; 378 } 379 if (!pdata->type) 380 pdata->type = M48T59RTC_TYPE_M48T59; 381 382 /* Try to use the generic memory read/write ops */ 383 if (!pdata->write_byte) 384 pdata->write_byte = m48t59_mem_writeb; 385 if (!pdata->read_byte) 386 pdata->read_byte = m48t59_mem_readb; 387 } 388 389 m48t59 = devm_kzalloc(&pdev->dev, sizeof(*m48t59), GFP_KERNEL); 390 if (!m48t59) 391 return -ENOMEM; 392 393 m48t59->ioaddr = pdata->ioaddr; 394 395 if (!m48t59->ioaddr) { 396 /* ioaddr not mapped externally */ 397 m48t59->ioaddr = devm_ioremap(&pdev->dev, res->start, 398 resource_size(res)); 399 if (!m48t59->ioaddr) 400 return ret; 401 } 402 403 /* Try to get irq number. We also can work in 404 * the mode without IRQ. 405 */ 406 m48t59->irq = platform_get_irq_optional(pdev, 0); 407 if (m48t59->irq <= 0) 408 m48t59->irq = NO_IRQ; 409 410 if (m48t59->irq != NO_IRQ) { 411 ret = devm_request_irq(&pdev->dev, m48t59->irq, 412 m48t59_rtc_interrupt, IRQF_SHARED, 413 "rtc-m48t59", &pdev->dev); 414 if (ret) 415 return ret; 416 } 417 418 m48t59->rtc = devm_rtc_allocate_device(&pdev->dev); 419 if (IS_ERR(m48t59->rtc)) 420 return PTR_ERR(m48t59->rtc); 421 422 switch (pdata->type) { 423 case M48T59RTC_TYPE_M48T59: 424 pdata->offset = 0x1ff0; 425 break; 426 case M48T59RTC_TYPE_M48T02: 427 clear_bit(RTC_FEATURE_ALARM, m48t59->rtc->features); 428 pdata->offset = 0x7f0; 429 break; 430 case M48T59RTC_TYPE_M48T08: 431 clear_bit(RTC_FEATURE_ALARM, m48t59->rtc->features); 432 pdata->offset = 0x1ff0; 433 break; 434 default: 435 dev_err(&pdev->dev, "Unknown RTC type\n"); 436 return -ENODEV; 437 } 438 439 spin_lock_init(&m48t59->lock); 440 platform_set_drvdata(pdev, m48t59); 441 442 m48t59->rtc->ops = &m48t59_rtc_ops; 443 m48t59->rtc->range_min = RTC_TIMESTAMP_BEGIN_1900; 444 m48t59->rtc->range_max = RTC_TIMESTAMP_END_2099; 445 446 nvmem_cfg.size = pdata->offset; 447 ret = devm_rtc_nvmem_register(m48t59->rtc, &nvmem_cfg); 448 if (ret) 449 return ret; 450 451 ret = devm_rtc_register_device(m48t59->rtc); 452 if (ret) 453 return ret; 454 455 return 0; 456 } 457 458 /* work with hotplug and coldplug */ 459 MODULE_ALIAS("platform:rtc-m48t59"); 460 461 static struct platform_driver m48t59_rtc_driver = { 462 .driver = { 463 .name = "rtc-m48t59", 464 }, 465 .probe = m48t59_rtc_probe, 466 }; 467 468 module_platform_driver(m48t59_rtc_driver); 469 470 MODULE_AUTHOR("Mark Zhan <rongkai.zhan@windriver.com>"); 471 MODULE_DESCRIPTION("M48T59/M48T02/M48T08 RTC driver"); 472 MODULE_LICENSE("GPL"); 473