xref: /linux/drivers/rtc/rtc-loongson.c (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1*1b733a9eSBinbin Zhou // SPDX-License-Identifier: GPL-2.0-or-later
2*1b733a9eSBinbin Zhou /*
3*1b733a9eSBinbin Zhou  * Loongson RTC driver
4*1b733a9eSBinbin Zhou  *
5*1b733a9eSBinbin Zhou  * Maintained out-of-tree by Huacai Chen <chenhuacai@kernel.org>.
6*1b733a9eSBinbin Zhou  * Rewritten for mainline by WANG Xuerui <git@xen0n.name>.
7*1b733a9eSBinbin Zhou  *                           Binbin Zhou <zhoubinbin@loongson.cn>
8*1b733a9eSBinbin Zhou  */
9*1b733a9eSBinbin Zhou 
10*1b733a9eSBinbin Zhou #include <linux/bitfield.h>
11*1b733a9eSBinbin Zhou #include <linux/kernel.h>
12*1b733a9eSBinbin Zhou #include <linux/module.h>
13*1b733a9eSBinbin Zhou #include <linux/platform_device.h>
14*1b733a9eSBinbin Zhou #include <linux/regmap.h>
15*1b733a9eSBinbin Zhou #include <linux/rtc.h>
16*1b733a9eSBinbin Zhou #include <linux/acpi.h>
17*1b733a9eSBinbin Zhou 
18*1b733a9eSBinbin Zhou /* Time Of Year(TOY) counters registers */
19*1b733a9eSBinbin Zhou #define TOY_TRIM_REG		0x20 /* Must be initialized to 0 */
20*1b733a9eSBinbin Zhou #define TOY_WRITE0_REG		0x24 /* TOY low 32-bits value (write-only) */
21*1b733a9eSBinbin Zhou #define TOY_WRITE1_REG		0x28 /* TOY high 32-bits value (write-only) */
22*1b733a9eSBinbin Zhou #define TOY_READ0_REG		0x2c /* TOY low 32-bits value (read-only) */
23*1b733a9eSBinbin Zhou #define TOY_READ1_REG		0x30 /* TOY high 32-bits value (read-only) */
24*1b733a9eSBinbin Zhou #define TOY_MATCH0_REG		0x34 /* TOY timing interrupt 0 */
25*1b733a9eSBinbin Zhou #define TOY_MATCH1_REG		0x38 /* TOY timing interrupt 1 */
26*1b733a9eSBinbin Zhou #define TOY_MATCH2_REG		0x3c /* TOY timing interrupt 2 */
27*1b733a9eSBinbin Zhou 
28*1b733a9eSBinbin Zhou /* RTC counters registers */
29*1b733a9eSBinbin Zhou #define RTC_CTRL_REG		0x40 /* TOY and RTC control register */
30*1b733a9eSBinbin Zhou #define RTC_TRIM_REG		0x60 /* Must be initialized to 0 */
31*1b733a9eSBinbin Zhou #define RTC_WRITE0_REG		0x64 /* RTC counters value (write-only) */
32*1b733a9eSBinbin Zhou #define RTC_READ0_REG		0x68 /* RTC counters value (read-only) */
33*1b733a9eSBinbin Zhou #define RTC_MATCH0_REG		0x6c /* RTC timing interrupt 0 */
34*1b733a9eSBinbin Zhou #define RTC_MATCH1_REG		0x70 /* RTC timing interrupt 1 */
35*1b733a9eSBinbin Zhou #define RTC_MATCH2_REG		0x74 /* RTC timing interrupt 2 */
36*1b733a9eSBinbin Zhou 
37*1b733a9eSBinbin Zhou /* bitmask of TOY_WRITE0_REG */
38*1b733a9eSBinbin Zhou #define TOY_MON			GENMASK(31, 26)
39*1b733a9eSBinbin Zhou #define TOY_DAY			GENMASK(25, 21)
40*1b733a9eSBinbin Zhou #define TOY_HOUR		GENMASK(20, 16)
41*1b733a9eSBinbin Zhou #define TOY_MIN			GENMASK(15, 10)
42*1b733a9eSBinbin Zhou #define TOY_SEC			GENMASK(9, 4)
43*1b733a9eSBinbin Zhou #define TOY_MSEC		GENMASK(3, 0)
44*1b733a9eSBinbin Zhou 
45*1b733a9eSBinbin Zhou /* bitmask of TOY_MATCH0/1/2_REG */
46*1b733a9eSBinbin Zhou #define TOY_MATCH_YEAR		GENMASK(31, 26)
47*1b733a9eSBinbin Zhou #define TOY_MATCH_MON		GENMASK(25, 22)
48*1b733a9eSBinbin Zhou #define TOY_MATCH_DAY		GENMASK(21, 17)
49*1b733a9eSBinbin Zhou #define TOY_MATCH_HOUR		GENMASK(16, 12)
50*1b733a9eSBinbin Zhou #define TOY_MATCH_MIN		GENMASK(11, 6)
51*1b733a9eSBinbin Zhou #define TOY_MATCH_SEC		GENMASK(5, 0)
52*1b733a9eSBinbin Zhou 
53*1b733a9eSBinbin Zhou /* bitmask of RTC_CTRL_REG */
54*1b733a9eSBinbin Zhou #define RTC_ENABLE		BIT(13) /* 1: RTC counters enable */
55*1b733a9eSBinbin Zhou #define TOY_ENABLE		BIT(11) /* 1: TOY counters enable */
56*1b733a9eSBinbin Zhou #define OSC_ENABLE		BIT(8) /* 1: 32.768k crystal enable */
57*1b733a9eSBinbin Zhou #define TOY_ENABLE_MASK		(TOY_ENABLE | OSC_ENABLE)
58*1b733a9eSBinbin Zhou 
59*1b733a9eSBinbin Zhou /* PM domain registers */
60*1b733a9eSBinbin Zhou #define PM1_STS_REG		0x0c	/* Power management 1 status register */
61*1b733a9eSBinbin Zhou #define RTC_STS			BIT(10)	/* RTC status */
62*1b733a9eSBinbin Zhou #define PM1_EN_REG		0x10	/* Power management 1 enable register */
63*1b733a9eSBinbin Zhou #define RTC_EN			BIT(10)	/* RTC event enable */
64*1b733a9eSBinbin Zhou 
65*1b733a9eSBinbin Zhou /*
66*1b733a9eSBinbin Zhou  * According to the LS1C manual, RTC_CTRL and alarm-related registers are not defined.
67*1b733a9eSBinbin Zhou  * Accessing the relevant registers will cause the system to hang.
68*1b733a9eSBinbin Zhou  */
69*1b733a9eSBinbin Zhou #define LS1C_RTC_CTRL_WORKAROUND	BIT(0)
70*1b733a9eSBinbin Zhou 
71*1b733a9eSBinbin Zhou struct loongson_rtc_config {
72*1b733a9eSBinbin Zhou 	u32 pm_offset;	/* Offset of PM domain, for RTC alarm wakeup */
73*1b733a9eSBinbin Zhou 	u32 flags;	/* Workaround bits */
74*1b733a9eSBinbin Zhou };
75*1b733a9eSBinbin Zhou 
76*1b733a9eSBinbin Zhou struct loongson_rtc_priv {
77*1b733a9eSBinbin Zhou 	spinlock_t lock;	/* protects PM registers access */
78*1b733a9eSBinbin Zhou 	u32 fix_year;		/* RTC alarm year compensation value */
79*1b733a9eSBinbin Zhou 	struct rtc_device *rtcdev;
80*1b733a9eSBinbin Zhou 	struct regmap *regmap;
81*1b733a9eSBinbin Zhou 	void __iomem *pm_base;	/* PM domain base, for RTC alarm wakeup */
82*1b733a9eSBinbin Zhou 	const struct loongson_rtc_config *config;
83*1b733a9eSBinbin Zhou };
84*1b733a9eSBinbin Zhou 
85*1b733a9eSBinbin Zhou static const struct loongson_rtc_config ls1b_rtc_config = {
86*1b733a9eSBinbin Zhou 	.pm_offset = 0,
87*1b733a9eSBinbin Zhou 	.flags = 0,
88*1b733a9eSBinbin Zhou };
89*1b733a9eSBinbin Zhou 
90*1b733a9eSBinbin Zhou static const struct loongson_rtc_config ls1c_rtc_config = {
91*1b733a9eSBinbin Zhou 	.pm_offset = 0,
92*1b733a9eSBinbin Zhou 	.flags = LS1C_RTC_CTRL_WORKAROUND,
93*1b733a9eSBinbin Zhou };
94*1b733a9eSBinbin Zhou 
95*1b733a9eSBinbin Zhou static const struct loongson_rtc_config generic_rtc_config = {
96*1b733a9eSBinbin Zhou 	.pm_offset = 0x100,
97*1b733a9eSBinbin Zhou 	.flags = 0,
98*1b733a9eSBinbin Zhou };
99*1b733a9eSBinbin Zhou 
100*1b733a9eSBinbin Zhou static const struct loongson_rtc_config ls2k1000_rtc_config = {
101*1b733a9eSBinbin Zhou 	.pm_offset = 0x800,
102*1b733a9eSBinbin Zhou 	.flags = 0,
103*1b733a9eSBinbin Zhou };
104*1b733a9eSBinbin Zhou 
105*1b733a9eSBinbin Zhou static const struct regmap_config loongson_rtc_regmap_config = {
106*1b733a9eSBinbin Zhou 	.reg_bits = 32,
107*1b733a9eSBinbin Zhou 	.val_bits = 32,
108*1b733a9eSBinbin Zhou 	.reg_stride = 4,
109*1b733a9eSBinbin Zhou };
110*1b733a9eSBinbin Zhou 
111*1b733a9eSBinbin Zhou /* RTC alarm irq handler */
loongson_rtc_isr(int irq,void * id)112*1b733a9eSBinbin Zhou static irqreturn_t loongson_rtc_isr(int irq, void *id)
113*1b733a9eSBinbin Zhou {
114*1b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = (struct loongson_rtc_priv *)id;
115*1b733a9eSBinbin Zhou 
116*1b733a9eSBinbin Zhou 	rtc_update_irq(priv->rtcdev, 1, RTC_AF | RTC_IRQF);
117*1b733a9eSBinbin Zhou 	return IRQ_HANDLED;
118*1b733a9eSBinbin Zhou }
119*1b733a9eSBinbin Zhou 
120*1b733a9eSBinbin Zhou /* For ACPI fixed event handler */
loongson_rtc_handler(void * id)121*1b733a9eSBinbin Zhou static u32 loongson_rtc_handler(void *id)
122*1b733a9eSBinbin Zhou {
123*1b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = (struct loongson_rtc_priv *)id;
124*1b733a9eSBinbin Zhou 
125*1b733a9eSBinbin Zhou 	spin_lock(&priv->lock);
126*1b733a9eSBinbin Zhou 	/* Disable RTC alarm wakeup and interrupt */
127*1b733a9eSBinbin Zhou 	writel(readl(priv->pm_base + PM1_EN_REG) & ~RTC_EN,
128*1b733a9eSBinbin Zhou 	       priv->pm_base + PM1_EN_REG);
129*1b733a9eSBinbin Zhou 
130*1b733a9eSBinbin Zhou 	/* Clear RTC interrupt status */
131*1b733a9eSBinbin Zhou 	writel(RTC_STS, priv->pm_base + PM1_STS_REG);
132*1b733a9eSBinbin Zhou 	spin_unlock(&priv->lock);
133*1b733a9eSBinbin Zhou 
134*1b733a9eSBinbin Zhou 	/*
135*1b733a9eSBinbin Zhou 	 * The TOY_MATCH0_REG should be cleared 0 here,
136*1b733a9eSBinbin Zhou 	 * otherwise the interrupt cannot be cleared.
137*1b733a9eSBinbin Zhou 	 */
138*1b733a9eSBinbin Zhou 	return regmap_write(priv->regmap, TOY_MATCH0_REG, 0);
139*1b733a9eSBinbin Zhou }
140*1b733a9eSBinbin Zhou 
loongson_rtc_set_enabled(struct device * dev)141*1b733a9eSBinbin Zhou static int loongson_rtc_set_enabled(struct device *dev)
142*1b733a9eSBinbin Zhou {
143*1b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
144*1b733a9eSBinbin Zhou 
145*1b733a9eSBinbin Zhou 	if (priv->config->flags & LS1C_RTC_CTRL_WORKAROUND)
146*1b733a9eSBinbin Zhou 		return 0;
147*1b733a9eSBinbin Zhou 
148*1b733a9eSBinbin Zhou 	/* Enable RTC TOY counters and crystal */
149*1b733a9eSBinbin Zhou 	return regmap_update_bits(priv->regmap, RTC_CTRL_REG, TOY_ENABLE_MASK,
150*1b733a9eSBinbin Zhou 				  TOY_ENABLE_MASK);
151*1b733a9eSBinbin Zhou }
152*1b733a9eSBinbin Zhou 
loongson_rtc_get_enabled(struct device * dev)153*1b733a9eSBinbin Zhou static bool loongson_rtc_get_enabled(struct device *dev)
154*1b733a9eSBinbin Zhou {
155*1b733a9eSBinbin Zhou 	int ret;
156*1b733a9eSBinbin Zhou 	u32 ctrl_data;
157*1b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
158*1b733a9eSBinbin Zhou 
159*1b733a9eSBinbin Zhou 	if (priv->config->flags & LS1C_RTC_CTRL_WORKAROUND)
160*1b733a9eSBinbin Zhou 		return true;
161*1b733a9eSBinbin Zhou 
162*1b733a9eSBinbin Zhou 	ret = regmap_read(priv->regmap, RTC_CTRL_REG, &ctrl_data);
163*1b733a9eSBinbin Zhou 	if (ret < 0)
164*1b733a9eSBinbin Zhou 		return false;
165*1b733a9eSBinbin Zhou 
166*1b733a9eSBinbin Zhou 	return ctrl_data & TOY_ENABLE_MASK;
167*1b733a9eSBinbin Zhou }
168*1b733a9eSBinbin Zhou 
loongson_rtc_read_time(struct device * dev,struct rtc_time * tm)169*1b733a9eSBinbin Zhou static int loongson_rtc_read_time(struct device *dev, struct rtc_time *tm)
170*1b733a9eSBinbin Zhou {
171*1b733a9eSBinbin Zhou 	int ret;
172*1b733a9eSBinbin Zhou 	u32 rtc_data[2];
173*1b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
174*1b733a9eSBinbin Zhou 
175*1b733a9eSBinbin Zhou 	if (!loongson_rtc_get_enabled(dev))
176*1b733a9eSBinbin Zhou 		return -EINVAL;
177*1b733a9eSBinbin Zhou 
178*1b733a9eSBinbin Zhou 	ret = regmap_bulk_read(priv->regmap, TOY_READ0_REG, rtc_data,
179*1b733a9eSBinbin Zhou 			       ARRAY_SIZE(rtc_data));
180*1b733a9eSBinbin Zhou 	if (ret < 0)
181*1b733a9eSBinbin Zhou 		return ret;
182*1b733a9eSBinbin Zhou 
183*1b733a9eSBinbin Zhou 	tm->tm_sec = FIELD_GET(TOY_SEC, rtc_data[0]);
184*1b733a9eSBinbin Zhou 	tm->tm_min = FIELD_GET(TOY_MIN, rtc_data[0]);
185*1b733a9eSBinbin Zhou 	tm->tm_hour = FIELD_GET(TOY_HOUR, rtc_data[0]);
186*1b733a9eSBinbin Zhou 	tm->tm_mday = FIELD_GET(TOY_DAY, rtc_data[0]);
187*1b733a9eSBinbin Zhou 	tm->tm_mon = FIELD_GET(TOY_MON, rtc_data[0]) - 1;
188*1b733a9eSBinbin Zhou 	tm->tm_year = rtc_data[1];
189*1b733a9eSBinbin Zhou 
190*1b733a9eSBinbin Zhou 	/* Prepare for RTC alarm year compensation value. */
191*1b733a9eSBinbin Zhou 	priv->fix_year = tm->tm_year / 64 * 64;
192*1b733a9eSBinbin Zhou 	return 0;
193*1b733a9eSBinbin Zhou }
194*1b733a9eSBinbin Zhou 
loongson_rtc_set_time(struct device * dev,struct rtc_time * tm)195*1b733a9eSBinbin Zhou static int loongson_rtc_set_time(struct device *dev, struct rtc_time *tm)
196*1b733a9eSBinbin Zhou {
197*1b733a9eSBinbin Zhou 	int ret;
198*1b733a9eSBinbin Zhou 	u32 rtc_data[2];
199*1b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
200*1b733a9eSBinbin Zhou 
201*1b733a9eSBinbin Zhou 	rtc_data[0] = FIELD_PREP(TOY_SEC, tm->tm_sec)
202*1b733a9eSBinbin Zhou 		    | FIELD_PREP(TOY_MIN, tm->tm_min)
203*1b733a9eSBinbin Zhou 		    | FIELD_PREP(TOY_HOUR, tm->tm_hour)
204*1b733a9eSBinbin Zhou 		    | FIELD_PREP(TOY_DAY, tm->tm_mday)
205*1b733a9eSBinbin Zhou 		    | FIELD_PREP(TOY_MON, tm->tm_mon + 1);
206*1b733a9eSBinbin Zhou 	rtc_data[1] = tm->tm_year;
207*1b733a9eSBinbin Zhou 
208*1b733a9eSBinbin Zhou 	ret = regmap_bulk_write(priv->regmap, TOY_WRITE0_REG, rtc_data,
209*1b733a9eSBinbin Zhou 				ARRAY_SIZE(rtc_data));
210*1b733a9eSBinbin Zhou 	if (ret < 0)
211*1b733a9eSBinbin Zhou 		return ret;
212*1b733a9eSBinbin Zhou 
213*1b733a9eSBinbin Zhou 	return loongson_rtc_set_enabled(dev);
214*1b733a9eSBinbin Zhou }
215*1b733a9eSBinbin Zhou 
loongson_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)216*1b733a9eSBinbin Zhou static int loongson_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
217*1b733a9eSBinbin Zhou {
218*1b733a9eSBinbin Zhou 	int ret;
219*1b733a9eSBinbin Zhou 	u32 alarm_data;
220*1b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
221*1b733a9eSBinbin Zhou 
222*1b733a9eSBinbin Zhou 	ret = regmap_read(priv->regmap, TOY_MATCH0_REG, &alarm_data);
223*1b733a9eSBinbin Zhou 	if (ret < 0)
224*1b733a9eSBinbin Zhou 		return ret;
225*1b733a9eSBinbin Zhou 
226*1b733a9eSBinbin Zhou 	alrm->time.tm_sec = FIELD_GET(TOY_MATCH_SEC, alarm_data);
227*1b733a9eSBinbin Zhou 	alrm->time.tm_min = FIELD_GET(TOY_MATCH_MIN, alarm_data);
228*1b733a9eSBinbin Zhou 	alrm->time.tm_hour = FIELD_GET(TOY_MATCH_HOUR, alarm_data);
229*1b733a9eSBinbin Zhou 	alrm->time.tm_mday = FIELD_GET(TOY_MATCH_DAY, alarm_data);
230*1b733a9eSBinbin Zhou 	alrm->time.tm_mon = FIELD_GET(TOY_MATCH_MON, alarm_data) - 1;
231*1b733a9eSBinbin Zhou 	/*
232*1b733a9eSBinbin Zhou 	 * This is a hardware bug: the year field of SYS_TOYMATCH is only 6 bits,
233*1b733a9eSBinbin Zhou 	 * making it impossible to save year values larger than 64.
234*1b733a9eSBinbin Zhou 	 *
235*1b733a9eSBinbin Zhou 	 * SYS_TOYMATCH is used to match the alarm time value and determine if
236*1b733a9eSBinbin Zhou 	 * an alarm is triggered, so we must keep the lower 6 bits of the year
237*1b733a9eSBinbin Zhou 	 * value constant during the value conversion.
238*1b733a9eSBinbin Zhou 	 *
239*1b733a9eSBinbin Zhou 	 * In summary, we need to manually add 64(or a multiple of 64) to the
240*1b733a9eSBinbin Zhou 	 * year value to avoid the invalid alarm prompt at startup.
241*1b733a9eSBinbin Zhou 	 */
242*1b733a9eSBinbin Zhou 	alrm->time.tm_year = FIELD_GET(TOY_MATCH_YEAR, alarm_data) + priv->fix_year;
243*1b733a9eSBinbin Zhou 
244*1b733a9eSBinbin Zhou 	alrm->enabled = !!(readl(priv->pm_base + PM1_EN_REG) & RTC_EN);
245*1b733a9eSBinbin Zhou 	return 0;
246*1b733a9eSBinbin Zhou }
247*1b733a9eSBinbin Zhou 
loongson_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)248*1b733a9eSBinbin Zhou static int loongson_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
249*1b733a9eSBinbin Zhou {
250*1b733a9eSBinbin Zhou 	u32 val;
251*1b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
252*1b733a9eSBinbin Zhou 
253*1b733a9eSBinbin Zhou 	spin_lock(&priv->lock);
254*1b733a9eSBinbin Zhou 	val = readl(priv->pm_base + PM1_EN_REG);
255*1b733a9eSBinbin Zhou 	/* Enable RTC alarm wakeup */
256*1b733a9eSBinbin Zhou 	writel(enabled ? val | RTC_EN : val & ~RTC_EN,
257*1b733a9eSBinbin Zhou 	       priv->pm_base + PM1_EN_REG);
258*1b733a9eSBinbin Zhou 	spin_unlock(&priv->lock);
259*1b733a9eSBinbin Zhou 
260*1b733a9eSBinbin Zhou 	return 0;
261*1b733a9eSBinbin Zhou }
262*1b733a9eSBinbin Zhou 
loongson_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)263*1b733a9eSBinbin Zhou static int loongson_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
264*1b733a9eSBinbin Zhou {
265*1b733a9eSBinbin Zhou 	int ret;
266*1b733a9eSBinbin Zhou 	u32 alarm_data;
267*1b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
268*1b733a9eSBinbin Zhou 
269*1b733a9eSBinbin Zhou 	alarm_data = FIELD_PREP(TOY_MATCH_SEC, alrm->time.tm_sec)
270*1b733a9eSBinbin Zhou 		   | FIELD_PREP(TOY_MATCH_MIN, alrm->time.tm_min)
271*1b733a9eSBinbin Zhou 		   | FIELD_PREP(TOY_MATCH_HOUR, alrm->time.tm_hour)
272*1b733a9eSBinbin Zhou 		   | FIELD_PREP(TOY_MATCH_DAY, alrm->time.tm_mday)
273*1b733a9eSBinbin Zhou 		   | FIELD_PREP(TOY_MATCH_MON, alrm->time.tm_mon + 1)
274*1b733a9eSBinbin Zhou 		   | FIELD_PREP(TOY_MATCH_YEAR, alrm->time.tm_year - priv->fix_year);
275*1b733a9eSBinbin Zhou 
276*1b733a9eSBinbin Zhou 	ret = regmap_write(priv->regmap, TOY_MATCH0_REG, alarm_data);
277*1b733a9eSBinbin Zhou 	if (ret < 0)
278*1b733a9eSBinbin Zhou 		return ret;
279*1b733a9eSBinbin Zhou 
280*1b733a9eSBinbin Zhou 	return loongson_rtc_alarm_irq_enable(dev, alrm->enabled);
281*1b733a9eSBinbin Zhou }
282*1b733a9eSBinbin Zhou 
283*1b733a9eSBinbin Zhou static const struct rtc_class_ops loongson_rtc_ops = {
284*1b733a9eSBinbin Zhou 	.read_time = loongson_rtc_read_time,
285*1b733a9eSBinbin Zhou 	.set_time = loongson_rtc_set_time,
286*1b733a9eSBinbin Zhou 	.read_alarm = loongson_rtc_read_alarm,
287*1b733a9eSBinbin Zhou 	.set_alarm = loongson_rtc_set_alarm,
288*1b733a9eSBinbin Zhou 	.alarm_irq_enable = loongson_rtc_alarm_irq_enable,
289*1b733a9eSBinbin Zhou };
290*1b733a9eSBinbin Zhou 
loongson_rtc_probe(struct platform_device * pdev)291*1b733a9eSBinbin Zhou static int loongson_rtc_probe(struct platform_device *pdev)
292*1b733a9eSBinbin Zhou {
293*1b733a9eSBinbin Zhou 	int ret, alarm_irq;
294*1b733a9eSBinbin Zhou 	void __iomem *regs;
295*1b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv;
296*1b733a9eSBinbin Zhou 	struct device *dev = &pdev->dev;
297*1b733a9eSBinbin Zhou 
298*1b733a9eSBinbin Zhou 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
299*1b733a9eSBinbin Zhou 	if (!priv)
300*1b733a9eSBinbin Zhou 		return -ENOMEM;
301*1b733a9eSBinbin Zhou 
302*1b733a9eSBinbin Zhou 	regs = devm_platform_ioremap_resource(pdev, 0);
303*1b733a9eSBinbin Zhou 	if (IS_ERR(regs))
304*1b733a9eSBinbin Zhou 		return dev_err_probe(dev, PTR_ERR(regs),
305*1b733a9eSBinbin Zhou 				     "devm_platform_ioremap_resource failed\n");
306*1b733a9eSBinbin Zhou 
307*1b733a9eSBinbin Zhou 	priv->regmap = devm_regmap_init_mmio(dev, regs,
308*1b733a9eSBinbin Zhou 					     &loongson_rtc_regmap_config);
309*1b733a9eSBinbin Zhou 	if (IS_ERR(priv->regmap))
310*1b733a9eSBinbin Zhou 		return dev_err_probe(dev, PTR_ERR(priv->regmap),
311*1b733a9eSBinbin Zhou 				     "devm_regmap_init_mmio failed\n");
312*1b733a9eSBinbin Zhou 
313*1b733a9eSBinbin Zhou 	priv->config = device_get_match_data(dev);
314*1b733a9eSBinbin Zhou 	spin_lock_init(&priv->lock);
315*1b733a9eSBinbin Zhou 	platform_set_drvdata(pdev, priv);
316*1b733a9eSBinbin Zhou 
317*1b733a9eSBinbin Zhou 	priv->rtcdev = devm_rtc_allocate_device(dev);
318*1b733a9eSBinbin Zhou 	if (IS_ERR(priv->rtcdev))
319*1b733a9eSBinbin Zhou 		return dev_err_probe(dev, PTR_ERR(priv->rtcdev),
320*1b733a9eSBinbin Zhou 				     "devm_rtc_allocate_device failed\n");
321*1b733a9eSBinbin Zhou 
322*1b733a9eSBinbin Zhou 	/* Get RTC alarm irq */
323*1b733a9eSBinbin Zhou 	alarm_irq = platform_get_irq(pdev, 0);
324*1b733a9eSBinbin Zhou 	if (alarm_irq > 0) {
325*1b733a9eSBinbin Zhou 		ret = devm_request_irq(dev, alarm_irq, loongson_rtc_isr,
326*1b733a9eSBinbin Zhou 				       0, "loongson-alarm", priv);
327*1b733a9eSBinbin Zhou 		if (ret < 0)
328*1b733a9eSBinbin Zhou 			return dev_err_probe(dev, ret, "Unable to request irq %d\n",
329*1b733a9eSBinbin Zhou 					     alarm_irq);
330*1b733a9eSBinbin Zhou 
331*1b733a9eSBinbin Zhou 		priv->pm_base = regs - priv->config->pm_offset;
332*1b733a9eSBinbin Zhou 		device_init_wakeup(dev, 1);
333*1b733a9eSBinbin Zhou 
334*1b733a9eSBinbin Zhou 		if (has_acpi_companion(dev))
335*1b733a9eSBinbin Zhou 			acpi_install_fixed_event_handler(ACPI_EVENT_RTC,
336*1b733a9eSBinbin Zhou 							 loongson_rtc_handler, priv);
337*1b733a9eSBinbin Zhou 	} else {
338*1b733a9eSBinbin Zhou 		/* Loongson-1C RTC does not support alarm */
339*1b733a9eSBinbin Zhou 		clear_bit(RTC_FEATURE_ALARM, priv->rtcdev->features);
340*1b733a9eSBinbin Zhou 	}
341*1b733a9eSBinbin Zhou 
342*1b733a9eSBinbin Zhou 	/* Loongson RTC does not support UIE */
343*1b733a9eSBinbin Zhou 	clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, priv->rtcdev->features);
344*1b733a9eSBinbin Zhou 	priv->rtcdev->ops = &loongson_rtc_ops;
345*1b733a9eSBinbin Zhou 	priv->rtcdev->range_min = RTC_TIMESTAMP_BEGIN_2000;
346*1b733a9eSBinbin Zhou 	priv->rtcdev->range_max = RTC_TIMESTAMP_END_2099;
347*1b733a9eSBinbin Zhou 
348*1b733a9eSBinbin Zhou 	return devm_rtc_register_device(priv->rtcdev);
349*1b733a9eSBinbin Zhou }
350*1b733a9eSBinbin Zhou 
loongson_rtc_remove(struct platform_device * pdev)351*1b733a9eSBinbin Zhou static void loongson_rtc_remove(struct platform_device *pdev)
352*1b733a9eSBinbin Zhou {
353*1b733a9eSBinbin Zhou 	struct device *dev = &pdev->dev;
354*1b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
355*1b733a9eSBinbin Zhou 
356*1b733a9eSBinbin Zhou 	if (!test_bit(RTC_FEATURE_ALARM, priv->rtcdev->features))
357*1b733a9eSBinbin Zhou 		return;
358*1b733a9eSBinbin Zhou 
359*1b733a9eSBinbin Zhou 	if (has_acpi_companion(dev))
360*1b733a9eSBinbin Zhou 		acpi_remove_fixed_event_handler(ACPI_EVENT_RTC,
361*1b733a9eSBinbin Zhou 						loongson_rtc_handler);
362*1b733a9eSBinbin Zhou 
363*1b733a9eSBinbin Zhou 	device_init_wakeup(dev, 0);
364*1b733a9eSBinbin Zhou 	loongson_rtc_alarm_irq_enable(dev, 0);
365*1b733a9eSBinbin Zhou }
366*1b733a9eSBinbin Zhou 
367*1b733a9eSBinbin Zhou static const struct of_device_id loongson_rtc_of_match[] = {
368*1b733a9eSBinbin Zhou 	{ .compatible = "loongson,ls1b-rtc", .data = &ls1b_rtc_config },
369*1b733a9eSBinbin Zhou 	{ .compatible = "loongson,ls1c-rtc", .data = &ls1c_rtc_config },
370*1b733a9eSBinbin Zhou 	{ .compatible = "loongson,ls7a-rtc", .data = &generic_rtc_config },
371*1b733a9eSBinbin Zhou 	{ .compatible = "loongson,ls2k1000-rtc", .data = &ls2k1000_rtc_config },
372*1b733a9eSBinbin Zhou 	{ /* sentinel */ }
373*1b733a9eSBinbin Zhou };
374*1b733a9eSBinbin Zhou MODULE_DEVICE_TABLE(of, loongson_rtc_of_match);
375*1b733a9eSBinbin Zhou 
376*1b733a9eSBinbin Zhou static const struct acpi_device_id loongson_rtc_acpi_match[] = {
377*1b733a9eSBinbin Zhou 	{ "LOON0001", .driver_data = (kernel_ulong_t)&generic_rtc_config },
378*1b733a9eSBinbin Zhou 	{ }
379*1b733a9eSBinbin Zhou };
380*1b733a9eSBinbin Zhou MODULE_DEVICE_TABLE(acpi, loongson_rtc_acpi_match);
381*1b733a9eSBinbin Zhou 
382*1b733a9eSBinbin Zhou static struct platform_driver loongson_rtc_driver = {
383*1b733a9eSBinbin Zhou 	.probe		= loongson_rtc_probe,
384*1b733a9eSBinbin Zhou 	.remove_new	= loongson_rtc_remove,
385*1b733a9eSBinbin Zhou 	.driver		= {
386*1b733a9eSBinbin Zhou 		.name	= "loongson-rtc",
387*1b733a9eSBinbin Zhou 		.of_match_table = loongson_rtc_of_match,
388*1b733a9eSBinbin Zhou 		.acpi_match_table = loongson_rtc_acpi_match,
389*1b733a9eSBinbin Zhou 	},
390*1b733a9eSBinbin Zhou };
391*1b733a9eSBinbin Zhou module_platform_driver(loongson_rtc_driver);
392*1b733a9eSBinbin Zhou 
393*1b733a9eSBinbin Zhou MODULE_DESCRIPTION("Loongson RTC driver");
394*1b733a9eSBinbin Zhou MODULE_AUTHOR("Binbin Zhou <zhoubinbin@loongson.cn>");
395*1b733a9eSBinbin Zhou MODULE_AUTHOR("WANG Xuerui <git@xen0n.name>");
396*1b733a9eSBinbin Zhou MODULE_AUTHOR("Huacai Chen <chenhuacai@kernel.org>");
397*1b733a9eSBinbin Zhou MODULE_LICENSE("GPL");
398