1 /* 2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright 2010 Orex Computed Radiography 4 */ 5 6 /* 7 * The code contained herein is licensed under the GNU General Public 8 * License. You may obtain a copy of the GNU General Public License 9 * Version 2 or later at the following locations: 10 * 11 * http://www.opensource.org/licenses/gpl-license.html 12 * http://www.gnu.org/copyleft/gpl.html 13 */ 14 15 /* based on rtc-mc13892.c */ 16 17 /* 18 * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block 19 * to implement a Linux RTC. Times and alarms are truncated to seconds. 20 * Since the RTC framework performs API locking via rtc->ops_lock the 21 * only simultaneous accesses we need to deal with is updating DryIce 22 * registers while servicing an alarm. 23 * 24 * Note that reading the DSR (DryIce Status Register) automatically clears 25 * the WCF (Write Complete Flag). All DryIce writes are synchronized to the 26 * LP (Low Power) domain and set the WCF upon completion. Writes to the 27 * DIER (DryIce Interrupt Enable Register) are the only exception. These 28 * occur at normal bus speeds and do not set WCF. Periodic interrupts are 29 * not supported by the hardware. 30 */ 31 32 #include <linux/io.h> 33 #include <linux/clk.h> 34 #include <linux/delay.h> 35 #include <linux/module.h> 36 #include <linux/platform_device.h> 37 #include <linux/rtc.h> 38 #include <linux/sched.h> 39 #include <linux/workqueue.h> 40 #include <linux/of.h> 41 42 /* DryIce Register Definitions */ 43 44 #define DTCMR 0x00 /* Time Counter MSB Reg */ 45 #define DTCLR 0x04 /* Time Counter LSB Reg */ 46 47 #define DCAMR 0x08 /* Clock Alarm MSB Reg */ 48 #define DCALR 0x0c /* Clock Alarm LSB Reg */ 49 #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */ 50 51 #define DCR 0x10 /* Control Reg */ 52 #define DCR_TCE (1 << 3) /* Time Counter Enable */ 53 54 #define DSR 0x14 /* Status Reg */ 55 #define DSR_WBF (1 << 10) /* Write Busy Flag */ 56 #define DSR_WNF (1 << 9) /* Write Next Flag */ 57 #define DSR_WCF (1 << 8) /* Write Complete Flag */ 58 #define DSR_WEF (1 << 7) /* Write Error Flag */ 59 #define DSR_CAF (1 << 4) /* Clock Alarm Flag */ 60 #define DSR_NVF (1 << 1) /* Non-Valid Flag */ 61 #define DSR_SVF (1 << 0) /* Security Violation Flag */ 62 63 #define DIER 0x18 /* Interrupt Enable Reg */ 64 #define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ 65 #define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ 66 #define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ 67 #define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ 68 69 /** 70 * struct imxdi_dev - private imxdi rtc data 71 * @pdev: pionter to platform dev 72 * @rtc: pointer to rtc struct 73 * @ioaddr: IO registers pointer 74 * @irq: dryice normal interrupt 75 * @clk: input reference clock 76 * @dsr: copy of the DSR register 77 * @irq_lock: interrupt enable register (DIER) lock 78 * @write_wait: registers write complete queue 79 * @write_mutex: serialize registers write 80 * @work: schedule alarm work 81 */ 82 struct imxdi_dev { 83 struct platform_device *pdev; 84 struct rtc_device *rtc; 85 void __iomem *ioaddr; 86 int irq; 87 struct clk *clk; 88 u32 dsr; 89 spinlock_t irq_lock; 90 wait_queue_head_t write_wait; 91 struct mutex write_mutex; 92 struct work_struct work; 93 }; 94 95 /* 96 * enable a dryice interrupt 97 */ 98 static void di_int_enable(struct imxdi_dev *imxdi, u32 intr) 99 { 100 unsigned long flags; 101 102 spin_lock_irqsave(&imxdi->irq_lock, flags); 103 __raw_writel(__raw_readl(imxdi->ioaddr + DIER) | intr, 104 imxdi->ioaddr + DIER); 105 spin_unlock_irqrestore(&imxdi->irq_lock, flags); 106 } 107 108 /* 109 * disable a dryice interrupt 110 */ 111 static void di_int_disable(struct imxdi_dev *imxdi, u32 intr) 112 { 113 unsigned long flags; 114 115 spin_lock_irqsave(&imxdi->irq_lock, flags); 116 __raw_writel(__raw_readl(imxdi->ioaddr + DIER) & ~intr, 117 imxdi->ioaddr + DIER); 118 spin_unlock_irqrestore(&imxdi->irq_lock, flags); 119 } 120 121 /* 122 * This function attempts to clear the dryice write-error flag. 123 * 124 * A dryice write error is similar to a bus fault and should not occur in 125 * normal operation. Clearing the flag requires another write, so the root 126 * cause of the problem may need to be fixed before the flag can be cleared. 127 */ 128 static void clear_write_error(struct imxdi_dev *imxdi) 129 { 130 int cnt; 131 132 dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n"); 133 134 /* clear the write error flag */ 135 __raw_writel(DSR_WEF, imxdi->ioaddr + DSR); 136 137 /* wait for it to take effect */ 138 for (cnt = 0; cnt < 1000; cnt++) { 139 if ((__raw_readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0) 140 return; 141 udelay(10); 142 } 143 dev_err(&imxdi->pdev->dev, 144 "ERROR: Cannot clear write-error flag!\n"); 145 } 146 147 /* 148 * Write a dryice register and wait until it completes. 149 * 150 * This function uses interrupts to determine when the 151 * write has completed. 152 */ 153 static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg) 154 { 155 int ret; 156 int rc = 0; 157 158 /* serialize register writes */ 159 mutex_lock(&imxdi->write_mutex); 160 161 /* enable the write-complete interrupt */ 162 di_int_enable(imxdi, DIER_WCIE); 163 164 imxdi->dsr = 0; 165 166 /* do the register write */ 167 __raw_writel(val, imxdi->ioaddr + reg); 168 169 /* wait for the write to finish */ 170 ret = wait_event_interruptible_timeout(imxdi->write_wait, 171 imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1)); 172 if (ret < 0) { 173 rc = ret; 174 goto out; 175 } else if (ret == 0) { 176 dev_warn(&imxdi->pdev->dev, 177 "Write-wait timeout " 178 "val = 0x%08x reg = 0x%08x\n", val, reg); 179 } 180 181 /* check for write error */ 182 if (imxdi->dsr & DSR_WEF) { 183 clear_write_error(imxdi); 184 rc = -EIO; 185 } 186 187 out: 188 mutex_unlock(&imxdi->write_mutex); 189 190 return rc; 191 } 192 193 /* 194 * read the seconds portion of the current time from the dryice time counter 195 */ 196 static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm) 197 { 198 struct imxdi_dev *imxdi = dev_get_drvdata(dev); 199 unsigned long now; 200 201 now = __raw_readl(imxdi->ioaddr + DTCMR); 202 rtc_time_to_tm(now, tm); 203 204 return 0; 205 } 206 207 /* 208 * set the seconds portion of dryice time counter and clear the 209 * fractional part. 210 */ 211 static int dryice_rtc_set_mmss(struct device *dev, unsigned long secs) 212 { 213 struct imxdi_dev *imxdi = dev_get_drvdata(dev); 214 int rc; 215 216 /* zero the fractional part first */ 217 rc = di_write_wait(imxdi, 0, DTCLR); 218 if (rc == 0) 219 rc = di_write_wait(imxdi, secs, DTCMR); 220 221 return rc; 222 } 223 224 static int dryice_rtc_alarm_irq_enable(struct device *dev, 225 unsigned int enabled) 226 { 227 struct imxdi_dev *imxdi = dev_get_drvdata(dev); 228 229 if (enabled) 230 di_int_enable(imxdi, DIER_CAIE); 231 else 232 di_int_disable(imxdi, DIER_CAIE); 233 234 return 0; 235 } 236 237 /* 238 * read the seconds portion of the alarm register. 239 * the fractional part of the alarm register is always zero. 240 */ 241 static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) 242 { 243 struct imxdi_dev *imxdi = dev_get_drvdata(dev); 244 u32 dcamr; 245 246 dcamr = __raw_readl(imxdi->ioaddr + DCAMR); 247 rtc_time_to_tm(dcamr, &alarm->time); 248 249 /* alarm is enabled if the interrupt is enabled */ 250 alarm->enabled = (__raw_readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0; 251 252 /* don't allow the DSR read to mess up DSR_WCF */ 253 mutex_lock(&imxdi->write_mutex); 254 255 /* alarm is pending if the alarm flag is set */ 256 alarm->pending = (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0; 257 258 mutex_unlock(&imxdi->write_mutex); 259 260 return 0; 261 } 262 263 /* 264 * set the seconds portion of dryice alarm register 265 */ 266 static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) 267 { 268 struct imxdi_dev *imxdi = dev_get_drvdata(dev); 269 unsigned long now; 270 unsigned long alarm_time; 271 int rc; 272 273 rc = rtc_tm_to_time(&alarm->time, &alarm_time); 274 if (rc) 275 return rc; 276 277 /* don't allow setting alarm in the past */ 278 now = __raw_readl(imxdi->ioaddr + DTCMR); 279 if (alarm_time < now) 280 return -EINVAL; 281 282 /* write the new alarm time */ 283 rc = di_write_wait(imxdi, (u32)alarm_time, DCAMR); 284 if (rc) 285 return rc; 286 287 if (alarm->enabled) 288 di_int_enable(imxdi, DIER_CAIE); /* enable alarm intr */ 289 else 290 di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */ 291 292 return 0; 293 } 294 295 static struct rtc_class_ops dryice_rtc_ops = { 296 .read_time = dryice_rtc_read_time, 297 .set_mmss = dryice_rtc_set_mmss, 298 .alarm_irq_enable = dryice_rtc_alarm_irq_enable, 299 .read_alarm = dryice_rtc_read_alarm, 300 .set_alarm = dryice_rtc_set_alarm, 301 }; 302 303 /* 304 * dryice "normal" interrupt handler 305 */ 306 static irqreturn_t dryice_norm_irq(int irq, void *dev_id) 307 { 308 struct imxdi_dev *imxdi = dev_id; 309 u32 dsr, dier; 310 irqreturn_t rc = IRQ_NONE; 311 312 dier = __raw_readl(imxdi->ioaddr + DIER); 313 314 /* handle write complete and write error cases */ 315 if ((dier & DIER_WCIE)) { 316 /*If the write wait queue is empty then there is no pending 317 operations. It means the interrupt is for DryIce -Security. 318 IRQ must be returned as none.*/ 319 if (list_empty_careful(&imxdi->write_wait.task_list)) 320 return rc; 321 322 /* DSR_WCF clears itself on DSR read */ 323 dsr = __raw_readl(imxdi->ioaddr + DSR); 324 if ((dsr & (DSR_WCF | DSR_WEF))) { 325 /* mask the interrupt */ 326 di_int_disable(imxdi, DIER_WCIE); 327 328 /* save the dsr value for the wait queue */ 329 imxdi->dsr |= dsr; 330 331 wake_up_interruptible(&imxdi->write_wait); 332 rc = IRQ_HANDLED; 333 } 334 } 335 336 /* handle the alarm case */ 337 if ((dier & DIER_CAIE)) { 338 /* DSR_WCF clears itself on DSR read */ 339 dsr = __raw_readl(imxdi->ioaddr + DSR); 340 if (dsr & DSR_CAF) { 341 /* mask the interrupt */ 342 di_int_disable(imxdi, DIER_CAIE); 343 344 /* finish alarm in user context */ 345 schedule_work(&imxdi->work); 346 rc = IRQ_HANDLED; 347 } 348 } 349 return rc; 350 } 351 352 /* 353 * post the alarm event from user context so it can sleep 354 * on the write completion. 355 */ 356 static void dryice_work(struct work_struct *work) 357 { 358 struct imxdi_dev *imxdi = container_of(work, 359 struct imxdi_dev, work); 360 361 /* dismiss the interrupt (ignore error) */ 362 di_write_wait(imxdi, DSR_CAF, DSR); 363 364 /* pass the alarm event to the rtc framework. */ 365 rtc_update_irq(imxdi->rtc, 1, RTC_AF | RTC_IRQF); 366 } 367 368 /* 369 * probe for dryice rtc device 370 */ 371 static int dryice_rtc_probe(struct platform_device *pdev) 372 { 373 struct resource *res; 374 struct imxdi_dev *imxdi; 375 int rc; 376 377 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 378 if (!res) 379 return -ENODEV; 380 381 imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL); 382 if (!imxdi) 383 return -ENOMEM; 384 385 imxdi->pdev = pdev; 386 387 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res), 388 pdev->name)) 389 return -EBUSY; 390 391 imxdi->ioaddr = devm_ioremap(&pdev->dev, res->start, 392 resource_size(res)); 393 if (imxdi->ioaddr == NULL) 394 return -ENOMEM; 395 396 spin_lock_init(&imxdi->irq_lock); 397 398 imxdi->irq = platform_get_irq(pdev, 0); 399 if (imxdi->irq < 0) 400 return imxdi->irq; 401 402 init_waitqueue_head(&imxdi->write_wait); 403 404 INIT_WORK(&imxdi->work, dryice_work); 405 406 mutex_init(&imxdi->write_mutex); 407 408 imxdi->clk = clk_get(&pdev->dev, NULL); 409 if (IS_ERR(imxdi->clk)) 410 return PTR_ERR(imxdi->clk); 411 clk_prepare_enable(imxdi->clk); 412 413 /* 414 * Initialize dryice hardware 415 */ 416 417 /* mask all interrupts */ 418 __raw_writel(0, imxdi->ioaddr + DIER); 419 420 rc = devm_request_irq(&pdev->dev, imxdi->irq, dryice_norm_irq, 421 IRQF_SHARED, pdev->name, imxdi); 422 if (rc) { 423 dev_warn(&pdev->dev, "interrupt not available.\n"); 424 goto err; 425 } 426 427 /* put dryice into valid state */ 428 if (__raw_readl(imxdi->ioaddr + DSR) & DSR_NVF) { 429 rc = di_write_wait(imxdi, DSR_NVF | DSR_SVF, DSR); 430 if (rc) 431 goto err; 432 } 433 434 /* initialize alarm */ 435 rc = di_write_wait(imxdi, DCAMR_UNSET, DCAMR); 436 if (rc) 437 goto err; 438 rc = di_write_wait(imxdi, 0, DCALR); 439 if (rc) 440 goto err; 441 442 /* clear alarm flag */ 443 if (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) { 444 rc = di_write_wait(imxdi, DSR_CAF, DSR); 445 if (rc) 446 goto err; 447 } 448 449 /* the timer won't count if it has never been written to */ 450 if (__raw_readl(imxdi->ioaddr + DTCMR) == 0) { 451 rc = di_write_wait(imxdi, 0, DTCMR); 452 if (rc) 453 goto err; 454 } 455 456 /* start keeping time */ 457 if (!(__raw_readl(imxdi->ioaddr + DCR) & DCR_TCE)) { 458 rc = di_write_wait(imxdi, 459 __raw_readl(imxdi->ioaddr + DCR) | DCR_TCE, 460 DCR); 461 if (rc) 462 goto err; 463 } 464 465 platform_set_drvdata(pdev, imxdi); 466 imxdi->rtc = rtc_device_register(pdev->name, &pdev->dev, 467 &dryice_rtc_ops, THIS_MODULE); 468 if (IS_ERR(imxdi->rtc)) { 469 rc = PTR_ERR(imxdi->rtc); 470 goto err; 471 } 472 473 return 0; 474 475 err: 476 clk_disable_unprepare(imxdi->clk); 477 clk_put(imxdi->clk); 478 479 return rc; 480 } 481 482 static int __devexit dryice_rtc_remove(struct platform_device *pdev) 483 { 484 struct imxdi_dev *imxdi = platform_get_drvdata(pdev); 485 486 flush_work(&imxdi->work); 487 488 /* mask all interrupts */ 489 __raw_writel(0, imxdi->ioaddr + DIER); 490 491 rtc_device_unregister(imxdi->rtc); 492 493 clk_disable_unprepare(imxdi->clk); 494 clk_put(imxdi->clk); 495 496 return 0; 497 } 498 499 #ifdef CONFIG_OF 500 static const struct of_device_id dryice_dt_ids[] = { 501 { .compatible = "fsl,imx25-rtc" }, 502 { /* sentinel */ } 503 }; 504 505 MODULE_DEVICE_TABLE(of, dryice_dt_ids); 506 #endif 507 508 static struct platform_driver dryice_rtc_driver = { 509 .driver = { 510 .name = "imxdi_rtc", 511 .owner = THIS_MODULE, 512 .of_match_table = of_match_ptr(dryice_dt_ids), 513 }, 514 .remove = __devexit_p(dryice_rtc_remove), 515 }; 516 517 static int __init dryice_rtc_init(void) 518 { 519 return platform_driver_probe(&dryice_rtc_driver, dryice_rtc_probe); 520 } 521 522 static void __exit dryice_rtc_exit(void) 523 { 524 platform_driver_unregister(&dryice_rtc_driver); 525 } 526 527 module_init(dryice_rtc_init); 528 module_exit(dryice_rtc_exit); 529 530 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 531 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); 532 MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)"); 533 MODULE_LICENSE("GPL"); 534