1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. 4 * 5 * Copyright (C) 2005 James Chapman (ds1337 core) 6 * Copyright (C) 2006 David Brownell 7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support) 8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes) 9 */ 10 11 #include <linux/bcd.h> 12 #include <linux/i2c.h> 13 #include <linux/init.h> 14 #include <linux/kstrtox.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/property.h> 18 #include <linux/rtc/ds1307.h> 19 #include <linux/rtc.h> 20 #include <linux/slab.h> 21 #include <linux/string.h> 22 #include <linux/hwmon.h> 23 #include <linux/hwmon-sysfs.h> 24 #include <linux/clk-provider.h> 25 #include <linux/regmap.h> 26 #include <linux/watchdog.h> 27 28 /* 29 * We can't determine type by probing, but if we expect pre-Linux code 30 * to have set the chip up as a clock (turning on the oscillator and 31 * setting the date and time), Linux can ignore the non-clock features. 32 * That's a natural job for a factory or repair bench. 33 */ 34 enum ds_type { 35 unknown_ds_type, /* always first and 0 */ 36 ds_1307, 37 ds_1308, 38 ds_1337, 39 ds_1338, 40 ds_1339, 41 ds_1340, 42 ds_1341, 43 ds_1388, 44 ds_3231, 45 m41t0, 46 m41t00, 47 m41t11, 48 mcp794xx, 49 rx_8025, 50 rx_8130, 51 last_ds_type /* always last */ 52 /* rs5c372 too? different address... */ 53 }; 54 55 /* RTC registers don't differ much, except for the century flag */ 56 #define DS1307_REG_SECS 0x00 /* 00-59 */ 57 # define DS1307_BIT_CH 0x80 58 # define DS1340_BIT_nEOSC 0x80 59 # define MCP794XX_BIT_ST 0x80 60 #define DS1307_REG_MIN 0x01 /* 00-59 */ 61 # define M41T0_BIT_OF 0x80 62 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ 63 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ 64 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ 65 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ 66 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ 67 #define DS1307_REG_WDAY 0x03 /* 01-07 */ 68 # define MCP794XX_BIT_OSCRUN BIT(5) 69 # define MCP794XX_BIT_VBATEN 0x08 70 #define DS1307_REG_MDAY 0x04 /* 01-31 */ 71 #define DS1307_REG_MONTH 0x05 /* 01-12 */ 72 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ 73 #define DS1307_REG_YEAR 0x06 /* 00-99 */ 74 75 /* 76 * Other registers (control, status, alarms, trickle charge, NVRAM, etc) 77 * start at 7, and they differ a LOT. Only control and status matter for 78 * basic RTC date and time functionality; be careful using them. 79 */ 80 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */ 81 # define DS1307_BIT_OUT 0x80 82 # define DS1338_BIT_OSF 0x20 83 # define DS1307_BIT_SQWE 0x10 84 # define DS1307_BIT_RS1 0x02 85 # define DS1307_BIT_RS0 0x01 86 #define DS1337_REG_CONTROL 0x0e 87 # define DS1337_BIT_nEOSC 0x80 88 # define DS1339_BIT_BBSQI 0x20 89 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ 90 # define DS1337_BIT_RS2 0x10 91 # define DS1337_BIT_RS1 0x08 92 # define DS1337_BIT_INTCN 0x04 93 # define DS1337_BIT_A2IE 0x02 94 # define DS1337_BIT_A1IE 0x01 95 #define DS1340_REG_CONTROL 0x07 96 # define DS1340_BIT_OUT 0x80 97 # define DS1340_BIT_FT 0x40 98 # define DS1340_BIT_CALIB_SIGN 0x20 99 # define DS1340_M_CALIBRATION 0x1f 100 #define DS1340_REG_FLAG 0x09 101 # define DS1340_BIT_OSF 0x80 102 #define DS1337_REG_STATUS 0x0f 103 # define DS1337_BIT_OSF 0x80 104 # define DS3231_BIT_EN32KHZ 0x08 105 # define DS1337_BIT_A2I 0x02 106 # define DS1337_BIT_A1I 0x01 107 #define DS1339_REG_ALARM1_SECS 0x07 108 109 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0 110 111 #define RX8025_REG_CTRL1 0x0e 112 # define RX8025_BIT_2412 0x20 113 #define RX8025_REG_CTRL2 0x0f 114 # define RX8025_BIT_PON 0x10 115 # define RX8025_BIT_VDET 0x40 116 # define RX8025_BIT_XST 0x20 117 118 #define RX8130_REG_ALARM_MIN 0x17 119 #define RX8130_REG_ALARM_HOUR 0x18 120 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19 121 #define RX8130_REG_EXTENSION 0x1c 122 #define RX8130_REG_EXTENSION_WADA BIT(3) 123 #define RX8130_REG_FLAG 0x1d 124 #define RX8130_REG_FLAG_VLF BIT(1) 125 #define RX8130_REG_FLAG_AF BIT(3) 126 #define RX8130_REG_CONTROL0 0x1e 127 #define RX8130_REG_CONTROL0_AIE BIT(3) 128 #define RX8130_REG_CONTROL1 0x1f 129 #define RX8130_REG_CONTROL1_INIEN BIT(4) 130 #define RX8130_REG_CONTROL1_CHGEN BIT(5) 131 132 #define MCP794XX_REG_CONTROL 0x07 133 # define MCP794XX_BIT_ALM0_EN 0x10 134 # define MCP794XX_BIT_ALM1_EN 0x20 135 #define MCP794XX_REG_ALARM0_BASE 0x0a 136 #define MCP794XX_REG_ALARM0_CTRL 0x0d 137 #define MCP794XX_REG_ALARM1_BASE 0x11 138 #define MCP794XX_REG_ALARM1_CTRL 0x14 139 # define MCP794XX_BIT_ALMX_IF BIT(3) 140 # define MCP794XX_BIT_ALMX_C0 BIT(4) 141 # define MCP794XX_BIT_ALMX_C1 BIT(5) 142 # define MCP794XX_BIT_ALMX_C2 BIT(6) 143 # define MCP794XX_BIT_ALMX_POL BIT(7) 144 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \ 145 MCP794XX_BIT_ALMX_C1 | \ 146 MCP794XX_BIT_ALMX_C2) 147 148 #define M41TXX_REG_CONTROL 0x07 149 # define M41TXX_BIT_OUT BIT(7) 150 # define M41TXX_BIT_FT BIT(6) 151 # define M41TXX_BIT_CALIB_SIGN BIT(5) 152 # define M41TXX_M_CALIBRATION GENMASK(4, 0) 153 154 #define DS1388_REG_WDOG_HUN_SECS 0x08 155 #define DS1388_REG_WDOG_SECS 0x09 156 #define DS1388_REG_FLAG 0x0b 157 # define DS1388_BIT_WF BIT(6) 158 # define DS1388_BIT_OSF BIT(7) 159 #define DS1388_REG_CONTROL 0x0c 160 # define DS1388_BIT_RST BIT(0) 161 # define DS1388_BIT_WDE BIT(1) 162 # define DS1388_BIT_nEOSC BIT(7) 163 164 /* negative offset step is -2.034ppm */ 165 #define M41TXX_NEG_OFFSET_STEP_PPB 2034 166 /* positive offset step is +4.068ppm */ 167 #define M41TXX_POS_OFFSET_STEP_PPB 4068 168 /* Min and max values supported with 'offset' interface by M41TXX */ 169 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB) 170 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB) 171 172 struct ds1307 { 173 enum ds_type type; 174 struct device *dev; 175 struct regmap *regmap; 176 const char *name; 177 struct rtc_device *rtc; 178 #ifdef CONFIG_COMMON_CLK 179 struct clk_hw clks[2]; 180 #endif 181 }; 182 183 struct chip_desc { 184 unsigned alarm:1; 185 u16 nvram_offset; 186 u16 nvram_size; 187 u8 offset; /* register's offset */ 188 u8 century_reg; 189 u8 century_enable_bit; 190 u8 century_bit; 191 u8 bbsqi_bit; 192 irq_handler_t irq_handler; 193 const struct rtc_class_ops *rtc_ops; 194 u16 trickle_charger_reg; 195 u8 (*do_trickle_setup)(struct ds1307 *, u32, 196 bool); 197 /* Does the RTC require trickle-resistor-ohms to select the value of 198 * the resistor between Vcc and Vbackup? 199 */ 200 bool requires_trickle_resistor; 201 /* Some RTC's batteries and supercaps were charged by default, others 202 * allow charging but were not configured previously to do so. 203 * Remember this behavior to stay backwards compatible. 204 */ 205 bool charge_default; 206 }; 207 208 static const struct chip_desc chips[last_ds_type]; 209 210 static int ds1307_get_time(struct device *dev, struct rtc_time *t) 211 { 212 struct ds1307 *ds1307 = dev_get_drvdata(dev); 213 int tmp, ret; 214 const struct chip_desc *chip = &chips[ds1307->type]; 215 u8 regs[7]; 216 217 if (ds1307->type == rx_8130) { 218 unsigned int regflag; 219 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag); 220 if (ret) { 221 dev_err(dev, "%s error %d\n", "read", ret); 222 return ret; 223 } 224 225 if (regflag & RX8130_REG_FLAG_VLF) { 226 dev_warn_once(dev, "oscillator failed, set time!\n"); 227 return -EINVAL; 228 } 229 } 230 231 /* read the RTC date and time registers all at once */ 232 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 233 sizeof(regs)); 234 if (ret) { 235 dev_err(dev, "%s error %d\n", "read", ret); 236 return ret; 237 } 238 239 dev_dbg(dev, "%s: %7ph\n", "read", regs); 240 241 /* if oscillator fail bit is set, no data can be trusted */ 242 if (ds1307->type == m41t0 && 243 regs[DS1307_REG_MIN] & M41T0_BIT_OF) { 244 dev_warn_once(dev, "oscillator failed, set time!\n"); 245 return -EINVAL; 246 } else if (ds1307->type == mcp794xx && 247 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_OSCRUN)) { 248 dev_warn_once(dev, "oscillator failed, set time!\n"); 249 return -EINVAL; 250 } 251 252 tmp = regs[DS1307_REG_SECS]; 253 switch (ds1307->type) { 254 case ds_1307: 255 case m41t0: 256 case m41t00: 257 case m41t11: 258 if (tmp & DS1307_BIT_CH) 259 return -EINVAL; 260 break; 261 case ds_1308: 262 case ds_1338: 263 if (tmp & DS1307_BIT_CH) 264 return -EINVAL; 265 266 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp); 267 if (ret) 268 return ret; 269 if (tmp & DS1338_BIT_OSF) 270 return -EINVAL; 271 break; 272 case ds_1340: 273 if (tmp & DS1340_BIT_nEOSC) 274 return -EINVAL; 275 276 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp); 277 if (ret) 278 return ret; 279 if (tmp & DS1340_BIT_OSF) 280 return -EINVAL; 281 break; 282 case ds_1388: 283 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp); 284 if (ret) 285 return ret; 286 if (tmp & DS1388_BIT_OSF) 287 return -EINVAL; 288 break; 289 case mcp794xx: 290 if (!(tmp & MCP794XX_BIT_ST)) 291 return -EINVAL; 292 293 break; 294 default: 295 break; 296 } 297 298 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f); 299 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f); 300 tmp = regs[DS1307_REG_HOUR] & 0x3f; 301 t->tm_hour = bcd2bin(tmp); 302 /* rx8130 is bit position, not BCD */ 303 if (ds1307->type == rx_8130) 304 t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f); 305 else 306 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1; 307 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f); 308 tmp = regs[DS1307_REG_MONTH] & 0x1f; 309 t->tm_mon = bcd2bin(tmp) - 1; 310 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100; 311 312 if (regs[chip->century_reg] & chip->century_bit && 313 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY)) 314 t->tm_year += 100; 315 316 dev_dbg(dev, "%s secs=%d, mins=%d, " 317 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 318 "read", t->tm_sec, t->tm_min, 319 t->tm_hour, t->tm_mday, 320 t->tm_mon, t->tm_year, t->tm_wday); 321 322 return 0; 323 } 324 325 static int ds1307_set_time(struct device *dev, struct rtc_time *t) 326 { 327 struct ds1307 *ds1307 = dev_get_drvdata(dev); 328 const struct chip_desc *chip = &chips[ds1307->type]; 329 int result; 330 int tmp; 331 u8 regs[7]; 332 333 dev_dbg(dev, "%s secs=%d, mins=%d, " 334 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 335 "write", t->tm_sec, t->tm_min, 336 t->tm_hour, t->tm_mday, 337 t->tm_mon, t->tm_year, t->tm_wday); 338 339 if (t->tm_year < 100) 340 return -EINVAL; 341 342 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY 343 if (t->tm_year > (chip->century_bit ? 299 : 199)) 344 return -EINVAL; 345 #else 346 if (t->tm_year > 199) 347 return -EINVAL; 348 #endif 349 350 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec); 351 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min); 352 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); 353 /* rx8130 is bit position, not BCD */ 354 if (ds1307->type == rx_8130) 355 regs[DS1307_REG_WDAY] = 1 << t->tm_wday; 356 else 357 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); 358 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); 359 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); 360 361 /* assume 20YY not 19YY */ 362 tmp = t->tm_year % 100; 363 regs[DS1307_REG_YEAR] = bin2bcd(tmp); 364 365 if (chip->century_enable_bit) 366 regs[chip->century_reg] |= chip->century_enable_bit; 367 if (t->tm_year > 199 && chip->century_bit) 368 regs[chip->century_reg] |= chip->century_bit; 369 370 switch (ds1307->type) { 371 case ds_1308: 372 case ds_1338: 373 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL, 374 DS1338_BIT_OSF, 0); 375 break; 376 case ds_1340: 377 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG, 378 DS1340_BIT_OSF, 0); 379 break; 380 case ds_1388: 381 regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG, 382 DS1388_BIT_OSF, 0); 383 break; 384 case mcp794xx: 385 /* 386 * these bits were cleared when preparing the date/time 387 * values and need to be set again before writing the 388 * regsfer out to the device. 389 */ 390 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST; 391 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN; 392 break; 393 default: 394 break; 395 } 396 397 dev_dbg(dev, "%s: %7ph\n", "write", regs); 398 399 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs, 400 sizeof(regs)); 401 if (result) { 402 dev_err(dev, "%s error %d\n", "write", result); 403 return result; 404 } 405 406 if (ds1307->type == rx_8130) { 407 /* clear Voltage Loss Flag as data is available now */ 408 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG, 409 ~(u8)RX8130_REG_FLAG_VLF); 410 if (result) { 411 dev_err(dev, "%s error %d\n", "write", result); 412 return result; 413 } 414 } 415 416 return 0; 417 } 418 419 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) 420 { 421 struct ds1307 *ds1307 = dev_get_drvdata(dev); 422 int ret; 423 u8 regs[9]; 424 425 /* read all ALARM1, ALARM2, and status registers at once */ 426 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, 427 regs, sizeof(regs)); 428 if (ret) { 429 dev_err(dev, "%s error %d\n", "alarm read", ret); 430 return ret; 431 } 432 433 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read", 434 ®s[0], ®s[4], ®s[7]); 435 436 /* 437 * report alarm time (ALARM1); assume 24 hour and day-of-month modes, 438 * and that all four fields are checked matches 439 */ 440 t->time.tm_sec = bcd2bin(regs[0] & 0x7f); 441 t->time.tm_min = bcd2bin(regs[1] & 0x7f); 442 t->time.tm_hour = bcd2bin(regs[2] & 0x3f); 443 t->time.tm_mday = bcd2bin(regs[3] & 0x3f); 444 445 /* ... and status */ 446 t->enabled = !!(regs[7] & DS1337_BIT_A1IE); 447 t->pending = !!(regs[8] & DS1337_BIT_A1I); 448 449 dev_dbg(dev, "%s secs=%d, mins=%d, " 450 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 451 "alarm read", t->time.tm_sec, t->time.tm_min, 452 t->time.tm_hour, t->time.tm_mday, 453 t->enabled, t->pending); 454 455 return 0; 456 } 457 458 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) 459 { 460 struct ds1307 *ds1307 = dev_get_drvdata(dev); 461 unsigned char regs[9]; 462 u8 control, status; 463 int ret; 464 465 dev_dbg(dev, "%s secs=%d, mins=%d, " 466 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 467 "alarm set", t->time.tm_sec, t->time.tm_min, 468 t->time.tm_hour, t->time.tm_mday, 469 t->enabled, t->pending); 470 471 /* read current status of both alarms and the chip */ 472 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 473 sizeof(regs)); 474 if (ret) { 475 dev_err(dev, "%s error %d\n", "alarm write", ret); 476 return ret; 477 } 478 control = regs[7]; 479 status = regs[8]; 480 481 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)", 482 ®s[0], ®s[4], control, status); 483 484 /* set ALARM1, using 24 hour and day-of-month modes */ 485 regs[0] = bin2bcd(t->time.tm_sec); 486 regs[1] = bin2bcd(t->time.tm_min); 487 regs[2] = bin2bcd(t->time.tm_hour); 488 regs[3] = bin2bcd(t->time.tm_mday); 489 490 /* set ALARM2 to non-garbage */ 491 regs[4] = 0; 492 regs[5] = 0; 493 regs[6] = 0; 494 495 /* disable alarms */ 496 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); 497 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); 498 499 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 500 sizeof(regs)); 501 if (ret) { 502 dev_err(dev, "can't set alarm time\n"); 503 return ret; 504 } 505 506 /* optionally enable ALARM1 */ 507 if (t->enabled) { 508 dev_dbg(dev, "alarm IRQ armed\n"); 509 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ 510 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]); 511 } 512 513 return 0; 514 } 515 516 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) 517 { 518 struct ds1307 *ds1307 = dev_get_drvdata(dev); 519 520 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 521 DS1337_BIT_A1IE, 522 enabled ? DS1337_BIT_A1IE : 0); 523 } 524 525 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode) 526 { 527 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE : 528 DS1307_TRICKLE_CHARGER_NO_DIODE; 529 530 setup |= DS13XX_TRICKLE_CHARGER_MAGIC; 531 532 switch (ohms) { 533 case 250: 534 setup |= DS1307_TRICKLE_CHARGER_250_OHM; 535 break; 536 case 2000: 537 setup |= DS1307_TRICKLE_CHARGER_2K_OHM; 538 break; 539 case 4000: 540 setup |= DS1307_TRICKLE_CHARGER_4K_OHM; 541 break; 542 default: 543 dev_warn(ds1307->dev, 544 "Unsupported ohm value %u in dt\n", ohms); 545 return 0; 546 } 547 return setup; 548 } 549 550 static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode) 551 { 552 /* make sure that the backup battery is enabled */ 553 u8 setup = RX8130_REG_CONTROL1_INIEN; 554 if (diode) 555 setup |= RX8130_REG_CONTROL1_CHGEN; 556 557 return setup; 558 } 559 560 static irqreturn_t rx8130_irq(int irq, void *dev_id) 561 { 562 struct ds1307 *ds1307 = dev_id; 563 u8 ctl[3]; 564 int ret; 565 566 rtc_lock(ds1307->rtc); 567 568 /* Read control registers. */ 569 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 570 sizeof(ctl)); 571 if (ret < 0) 572 goto out; 573 if (!(ctl[1] & RX8130_REG_FLAG_AF)) 574 goto out; 575 ctl[1] &= ~RX8130_REG_FLAG_AF; 576 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 577 578 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 579 sizeof(ctl)); 580 if (ret < 0) 581 goto out; 582 583 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 584 585 out: 586 rtc_unlock(ds1307->rtc); 587 588 return IRQ_HANDLED; 589 } 590 591 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t) 592 { 593 struct ds1307 *ds1307 = dev_get_drvdata(dev); 594 u8 ald[3], ctl[3]; 595 int ret; 596 597 /* Read alarm registers. */ 598 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 599 sizeof(ald)); 600 if (ret < 0) 601 return ret; 602 603 /* Read control registers. */ 604 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 605 sizeof(ctl)); 606 if (ret < 0) 607 return ret; 608 609 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE); 610 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF); 611 612 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 613 t->time.tm_sec = -1; 614 t->time.tm_min = bcd2bin(ald[0] & 0x7f); 615 t->time.tm_hour = bcd2bin(ald[1] & 0x7f); 616 t->time.tm_wday = -1; 617 t->time.tm_mday = bcd2bin(ald[2] & 0x7f); 618 t->time.tm_mon = -1; 619 t->time.tm_year = -1; 620 t->time.tm_yday = -1; 621 t->time.tm_isdst = -1; 622 623 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n", 624 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 625 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled); 626 627 return 0; 628 } 629 630 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t) 631 { 632 struct ds1307 *ds1307 = dev_get_drvdata(dev); 633 u8 ald[3], ctl[3]; 634 int ret; 635 636 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 637 "enabled=%d pending=%d\n", __func__, 638 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 639 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 640 t->enabled, t->pending); 641 642 /* Read control registers. */ 643 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 644 sizeof(ctl)); 645 if (ret < 0) 646 return ret; 647 648 ctl[0] &= RX8130_REG_EXTENSION_WADA; 649 ctl[1] &= ~RX8130_REG_FLAG_AF; 650 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 651 652 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 653 sizeof(ctl)); 654 if (ret < 0) 655 return ret; 656 657 /* Hardware alarm precision is 1 minute! */ 658 ald[0] = bin2bcd(t->time.tm_min); 659 ald[1] = bin2bcd(t->time.tm_hour); 660 ald[2] = bin2bcd(t->time.tm_mday); 661 662 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 663 sizeof(ald)); 664 if (ret < 0) 665 return ret; 666 667 if (!t->enabled) 668 return 0; 669 670 ctl[2] |= RX8130_REG_CONTROL0_AIE; 671 672 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]); 673 } 674 675 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled) 676 { 677 struct ds1307 *ds1307 = dev_get_drvdata(dev); 678 int ret, reg; 679 680 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®); 681 if (ret < 0) 682 return ret; 683 684 if (enabled) 685 reg |= RX8130_REG_CONTROL0_AIE; 686 else 687 reg &= ~RX8130_REG_CONTROL0_AIE; 688 689 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg); 690 } 691 692 static irqreturn_t mcp794xx_irq(int irq, void *dev_id) 693 { 694 struct ds1307 *ds1307 = dev_id; 695 struct mutex *lock = &ds1307->rtc->ops_lock; 696 int reg, ret; 697 698 mutex_lock(lock); 699 700 /* Check and clear alarm 0 interrupt flag. */ 701 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®); 702 if (ret) 703 goto out; 704 if (!(reg & MCP794XX_BIT_ALMX_IF)) 705 goto out; 706 reg &= ~MCP794XX_BIT_ALMX_IF; 707 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg); 708 if (ret) 709 goto out; 710 711 /* Disable alarm 0. */ 712 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 713 MCP794XX_BIT_ALM0_EN, 0); 714 if (ret) 715 goto out; 716 717 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 718 719 out: 720 mutex_unlock(lock); 721 722 return IRQ_HANDLED; 723 } 724 725 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t) 726 { 727 struct ds1307 *ds1307 = dev_get_drvdata(dev); 728 u8 regs[10]; 729 int ret; 730 731 /* Read control and alarm 0 registers. */ 732 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 733 sizeof(regs)); 734 if (ret) 735 return ret; 736 737 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN); 738 739 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 740 t->time.tm_sec = bcd2bin(regs[3] & 0x7f); 741 t->time.tm_min = bcd2bin(regs[4] & 0x7f); 742 t->time.tm_hour = bcd2bin(regs[5] & 0x3f); 743 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1; 744 t->time.tm_mday = bcd2bin(regs[7] & 0x3f); 745 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1; 746 t->time.tm_year = -1; 747 t->time.tm_yday = -1; 748 t->time.tm_isdst = -1; 749 750 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 751 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__, 752 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 753 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled, 754 !!(regs[6] & MCP794XX_BIT_ALMX_POL), 755 !!(regs[6] & MCP794XX_BIT_ALMX_IF), 756 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4); 757 758 return 0; 759 } 760 761 /* 762 * We may have a random RTC weekday, therefore calculate alarm weekday based 763 * on current weekday we read from the RTC timekeeping regs 764 */ 765 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm) 766 { 767 struct rtc_time tm_now; 768 int days_now, days_alarm, ret; 769 770 ret = ds1307_get_time(dev, &tm_now); 771 if (ret) 772 return ret; 773 774 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60); 775 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60); 776 777 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1; 778 } 779 780 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t) 781 { 782 struct ds1307 *ds1307 = dev_get_drvdata(dev); 783 unsigned char regs[10]; 784 int wday, ret; 785 786 wday = mcp794xx_alm_weekday(dev, &t->time); 787 if (wday < 0) 788 return wday; 789 790 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 791 "enabled=%d pending=%d\n", __func__, 792 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 793 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 794 t->enabled, t->pending); 795 796 /* Read control and alarm 0 registers. */ 797 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 798 sizeof(regs)); 799 if (ret) 800 return ret; 801 802 /* Set alarm 0, using 24-hour and day-of-month modes. */ 803 regs[3] = bin2bcd(t->time.tm_sec); 804 regs[4] = bin2bcd(t->time.tm_min); 805 regs[5] = bin2bcd(t->time.tm_hour); 806 regs[6] = wday; 807 regs[7] = bin2bcd(t->time.tm_mday); 808 regs[8] = bin2bcd(t->time.tm_mon + 1); 809 810 /* Clear the alarm 0 interrupt flag. */ 811 regs[6] &= ~MCP794XX_BIT_ALMX_IF; 812 /* Set alarm match: second, minute, hour, day, date, month. */ 813 regs[6] |= MCP794XX_MSK_ALMX_MATCH; 814 /* Disable interrupt. We will not enable until completely programmed */ 815 regs[0] &= ~MCP794XX_BIT_ALM0_EN; 816 817 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 818 sizeof(regs)); 819 if (ret) 820 return ret; 821 822 if (!t->enabled) 823 return 0; 824 regs[0] |= MCP794XX_BIT_ALM0_EN; 825 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]); 826 } 827 828 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled) 829 { 830 struct ds1307 *ds1307 = dev_get_drvdata(dev); 831 832 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 833 MCP794XX_BIT_ALM0_EN, 834 enabled ? MCP794XX_BIT_ALM0_EN : 0); 835 } 836 837 static int m41txx_rtc_read_offset(struct device *dev, long *offset) 838 { 839 struct ds1307 *ds1307 = dev_get_drvdata(dev); 840 unsigned int ctrl_reg; 841 u8 val; 842 843 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 844 845 val = ctrl_reg & M41TXX_M_CALIBRATION; 846 847 /* check if positive */ 848 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN) 849 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB); 850 else 851 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB); 852 853 return 0; 854 } 855 856 static int m41txx_rtc_set_offset(struct device *dev, long offset) 857 { 858 struct ds1307 *ds1307 = dev_get_drvdata(dev); 859 unsigned int ctrl_reg; 860 861 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET)) 862 return -ERANGE; 863 864 if (offset >= 0) { 865 ctrl_reg = DIV_ROUND_CLOSEST(offset, 866 M41TXX_POS_OFFSET_STEP_PPB); 867 ctrl_reg |= M41TXX_BIT_CALIB_SIGN; 868 } else { 869 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset), 870 M41TXX_NEG_OFFSET_STEP_PPB); 871 } 872 873 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, 874 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN, 875 ctrl_reg); 876 } 877 878 #ifdef CONFIG_WATCHDOG_CORE 879 static int ds1388_wdt_start(struct watchdog_device *wdt_dev) 880 { 881 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 882 u8 regs[2]; 883 int ret; 884 885 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG, 886 DS1388_BIT_WF, 0); 887 if (ret) 888 return ret; 889 890 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 891 DS1388_BIT_WDE | DS1388_BIT_RST, 0); 892 if (ret) 893 return ret; 894 895 /* 896 * watchdog timeouts are measured in seconds. So ignore hundredths of 897 * seconds field. 898 */ 899 regs[0] = 0; 900 regs[1] = bin2bcd(wdt_dev->timeout); 901 902 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 903 sizeof(regs)); 904 if (ret) 905 return ret; 906 907 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 908 DS1388_BIT_WDE | DS1388_BIT_RST, 909 DS1388_BIT_WDE | DS1388_BIT_RST); 910 } 911 912 static int ds1388_wdt_stop(struct watchdog_device *wdt_dev) 913 { 914 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 915 916 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 917 DS1388_BIT_WDE | DS1388_BIT_RST, 0); 918 } 919 920 static int ds1388_wdt_ping(struct watchdog_device *wdt_dev) 921 { 922 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 923 u8 regs[2]; 924 925 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 926 sizeof(regs)); 927 } 928 929 static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev, 930 unsigned int val) 931 { 932 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 933 u8 regs[2]; 934 935 wdt_dev->timeout = val; 936 regs[0] = 0; 937 regs[1] = bin2bcd(wdt_dev->timeout); 938 939 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 940 sizeof(regs)); 941 } 942 #endif 943 944 static const struct rtc_class_ops rx8130_rtc_ops = { 945 .read_time = ds1307_get_time, 946 .set_time = ds1307_set_time, 947 .read_alarm = rx8130_read_alarm, 948 .set_alarm = rx8130_set_alarm, 949 .alarm_irq_enable = rx8130_alarm_irq_enable, 950 }; 951 952 static const struct rtc_class_ops mcp794xx_rtc_ops = { 953 .read_time = ds1307_get_time, 954 .set_time = ds1307_set_time, 955 .read_alarm = mcp794xx_read_alarm, 956 .set_alarm = mcp794xx_set_alarm, 957 .alarm_irq_enable = mcp794xx_alarm_irq_enable, 958 }; 959 960 static const struct rtc_class_ops m41txx_rtc_ops = { 961 .read_time = ds1307_get_time, 962 .set_time = ds1307_set_time, 963 .read_alarm = ds1337_read_alarm, 964 .set_alarm = ds1337_set_alarm, 965 .alarm_irq_enable = ds1307_alarm_irq_enable, 966 .read_offset = m41txx_rtc_read_offset, 967 .set_offset = m41txx_rtc_set_offset, 968 }; 969 970 static const struct chip_desc chips[last_ds_type] = { 971 [ds_1307] = { 972 .nvram_offset = 8, 973 .nvram_size = 56, 974 }, 975 [ds_1308] = { 976 .nvram_offset = 8, 977 .nvram_size = 56, 978 }, 979 [ds_1337] = { 980 .alarm = 1, 981 .century_reg = DS1307_REG_MONTH, 982 .century_bit = DS1337_BIT_CENTURY, 983 }, 984 [ds_1338] = { 985 .nvram_offset = 8, 986 .nvram_size = 56, 987 }, 988 [ds_1339] = { 989 .alarm = 1, 990 .century_reg = DS1307_REG_MONTH, 991 .century_bit = DS1337_BIT_CENTURY, 992 .bbsqi_bit = DS1339_BIT_BBSQI, 993 .trickle_charger_reg = 0x10, 994 .do_trickle_setup = &do_trickle_setup_ds1339, 995 .requires_trickle_resistor = true, 996 .charge_default = true, 997 }, 998 [ds_1340] = { 999 .century_reg = DS1307_REG_HOUR, 1000 .century_enable_bit = DS1340_BIT_CENTURY_EN, 1001 .century_bit = DS1340_BIT_CENTURY, 1002 .do_trickle_setup = &do_trickle_setup_ds1339, 1003 .trickle_charger_reg = 0x08, 1004 .requires_trickle_resistor = true, 1005 .charge_default = true, 1006 }, 1007 [ds_1341] = { 1008 .century_reg = DS1307_REG_MONTH, 1009 .century_bit = DS1337_BIT_CENTURY, 1010 }, 1011 [ds_1388] = { 1012 .offset = 1, 1013 .trickle_charger_reg = 0x0a, 1014 }, 1015 [ds_3231] = { 1016 .alarm = 1, 1017 .century_reg = DS1307_REG_MONTH, 1018 .century_bit = DS1337_BIT_CENTURY, 1019 .bbsqi_bit = DS3231_BIT_BBSQW, 1020 }, 1021 [rx_8130] = { 1022 .alarm = 1, 1023 /* this is battery backed SRAM */ 1024 .nvram_offset = 0x20, 1025 .nvram_size = 4, /* 32bit (4 word x 8 bit) */ 1026 .offset = 0x10, 1027 .irq_handler = rx8130_irq, 1028 .rtc_ops = &rx8130_rtc_ops, 1029 .trickle_charger_reg = RX8130_REG_CONTROL1, 1030 .do_trickle_setup = &do_trickle_setup_rx8130, 1031 }, 1032 [m41t0] = { 1033 .rtc_ops = &m41txx_rtc_ops, 1034 }, 1035 [m41t00] = { 1036 .rtc_ops = &m41txx_rtc_ops, 1037 }, 1038 [m41t11] = { 1039 /* this is battery backed SRAM */ 1040 .nvram_offset = 8, 1041 .nvram_size = 56, 1042 .rtc_ops = &m41txx_rtc_ops, 1043 }, 1044 [mcp794xx] = { 1045 .alarm = 1, 1046 /* this is battery backed SRAM */ 1047 .nvram_offset = 0x20, 1048 .nvram_size = 0x40, 1049 .irq_handler = mcp794xx_irq, 1050 .rtc_ops = &mcp794xx_rtc_ops, 1051 }, 1052 }; 1053 1054 static const struct i2c_device_id ds1307_id[] = { 1055 { "ds1307", ds_1307 }, 1056 { "ds1308", ds_1308 }, 1057 { "ds1337", ds_1337 }, 1058 { "ds1338", ds_1338 }, 1059 { "ds1339", ds_1339 }, 1060 { "ds1388", ds_1388 }, 1061 { "ds1340", ds_1340 }, 1062 { "ds1341", ds_1341 }, 1063 { "ds3231", ds_3231 }, 1064 { "m41t0", m41t0 }, 1065 { "m41t00", m41t00 }, 1066 { "m41t11", m41t11 }, 1067 { "mcp7940x", mcp794xx }, 1068 { "mcp7941x", mcp794xx }, 1069 { "pt7c4338", ds_1307 }, 1070 { "rx8025", rx_8025 }, 1071 { "isl12057", ds_1337 }, 1072 { "rx8130", rx_8130 }, 1073 { } 1074 }; 1075 MODULE_DEVICE_TABLE(i2c, ds1307_id); 1076 1077 static const struct of_device_id ds1307_of_match[] = { 1078 { 1079 .compatible = "dallas,ds1307", 1080 .data = (void *)ds_1307 1081 }, 1082 { 1083 .compatible = "dallas,ds1308", 1084 .data = (void *)ds_1308 1085 }, 1086 { 1087 .compatible = "dallas,ds1337", 1088 .data = (void *)ds_1337 1089 }, 1090 { 1091 .compatible = "dallas,ds1338", 1092 .data = (void *)ds_1338 1093 }, 1094 { 1095 .compatible = "dallas,ds1339", 1096 .data = (void *)ds_1339 1097 }, 1098 { 1099 .compatible = "dallas,ds1388", 1100 .data = (void *)ds_1388 1101 }, 1102 { 1103 .compatible = "dallas,ds1340", 1104 .data = (void *)ds_1340 1105 }, 1106 { 1107 .compatible = "dallas,ds1341", 1108 .data = (void *)ds_1341 1109 }, 1110 { 1111 .compatible = "maxim,ds3231", 1112 .data = (void *)ds_3231 1113 }, 1114 { 1115 .compatible = "st,m41t0", 1116 .data = (void *)m41t0 1117 }, 1118 { 1119 .compatible = "st,m41t00", 1120 .data = (void *)m41t00 1121 }, 1122 { 1123 .compatible = "st,m41t11", 1124 .data = (void *)m41t11 1125 }, 1126 { 1127 .compatible = "microchip,mcp7940x", 1128 .data = (void *)mcp794xx 1129 }, 1130 { 1131 .compatible = "microchip,mcp7941x", 1132 .data = (void *)mcp794xx 1133 }, 1134 { 1135 .compatible = "pericom,pt7c4338", 1136 .data = (void *)ds_1307 1137 }, 1138 { 1139 .compatible = "epson,rx8025", 1140 .data = (void *)rx_8025 1141 }, 1142 { 1143 .compatible = "isil,isl12057", 1144 .data = (void *)ds_1337 1145 }, 1146 { 1147 .compatible = "epson,rx8130", 1148 .data = (void *)rx_8130 1149 }, 1150 { } 1151 }; 1152 MODULE_DEVICE_TABLE(of, ds1307_of_match); 1153 1154 /* 1155 * The ds1337 and ds1339 both have two alarms, but we only use the first 1156 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm 1157 * signal; ds1339 chips have only one alarm signal. 1158 */ 1159 static irqreturn_t ds1307_irq(int irq, void *dev_id) 1160 { 1161 struct ds1307 *ds1307 = dev_id; 1162 struct mutex *lock = &ds1307->rtc->ops_lock; 1163 int stat, ret; 1164 1165 mutex_lock(lock); 1166 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat); 1167 if (ret) 1168 goto out; 1169 1170 if (stat & DS1337_BIT_A1I) { 1171 stat &= ~DS1337_BIT_A1I; 1172 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat); 1173 1174 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1175 DS1337_BIT_A1IE, 0); 1176 if (ret) 1177 goto out; 1178 1179 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 1180 } 1181 1182 out: 1183 mutex_unlock(lock); 1184 1185 return IRQ_HANDLED; 1186 } 1187 1188 /*----------------------------------------------------------------------*/ 1189 1190 static const struct rtc_class_ops ds13xx_rtc_ops = { 1191 .read_time = ds1307_get_time, 1192 .set_time = ds1307_set_time, 1193 .read_alarm = ds1337_read_alarm, 1194 .set_alarm = ds1337_set_alarm, 1195 .alarm_irq_enable = ds1307_alarm_irq_enable, 1196 }; 1197 1198 static ssize_t frequency_test_store(struct device *dev, 1199 struct device_attribute *attr, 1200 const char *buf, size_t count) 1201 { 1202 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1203 bool freq_test_en; 1204 int ret; 1205 1206 ret = kstrtobool(buf, &freq_test_en); 1207 if (ret) { 1208 dev_err(dev, "Failed to store RTC Frequency Test attribute\n"); 1209 return ret; 1210 } 1211 1212 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT, 1213 freq_test_en ? M41TXX_BIT_FT : 0); 1214 1215 return count; 1216 } 1217 1218 static ssize_t frequency_test_show(struct device *dev, 1219 struct device_attribute *attr, 1220 char *buf) 1221 { 1222 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1223 unsigned int ctrl_reg; 1224 1225 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 1226 1227 return sysfs_emit(buf, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" : "off\n"); 1228 } 1229 1230 static DEVICE_ATTR_RW(frequency_test); 1231 1232 static struct attribute *rtc_freq_test_attrs[] = { 1233 &dev_attr_frequency_test.attr, 1234 NULL, 1235 }; 1236 1237 static const struct attribute_group rtc_freq_test_attr_group = { 1238 .attrs = rtc_freq_test_attrs, 1239 }; 1240 1241 static int ds1307_add_frequency_test(struct ds1307 *ds1307) 1242 { 1243 int err; 1244 1245 switch (ds1307->type) { 1246 case m41t0: 1247 case m41t00: 1248 case m41t11: 1249 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group); 1250 if (err) 1251 return err; 1252 break; 1253 default: 1254 break; 1255 } 1256 1257 return 0; 1258 } 1259 1260 /*----------------------------------------------------------------------*/ 1261 1262 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val, 1263 size_t bytes) 1264 { 1265 struct ds1307 *ds1307 = priv; 1266 const struct chip_desc *chip = &chips[ds1307->type]; 1267 1268 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset, 1269 val, bytes); 1270 } 1271 1272 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val, 1273 size_t bytes) 1274 { 1275 struct ds1307 *ds1307 = priv; 1276 const struct chip_desc *chip = &chips[ds1307->type]; 1277 1278 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset, 1279 val, bytes); 1280 } 1281 1282 /*----------------------------------------------------------------------*/ 1283 1284 static u8 ds1307_trickle_init(struct ds1307 *ds1307, 1285 const struct chip_desc *chip) 1286 { 1287 u32 ohms, chargeable; 1288 bool diode = chip->charge_default; 1289 1290 if (!chip->do_trickle_setup) 1291 return 0; 1292 1293 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms", 1294 &ohms) && chip->requires_trickle_resistor) 1295 return 0; 1296 1297 /* aux-voltage-chargeable takes precedence over the deprecated 1298 * trickle-diode-disable 1299 */ 1300 if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable", 1301 &chargeable)) { 1302 switch (chargeable) { 1303 case 0: 1304 diode = false; 1305 break; 1306 case 1: 1307 diode = true; 1308 break; 1309 default: 1310 dev_warn(ds1307->dev, 1311 "unsupported aux-voltage-chargeable value\n"); 1312 break; 1313 } 1314 } else if (device_property_read_bool(ds1307->dev, 1315 "trickle-diode-disable")) { 1316 diode = false; 1317 } 1318 1319 return chip->do_trickle_setup(ds1307, ohms, diode); 1320 } 1321 1322 /*----------------------------------------------------------------------*/ 1323 1324 #if IS_REACHABLE(CONFIG_HWMON) 1325 1326 /* 1327 * Temperature sensor support for ds3231 devices. 1328 */ 1329 1330 #define DS3231_REG_TEMPERATURE 0x11 1331 1332 /* 1333 * A user-initiated temperature conversion is not started by this function, 1334 * so the temperature is updated once every 64 seconds. 1335 */ 1336 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC) 1337 { 1338 struct ds1307 *ds1307 = dev_get_drvdata(dev); 1339 u8 temp_buf[2]; 1340 s16 temp; 1341 int ret; 1342 1343 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE, 1344 temp_buf, sizeof(temp_buf)); 1345 if (ret) 1346 return ret; 1347 /* 1348 * Temperature is represented as a 10-bit code with a resolution of 1349 * 0.25 degree celsius and encoded in two's complement format. 1350 */ 1351 temp = (temp_buf[0] << 8) | temp_buf[1]; 1352 temp >>= 6; 1353 *mC = temp * 250; 1354 1355 return 0; 1356 } 1357 1358 static ssize_t ds3231_hwmon_show_temp(struct device *dev, 1359 struct device_attribute *attr, char *buf) 1360 { 1361 int ret; 1362 s32 temp; 1363 1364 ret = ds3231_hwmon_read_temp(dev, &temp); 1365 if (ret) 1366 return ret; 1367 1368 return sprintf(buf, "%d\n", temp); 1369 } 1370 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp, 1371 NULL, 0); 1372 1373 static struct attribute *ds3231_hwmon_attrs[] = { 1374 &sensor_dev_attr_temp1_input.dev_attr.attr, 1375 NULL, 1376 }; 1377 ATTRIBUTE_GROUPS(ds3231_hwmon); 1378 1379 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1380 { 1381 struct device *dev; 1382 1383 if (ds1307->type != ds_3231) 1384 return; 1385 1386 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name, 1387 ds1307, 1388 ds3231_hwmon_groups); 1389 if (IS_ERR(dev)) { 1390 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n", 1391 PTR_ERR(dev)); 1392 } 1393 } 1394 1395 #else 1396 1397 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1398 { 1399 } 1400 1401 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */ 1402 1403 /*----------------------------------------------------------------------*/ 1404 1405 /* 1406 * Square-wave output support for DS3231 1407 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf 1408 */ 1409 #ifdef CONFIG_COMMON_CLK 1410 1411 enum { 1412 DS3231_CLK_SQW = 0, 1413 DS3231_CLK_32KHZ, 1414 }; 1415 1416 #define clk_sqw_to_ds1307(clk) \ 1417 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW]) 1418 #define clk_32khz_to_ds1307(clk) \ 1419 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ]) 1420 1421 static int ds3231_clk_sqw_rates[] = { 1422 1, 1423 1024, 1424 4096, 1425 8192, 1426 }; 1427 1428 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value) 1429 { 1430 struct mutex *lock = &ds1307->rtc->ops_lock; 1431 int ret; 1432 1433 mutex_lock(lock); 1434 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1435 mask, value); 1436 mutex_unlock(lock); 1437 1438 return ret; 1439 } 1440 1441 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw, 1442 unsigned long parent_rate) 1443 { 1444 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1445 int control, ret; 1446 int rate_sel = 0; 1447 1448 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1449 if (ret) 1450 return ret; 1451 if (control & DS1337_BIT_RS1) 1452 rate_sel += 1; 1453 if (control & DS1337_BIT_RS2) 1454 rate_sel += 2; 1455 1456 return ds3231_clk_sqw_rates[rate_sel]; 1457 } 1458 1459 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate, 1460 unsigned long *prate) 1461 { 1462 int i; 1463 1464 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) { 1465 if (ds3231_clk_sqw_rates[i] <= rate) 1466 return ds3231_clk_sqw_rates[i]; 1467 } 1468 1469 return 0; 1470 } 1471 1472 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate, 1473 unsigned long parent_rate) 1474 { 1475 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1476 int control = 0; 1477 int rate_sel; 1478 1479 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates); 1480 rate_sel++) { 1481 if (ds3231_clk_sqw_rates[rate_sel] == rate) 1482 break; 1483 } 1484 1485 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates)) 1486 return -EINVAL; 1487 1488 if (rate_sel & 1) 1489 control |= DS1337_BIT_RS1; 1490 if (rate_sel & 2) 1491 control |= DS1337_BIT_RS2; 1492 1493 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2, 1494 control); 1495 } 1496 1497 static int ds3231_clk_sqw_prepare(struct clk_hw *hw) 1498 { 1499 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1500 1501 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0); 1502 } 1503 1504 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw) 1505 { 1506 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1507 1508 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN); 1509 } 1510 1511 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw) 1512 { 1513 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1514 int control, ret; 1515 1516 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1517 if (ret) 1518 return ret; 1519 1520 return !(control & DS1337_BIT_INTCN); 1521 } 1522 1523 static const struct clk_ops ds3231_clk_sqw_ops = { 1524 .prepare = ds3231_clk_sqw_prepare, 1525 .unprepare = ds3231_clk_sqw_unprepare, 1526 .is_prepared = ds3231_clk_sqw_is_prepared, 1527 .recalc_rate = ds3231_clk_sqw_recalc_rate, 1528 .round_rate = ds3231_clk_sqw_round_rate, 1529 .set_rate = ds3231_clk_sqw_set_rate, 1530 }; 1531 1532 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw, 1533 unsigned long parent_rate) 1534 { 1535 return 32768; 1536 } 1537 1538 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable) 1539 { 1540 struct mutex *lock = &ds1307->rtc->ops_lock; 1541 int ret; 1542 1543 mutex_lock(lock); 1544 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS, 1545 DS3231_BIT_EN32KHZ, 1546 enable ? DS3231_BIT_EN32KHZ : 0); 1547 mutex_unlock(lock); 1548 1549 return ret; 1550 } 1551 1552 static int ds3231_clk_32khz_prepare(struct clk_hw *hw) 1553 { 1554 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1555 1556 return ds3231_clk_32khz_control(ds1307, true); 1557 } 1558 1559 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw) 1560 { 1561 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1562 1563 ds3231_clk_32khz_control(ds1307, false); 1564 } 1565 1566 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw) 1567 { 1568 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1569 int status, ret; 1570 1571 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status); 1572 if (ret) 1573 return ret; 1574 1575 return !!(status & DS3231_BIT_EN32KHZ); 1576 } 1577 1578 static const struct clk_ops ds3231_clk_32khz_ops = { 1579 .prepare = ds3231_clk_32khz_prepare, 1580 .unprepare = ds3231_clk_32khz_unprepare, 1581 .is_prepared = ds3231_clk_32khz_is_prepared, 1582 .recalc_rate = ds3231_clk_32khz_recalc_rate, 1583 }; 1584 1585 static const char *ds3231_clks_names[] = { 1586 [DS3231_CLK_SQW] = "ds3231_clk_sqw", 1587 [DS3231_CLK_32KHZ] = "ds3231_clk_32khz", 1588 }; 1589 1590 static struct clk_init_data ds3231_clks_init[] = { 1591 [DS3231_CLK_SQW] = { 1592 .ops = &ds3231_clk_sqw_ops, 1593 }, 1594 [DS3231_CLK_32KHZ] = { 1595 .ops = &ds3231_clk_32khz_ops, 1596 }, 1597 }; 1598 1599 static int ds3231_clks_register(struct ds1307 *ds1307) 1600 { 1601 struct device_node *node = ds1307->dev->of_node; 1602 struct clk_onecell_data *onecell; 1603 int i; 1604 1605 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL); 1606 if (!onecell) 1607 return -ENOMEM; 1608 1609 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init); 1610 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num, 1611 sizeof(onecell->clks[0]), GFP_KERNEL); 1612 if (!onecell->clks) 1613 return -ENOMEM; 1614 1615 /* optional override of the clockname */ 1616 device_property_read_string_array(ds1307->dev, "clock-output-names", 1617 ds3231_clks_names, 1618 ARRAY_SIZE(ds3231_clks_names)); 1619 1620 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) { 1621 struct clk_init_data init = ds3231_clks_init[i]; 1622 1623 /* 1624 * Interrupt signal due to alarm conditions and square-wave 1625 * output share same pin, so don't initialize both. 1626 */ 1627 if (i == DS3231_CLK_SQW && test_bit(RTC_FEATURE_ALARM, ds1307->rtc->features)) 1628 continue; 1629 1630 init.name = ds3231_clks_names[i]; 1631 ds1307->clks[i].init = &init; 1632 1633 onecell->clks[i] = devm_clk_register(ds1307->dev, 1634 &ds1307->clks[i]); 1635 if (IS_ERR(onecell->clks[i])) 1636 return PTR_ERR(onecell->clks[i]); 1637 } 1638 1639 if (node) 1640 of_clk_add_provider(node, of_clk_src_onecell_get, onecell); 1641 1642 return 0; 1643 } 1644 1645 static void ds1307_clks_register(struct ds1307 *ds1307) 1646 { 1647 int ret; 1648 1649 if (ds1307->type != ds_3231) 1650 return; 1651 1652 ret = ds3231_clks_register(ds1307); 1653 if (ret) { 1654 dev_warn(ds1307->dev, "unable to register clock device %d\n", 1655 ret); 1656 } 1657 } 1658 1659 #else 1660 1661 static void ds1307_clks_register(struct ds1307 *ds1307) 1662 { 1663 } 1664 1665 #endif /* CONFIG_COMMON_CLK */ 1666 1667 #ifdef CONFIG_WATCHDOG_CORE 1668 static const struct watchdog_info ds1388_wdt_info = { 1669 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, 1670 .identity = "DS1388 watchdog", 1671 }; 1672 1673 static const struct watchdog_ops ds1388_wdt_ops = { 1674 .owner = THIS_MODULE, 1675 .start = ds1388_wdt_start, 1676 .stop = ds1388_wdt_stop, 1677 .ping = ds1388_wdt_ping, 1678 .set_timeout = ds1388_wdt_set_timeout, 1679 1680 }; 1681 1682 static void ds1307_wdt_register(struct ds1307 *ds1307) 1683 { 1684 struct watchdog_device *wdt; 1685 int err; 1686 int val; 1687 1688 if (ds1307->type != ds_1388) 1689 return; 1690 1691 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL); 1692 if (!wdt) 1693 return; 1694 1695 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val); 1696 if (!err && val & DS1388_BIT_WF) 1697 wdt->bootstatus = WDIOF_CARDRESET; 1698 1699 wdt->info = &ds1388_wdt_info; 1700 wdt->ops = &ds1388_wdt_ops; 1701 wdt->timeout = 99; 1702 wdt->max_timeout = 99; 1703 wdt->min_timeout = 1; 1704 1705 watchdog_init_timeout(wdt, 0, ds1307->dev); 1706 watchdog_set_drvdata(wdt, ds1307); 1707 devm_watchdog_register_device(ds1307->dev, wdt); 1708 } 1709 #else 1710 static void ds1307_wdt_register(struct ds1307 *ds1307) 1711 { 1712 } 1713 #endif /* CONFIG_WATCHDOG_CORE */ 1714 1715 static const struct regmap_config regmap_config = { 1716 .reg_bits = 8, 1717 .val_bits = 8, 1718 }; 1719 1720 static int ds1307_probe(struct i2c_client *client) 1721 { 1722 const struct i2c_device_id *id = i2c_client_get_device_id(client); 1723 struct ds1307 *ds1307; 1724 const void *match; 1725 int err = -ENODEV; 1726 int tmp; 1727 const struct chip_desc *chip; 1728 bool want_irq; 1729 bool ds1307_can_wakeup_device = false; 1730 unsigned char regs[8]; 1731 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev); 1732 u8 trickle_charger_setup = 0; 1733 1734 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL); 1735 if (!ds1307) 1736 return -ENOMEM; 1737 1738 dev_set_drvdata(&client->dev, ds1307); 1739 ds1307->dev = &client->dev; 1740 ds1307->name = client->name; 1741 1742 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config); 1743 if (IS_ERR(ds1307->regmap)) { 1744 dev_err(ds1307->dev, "regmap allocation failed\n"); 1745 return PTR_ERR(ds1307->regmap); 1746 } 1747 1748 i2c_set_clientdata(client, ds1307); 1749 1750 match = device_get_match_data(&client->dev); 1751 if (match) { 1752 ds1307->type = (uintptr_t)match; 1753 chip = &chips[ds1307->type]; 1754 } else if (id) { 1755 chip = &chips[id->driver_data]; 1756 ds1307->type = id->driver_data; 1757 } else { 1758 return -ENODEV; 1759 } 1760 1761 want_irq = client->irq > 0 && chip->alarm; 1762 1763 if (!pdata) 1764 trickle_charger_setup = ds1307_trickle_init(ds1307, chip); 1765 else if (pdata->trickle_charger_setup) 1766 trickle_charger_setup = pdata->trickle_charger_setup; 1767 1768 if (trickle_charger_setup && chip->trickle_charger_reg) { 1769 dev_dbg(ds1307->dev, 1770 "writing trickle charger info 0x%x to 0x%x\n", 1771 trickle_charger_setup, chip->trickle_charger_reg); 1772 regmap_write(ds1307->regmap, chip->trickle_charger_reg, 1773 trickle_charger_setup); 1774 } 1775 1776 /* 1777 * For devices with no IRQ directly connected to the SoC, the RTC chip 1778 * can be forced as a wakeup source by stating that explicitly in 1779 * the device's .dts file using the "wakeup-source" boolean property. 1780 * If the "wakeup-source" property is set, don't request an IRQ. 1781 * This will guarantee the 'wakealarm' sysfs entry is available on the device, 1782 * if supported by the RTC. 1783 */ 1784 if (chip->alarm && device_property_read_bool(&client->dev, "wakeup-source")) 1785 ds1307_can_wakeup_device = true; 1786 1787 switch (ds1307->type) { 1788 case ds_1337: 1789 case ds_1339: 1790 case ds_1341: 1791 case ds_3231: 1792 /* get registers that the "rtc" read below won't read... */ 1793 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL, 1794 regs, 2); 1795 if (err) { 1796 dev_dbg(ds1307->dev, "read error %d\n", err); 1797 goto exit; 1798 } 1799 1800 /* oscillator off? turn it on, so clock can tick. */ 1801 if (regs[0] & DS1337_BIT_nEOSC) 1802 regs[0] &= ~DS1337_BIT_nEOSC; 1803 1804 /* 1805 * Using IRQ or defined as wakeup-source? 1806 * Disable the square wave and both alarms. 1807 * For some variants, be sure alarms can trigger when we're 1808 * running on Vbackup (BBSQI/BBSQW) 1809 */ 1810 if (want_irq || ds1307_can_wakeup_device) { 1811 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit; 1812 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE); 1813 } 1814 1815 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, 1816 regs[0]); 1817 1818 /* oscillator fault? clear flag, and warn */ 1819 if (regs[1] & DS1337_BIT_OSF) { 1820 regmap_write(ds1307->regmap, DS1337_REG_STATUS, 1821 regs[1] & ~DS1337_BIT_OSF); 1822 dev_warn(ds1307->dev, "SET TIME!\n"); 1823 } 1824 break; 1825 1826 case rx_8025: 1827 err = regmap_bulk_read(ds1307->regmap, 1828 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2); 1829 if (err) { 1830 dev_dbg(ds1307->dev, "read error %d\n", err); 1831 goto exit; 1832 } 1833 1834 /* oscillator off? turn it on, so clock can tick. */ 1835 if (!(regs[1] & RX8025_BIT_XST)) { 1836 regs[1] |= RX8025_BIT_XST; 1837 regmap_write(ds1307->regmap, 1838 RX8025_REG_CTRL2 << 4 | 0x08, 1839 regs[1]); 1840 dev_warn(ds1307->dev, 1841 "oscillator stop detected - SET TIME!\n"); 1842 } 1843 1844 if (regs[1] & RX8025_BIT_PON) { 1845 regs[1] &= ~RX8025_BIT_PON; 1846 regmap_write(ds1307->regmap, 1847 RX8025_REG_CTRL2 << 4 | 0x08, 1848 regs[1]); 1849 dev_warn(ds1307->dev, "power-on detected\n"); 1850 } 1851 1852 if (regs[1] & RX8025_BIT_VDET) { 1853 regs[1] &= ~RX8025_BIT_VDET; 1854 regmap_write(ds1307->regmap, 1855 RX8025_REG_CTRL2 << 4 | 0x08, 1856 regs[1]); 1857 dev_warn(ds1307->dev, "voltage drop detected\n"); 1858 } 1859 1860 /* make sure we are running in 24hour mode */ 1861 if (!(regs[0] & RX8025_BIT_2412)) { 1862 u8 hour; 1863 1864 /* switch to 24 hour mode */ 1865 regmap_write(ds1307->regmap, 1866 RX8025_REG_CTRL1 << 4 | 0x08, 1867 regs[0] | RX8025_BIT_2412); 1868 1869 err = regmap_bulk_read(ds1307->regmap, 1870 RX8025_REG_CTRL1 << 4 | 0x08, 1871 regs, 2); 1872 if (err) { 1873 dev_dbg(ds1307->dev, "read error %d\n", err); 1874 goto exit; 1875 } 1876 1877 /* correct hour */ 1878 hour = bcd2bin(regs[DS1307_REG_HOUR]); 1879 if (hour == 12) 1880 hour = 0; 1881 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 1882 hour += 12; 1883 1884 regmap_write(ds1307->regmap, 1885 DS1307_REG_HOUR << 4 | 0x08, hour); 1886 } 1887 break; 1888 case ds_1388: 1889 err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp); 1890 if (err) { 1891 dev_dbg(ds1307->dev, "read error %d\n", err); 1892 goto exit; 1893 } 1894 1895 /* oscillator off? turn it on, so clock can tick. */ 1896 if (tmp & DS1388_BIT_nEOSC) { 1897 tmp &= ~DS1388_BIT_nEOSC; 1898 regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp); 1899 } 1900 break; 1901 default: 1902 break; 1903 } 1904 1905 /* read RTC registers */ 1906 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 1907 sizeof(regs)); 1908 if (err) { 1909 dev_dbg(ds1307->dev, "read error %d\n", err); 1910 goto exit; 1911 } 1912 1913 if (ds1307->type == mcp794xx && 1914 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) { 1915 regmap_write(ds1307->regmap, DS1307_REG_WDAY, 1916 regs[DS1307_REG_WDAY] | 1917 MCP794XX_BIT_VBATEN); 1918 } 1919 1920 tmp = regs[DS1307_REG_HOUR]; 1921 switch (ds1307->type) { 1922 case ds_1340: 1923 case m41t0: 1924 case m41t00: 1925 case m41t11: 1926 /* 1927 * NOTE: ignores century bits; fix before deploying 1928 * systems that will run through year 2100. 1929 */ 1930 break; 1931 case rx_8025: 1932 break; 1933 default: 1934 if (!(tmp & DS1307_BIT_12HR)) 1935 break; 1936 1937 /* 1938 * Be sure we're in 24 hour mode. Multi-master systems 1939 * take note... 1940 */ 1941 tmp = bcd2bin(tmp & 0x1f); 1942 if (tmp == 12) 1943 tmp = 0; 1944 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 1945 tmp += 12; 1946 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR, 1947 bin2bcd(tmp)); 1948 } 1949 1950 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev); 1951 if (IS_ERR(ds1307->rtc)) 1952 return PTR_ERR(ds1307->rtc); 1953 1954 if (want_irq || ds1307_can_wakeup_device) 1955 device_set_wakeup_capable(ds1307->dev, true); 1956 else 1957 clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features); 1958 1959 if (ds1307_can_wakeup_device && !want_irq) { 1960 dev_info(ds1307->dev, 1961 "'wakeup-source' is set, request for an IRQ is disabled!\n"); 1962 /* We cannot support UIE mode if we do not have an IRQ line */ 1963 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, ds1307->rtc->features); 1964 } 1965 1966 if (want_irq) { 1967 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL, 1968 chip->irq_handler ?: ds1307_irq, 1969 IRQF_SHARED | IRQF_ONESHOT, 1970 ds1307->name, ds1307); 1971 if (err) { 1972 client->irq = 0; 1973 device_set_wakeup_capable(ds1307->dev, false); 1974 clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features); 1975 dev_err(ds1307->dev, "unable to request IRQ!\n"); 1976 } else { 1977 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq); 1978 } 1979 } 1980 1981 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops; 1982 err = ds1307_add_frequency_test(ds1307); 1983 if (err) 1984 return err; 1985 1986 err = devm_rtc_register_device(ds1307->rtc); 1987 if (err) 1988 return err; 1989 1990 if (chip->nvram_size) { 1991 struct nvmem_config nvmem_cfg = { 1992 .name = "ds1307_nvram", 1993 .word_size = 1, 1994 .stride = 1, 1995 .size = chip->nvram_size, 1996 .reg_read = ds1307_nvram_read, 1997 .reg_write = ds1307_nvram_write, 1998 .priv = ds1307, 1999 }; 2000 2001 devm_rtc_nvmem_register(ds1307->rtc, &nvmem_cfg); 2002 } 2003 2004 ds1307_hwmon_register(ds1307); 2005 ds1307_clks_register(ds1307); 2006 ds1307_wdt_register(ds1307); 2007 2008 return 0; 2009 2010 exit: 2011 return err; 2012 } 2013 2014 static struct i2c_driver ds1307_driver = { 2015 .driver = { 2016 .name = "rtc-ds1307", 2017 .of_match_table = ds1307_of_match, 2018 }, 2019 .probe = ds1307_probe, 2020 .id_table = ds1307_id, 2021 }; 2022 2023 module_i2c_driver(ds1307_driver); 2024 2025 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); 2026 MODULE_LICENSE("GPL"); 2027