1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. 4 * 5 * Copyright (C) 2005 James Chapman (ds1337 core) 6 * Copyright (C) 2006 David Brownell 7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support) 8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes) 9 */ 10 11 #include <linux/bcd.h> 12 #include <linux/i2c.h> 13 #include <linux/init.h> 14 #include <linux/kstrtox.h> 15 #include <linux/module.h> 16 #include <linux/property.h> 17 #include <linux/rtc/ds1307.h> 18 #include <linux/rtc.h> 19 #include <linux/slab.h> 20 #include <linux/string.h> 21 #include <linux/hwmon.h> 22 #include <linux/hwmon-sysfs.h> 23 #include <linux/clk-provider.h> 24 #include <linux/regmap.h> 25 #include <linux/watchdog.h> 26 27 /* 28 * We can't determine type by probing, but if we expect pre-Linux code 29 * to have set the chip up as a clock (turning on the oscillator and 30 * setting the date and time), Linux can ignore the non-clock features. 31 * That's a natural job for a factory or repair bench. 32 */ 33 enum ds_type { 34 unknown_ds_type, /* always first and 0 */ 35 ds_1307, 36 ds_1308, 37 ds_1337, 38 ds_1338, 39 ds_1339, 40 ds_1340, 41 ds_1341, 42 ds_1388, 43 ds_3231, 44 m41t0, 45 m41t00, 46 m41t11, 47 mcp794xx, 48 rx_8025, 49 rx_8130, 50 last_ds_type /* always last */ 51 /* rs5c372 too? different address... */ 52 }; 53 54 /* RTC registers don't differ much, except for the century flag */ 55 #define DS1307_REG_SECS 0x00 /* 00-59 */ 56 # define DS1307_BIT_CH 0x80 57 # define DS1340_BIT_nEOSC 0x80 58 # define MCP794XX_BIT_ST 0x80 59 #define DS1307_REG_MIN 0x01 /* 00-59 */ 60 # define M41T0_BIT_OF 0x80 61 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ 62 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ 63 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ 64 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ 65 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ 66 #define DS1307_REG_WDAY 0x03 /* 01-07 */ 67 # define MCP794XX_BIT_OSCRUN BIT(5) 68 # define MCP794XX_BIT_VBATEN 0x08 69 #define DS1307_REG_MDAY 0x04 /* 01-31 */ 70 #define DS1307_REG_MONTH 0x05 /* 01-12 */ 71 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ 72 #define DS1307_REG_YEAR 0x06 /* 00-99 */ 73 74 /* 75 * Other registers (control, status, alarms, trickle charge, NVRAM, etc) 76 * start at 7, and they differ a LOT. Only control and status matter for 77 * basic RTC date and time functionality; be careful using them. 78 */ 79 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */ 80 # define DS1307_BIT_OUT 0x80 81 # define DS1338_BIT_OSF 0x20 82 # define DS1307_BIT_SQWE 0x10 83 # define DS1307_BIT_RS1 0x02 84 # define DS1307_BIT_RS0 0x01 85 #define DS1337_REG_CONTROL 0x0e 86 # define DS1337_BIT_nEOSC 0x80 87 # define DS1339_BIT_BBSQI 0x20 88 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ 89 # define DS1337_BIT_RS2 0x10 90 # define DS1337_BIT_RS1 0x08 91 # define DS1337_BIT_INTCN 0x04 92 # define DS1337_BIT_A2IE 0x02 93 # define DS1337_BIT_A1IE 0x01 94 #define DS1340_REG_CONTROL 0x07 95 # define DS1340_BIT_OUT 0x80 96 # define DS1340_BIT_FT 0x40 97 # define DS1340_BIT_CALIB_SIGN 0x20 98 # define DS1340_M_CALIBRATION 0x1f 99 #define DS1340_REG_FLAG 0x09 100 # define DS1340_BIT_OSF 0x80 101 #define DS1337_REG_STATUS 0x0f 102 # define DS1337_BIT_OSF 0x80 103 # define DS3231_BIT_EN32KHZ 0x08 104 # define DS1337_BIT_A2I 0x02 105 # define DS1337_BIT_A1I 0x01 106 #define DS1339_REG_ALARM1_SECS 0x07 107 108 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0 109 110 #define RX8025_REG_CTRL1 0x0e 111 # define RX8025_BIT_2412 0x20 112 #define RX8025_REG_CTRL2 0x0f 113 # define RX8025_BIT_PON 0x10 114 # define RX8025_BIT_VDET 0x40 115 # define RX8025_BIT_XST 0x20 116 117 #define RX8130_REG_ALARM_MIN 0x17 118 #define RX8130_REG_ALARM_HOUR 0x18 119 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19 120 #define RX8130_REG_EXTENSION 0x1c 121 #define RX8130_REG_EXTENSION_WADA BIT(3) 122 #define RX8130_REG_FLAG 0x1d 123 #define RX8130_REG_FLAG_VLF BIT(1) 124 #define RX8130_REG_FLAG_AF BIT(3) 125 #define RX8130_REG_CONTROL0 0x1e 126 #define RX8130_REG_CONTROL0_AIE BIT(3) 127 #define RX8130_REG_CONTROL1 0x1f 128 #define RX8130_REG_CONTROL1_INIEN BIT(4) 129 #define RX8130_REG_CONTROL1_CHGEN BIT(5) 130 131 #define MCP794XX_REG_CONTROL 0x07 132 # define MCP794XX_BIT_ALM0_EN 0x10 133 # define MCP794XX_BIT_ALM1_EN 0x20 134 #define MCP794XX_REG_ALARM0_BASE 0x0a 135 #define MCP794XX_REG_ALARM0_CTRL 0x0d 136 #define MCP794XX_REG_ALARM1_BASE 0x11 137 #define MCP794XX_REG_ALARM1_CTRL 0x14 138 # define MCP794XX_BIT_ALMX_IF BIT(3) 139 # define MCP794XX_BIT_ALMX_C0 BIT(4) 140 # define MCP794XX_BIT_ALMX_C1 BIT(5) 141 # define MCP794XX_BIT_ALMX_C2 BIT(6) 142 # define MCP794XX_BIT_ALMX_POL BIT(7) 143 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \ 144 MCP794XX_BIT_ALMX_C1 | \ 145 MCP794XX_BIT_ALMX_C2) 146 147 #define M41TXX_REG_CONTROL 0x07 148 # define M41TXX_BIT_OUT BIT(7) 149 # define M41TXX_BIT_FT BIT(6) 150 # define M41TXX_BIT_CALIB_SIGN BIT(5) 151 # define M41TXX_M_CALIBRATION GENMASK(4, 0) 152 153 #define DS1388_REG_WDOG_HUN_SECS 0x08 154 #define DS1388_REG_WDOG_SECS 0x09 155 #define DS1388_REG_FLAG 0x0b 156 # define DS1388_BIT_WF BIT(6) 157 # define DS1388_BIT_OSF BIT(7) 158 #define DS1388_REG_CONTROL 0x0c 159 # define DS1388_BIT_RST BIT(0) 160 # define DS1388_BIT_WDE BIT(1) 161 # define DS1388_BIT_nEOSC BIT(7) 162 163 /* negative offset step is -2.034ppm */ 164 #define M41TXX_NEG_OFFSET_STEP_PPB 2034 165 /* positive offset step is +4.068ppm */ 166 #define M41TXX_POS_OFFSET_STEP_PPB 4068 167 /* Min and max values supported with 'offset' interface by M41TXX */ 168 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB) 169 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB) 170 171 struct ds1307 { 172 enum ds_type type; 173 struct device *dev; 174 struct regmap *regmap; 175 const char *name; 176 struct rtc_device *rtc; 177 #ifdef CONFIG_COMMON_CLK 178 struct clk_hw clks[2]; 179 #endif 180 }; 181 182 struct chip_desc { 183 unsigned alarm:1; 184 u16 nvram_offset; 185 u16 nvram_size; 186 u8 offset; /* register's offset */ 187 u8 century_reg; 188 u8 century_enable_bit; 189 u8 century_bit; 190 u8 bbsqi_bit; 191 irq_handler_t irq_handler; 192 const struct rtc_class_ops *rtc_ops; 193 u16 trickle_charger_reg; 194 u8 (*do_trickle_setup)(struct ds1307 *, u32, 195 bool); 196 /* Does the RTC require trickle-resistor-ohms to select the value of 197 * the resistor between Vcc and Vbackup? 198 */ 199 bool requires_trickle_resistor; 200 /* Some RTC's batteries and supercaps were charged by default, others 201 * allow charging but were not configured previously to do so. 202 * Remember this behavior to stay backwards compatible. 203 */ 204 bool charge_default; 205 }; 206 207 static const struct chip_desc chips[last_ds_type]; 208 209 static int ds1307_get_time(struct device *dev, struct rtc_time *t) 210 { 211 struct ds1307 *ds1307 = dev_get_drvdata(dev); 212 int tmp, ret; 213 const struct chip_desc *chip = &chips[ds1307->type]; 214 u8 regs[7]; 215 216 if (ds1307->type == rx_8130) { 217 unsigned int regflag; 218 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag); 219 if (ret) { 220 dev_err(dev, "%s error %d\n", "read", ret); 221 return ret; 222 } 223 224 if (regflag & RX8130_REG_FLAG_VLF) { 225 dev_warn_once(dev, "oscillator failed, set time!\n"); 226 return -EINVAL; 227 } 228 } 229 230 /* read the RTC date and time registers all at once */ 231 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 232 sizeof(regs)); 233 if (ret) { 234 dev_err(dev, "%s error %d\n", "read", ret); 235 return ret; 236 } 237 238 dev_dbg(dev, "%s: %7ph\n", "read", regs); 239 240 /* if oscillator fail bit is set, no data can be trusted */ 241 if (ds1307->type == m41t0 && 242 regs[DS1307_REG_MIN] & M41T0_BIT_OF) { 243 dev_warn_once(dev, "oscillator failed, set time!\n"); 244 return -EINVAL; 245 } else if (ds1307->type == mcp794xx && 246 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_OSCRUN)) { 247 dev_warn_once(dev, "oscillator failed, set time!\n"); 248 return -EINVAL; 249 } 250 251 tmp = regs[DS1307_REG_SECS]; 252 switch (ds1307->type) { 253 case ds_1307: 254 case m41t0: 255 case m41t00: 256 case m41t11: 257 if (tmp & DS1307_BIT_CH) 258 return -EINVAL; 259 break; 260 case ds_1308: 261 case ds_1338: 262 if (tmp & DS1307_BIT_CH) 263 return -EINVAL; 264 265 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp); 266 if (ret) 267 return ret; 268 if (tmp & DS1338_BIT_OSF) 269 return -EINVAL; 270 break; 271 case ds_1337: 272 case ds_1339: 273 case ds_1341: 274 case ds_3231: 275 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &tmp); 276 if (ret) 277 return ret; 278 if (tmp & DS1337_BIT_OSF) 279 return -EINVAL; 280 break; 281 case ds_1340: 282 if (tmp & DS1340_BIT_nEOSC) 283 return -EINVAL; 284 285 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp); 286 if (ret) 287 return ret; 288 if (tmp & DS1340_BIT_OSF) 289 return -EINVAL; 290 break; 291 case ds_1388: 292 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp); 293 if (ret) 294 return ret; 295 if (tmp & DS1388_BIT_OSF) 296 return -EINVAL; 297 break; 298 case mcp794xx: 299 if (!(tmp & MCP794XX_BIT_ST)) 300 return -EINVAL; 301 302 break; 303 default: 304 break; 305 } 306 307 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f); 308 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f); 309 tmp = regs[DS1307_REG_HOUR] & 0x3f; 310 t->tm_hour = bcd2bin(tmp); 311 /* rx8130 is bit position, not BCD */ 312 if (ds1307->type == rx_8130) 313 t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f) - 1; 314 else 315 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1; 316 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f); 317 tmp = regs[DS1307_REG_MONTH] & 0x1f; 318 t->tm_mon = bcd2bin(tmp) - 1; 319 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100; 320 321 if (regs[chip->century_reg] & chip->century_bit && 322 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY)) 323 t->tm_year += 100; 324 325 dev_dbg(dev, "%s secs=%d, mins=%d, " 326 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 327 "read", t->tm_sec, t->tm_min, 328 t->tm_hour, t->tm_mday, 329 t->tm_mon, t->tm_year, t->tm_wday); 330 331 return 0; 332 } 333 334 static int ds1307_set_time(struct device *dev, struct rtc_time *t) 335 { 336 struct ds1307 *ds1307 = dev_get_drvdata(dev); 337 const struct chip_desc *chip = &chips[ds1307->type]; 338 int result; 339 int tmp; 340 u8 regs[7]; 341 342 dev_dbg(dev, "%s secs=%d, mins=%d, " 343 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 344 "write", t->tm_sec, t->tm_min, 345 t->tm_hour, t->tm_mday, 346 t->tm_mon, t->tm_year, t->tm_wday); 347 348 if (t->tm_year < 100) 349 return -EINVAL; 350 351 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY 352 if (t->tm_year > (chip->century_bit ? 299 : 199)) 353 return -EINVAL; 354 #else 355 if (t->tm_year > 199) 356 return -EINVAL; 357 #endif 358 359 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec); 360 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min); 361 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); 362 /* rx8130 is bit position, not BCD */ 363 if (ds1307->type == rx_8130) 364 regs[DS1307_REG_WDAY] = 1 << t->tm_wday; 365 else 366 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); 367 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); 368 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); 369 370 /* assume 20YY not 19YY */ 371 tmp = t->tm_year % 100; 372 regs[DS1307_REG_YEAR] = bin2bcd(tmp); 373 374 if (chip->century_enable_bit) 375 regs[chip->century_reg] |= chip->century_enable_bit; 376 if (t->tm_year > 199 && chip->century_bit) 377 regs[chip->century_reg] |= chip->century_bit; 378 379 switch (ds1307->type) { 380 case ds_1308: 381 case ds_1338: 382 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL, 383 DS1338_BIT_OSF, 0); 384 break; 385 case ds_1337: 386 case ds_1339: 387 case ds_1341: 388 case ds_3231: 389 regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS, 390 DS1337_BIT_OSF, 0); 391 break; 392 case ds_1340: 393 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG, 394 DS1340_BIT_OSF, 0); 395 break; 396 case ds_1388: 397 regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG, 398 DS1388_BIT_OSF, 0); 399 break; 400 case mcp794xx: 401 /* 402 * these bits were cleared when preparing the date/time 403 * values and need to be set again before writing the 404 * regsfer out to the device. 405 */ 406 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST; 407 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN; 408 break; 409 default: 410 break; 411 } 412 413 dev_dbg(dev, "%s: %7ph\n", "write", regs); 414 415 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs, 416 sizeof(regs)); 417 if (result) { 418 dev_err(dev, "%s error %d\n", "write", result); 419 return result; 420 } 421 422 if (ds1307->type == rx_8130) { 423 /* clear Voltage Loss Flag as data is available now */ 424 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG, 425 ~(u8)RX8130_REG_FLAG_VLF); 426 if (result) { 427 dev_err(dev, "%s error %d\n", "write", result); 428 return result; 429 } 430 } 431 432 return 0; 433 } 434 435 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) 436 { 437 struct ds1307 *ds1307 = dev_get_drvdata(dev); 438 int ret; 439 u8 regs[9]; 440 441 /* read all ALARM1, ALARM2, and status registers at once */ 442 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, 443 regs, sizeof(regs)); 444 if (ret) { 445 dev_err(dev, "%s error %d\n", "alarm read", ret); 446 return ret; 447 } 448 449 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read", 450 ®s[0], ®s[4], ®s[7]); 451 452 /* 453 * report alarm time (ALARM1); assume 24 hour and day-of-month modes, 454 * and that all four fields are checked matches 455 */ 456 t->time.tm_sec = bcd2bin(regs[0] & 0x7f); 457 t->time.tm_min = bcd2bin(regs[1] & 0x7f); 458 t->time.tm_hour = bcd2bin(regs[2] & 0x3f); 459 t->time.tm_mday = bcd2bin(regs[3] & 0x3f); 460 461 /* ... and status */ 462 t->enabled = !!(regs[7] & DS1337_BIT_A1IE); 463 t->pending = !!(regs[8] & DS1337_BIT_A1I); 464 465 dev_dbg(dev, "%s secs=%d, mins=%d, " 466 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 467 "alarm read", t->time.tm_sec, t->time.tm_min, 468 t->time.tm_hour, t->time.tm_mday, 469 t->enabled, t->pending); 470 471 return 0; 472 } 473 474 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) 475 { 476 struct ds1307 *ds1307 = dev_get_drvdata(dev); 477 unsigned char regs[9]; 478 u8 control, status; 479 int ret; 480 481 dev_dbg(dev, "%s secs=%d, mins=%d, " 482 "hours=%d, mday=%d, enabled=%d, pending=%d\n", 483 "alarm set", t->time.tm_sec, t->time.tm_min, 484 t->time.tm_hour, t->time.tm_mday, 485 t->enabled, t->pending); 486 487 /* read current status of both alarms and the chip */ 488 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 489 sizeof(regs)); 490 if (ret) { 491 dev_err(dev, "%s error %d\n", "alarm write", ret); 492 return ret; 493 } 494 control = regs[7]; 495 status = regs[8]; 496 497 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)", 498 ®s[0], ®s[4], control, status); 499 500 /* set ALARM1, using 24 hour and day-of-month modes */ 501 regs[0] = bin2bcd(t->time.tm_sec); 502 regs[1] = bin2bcd(t->time.tm_min); 503 regs[2] = bin2bcd(t->time.tm_hour); 504 regs[3] = bin2bcd(t->time.tm_mday); 505 506 /* set ALARM2 to non-garbage */ 507 regs[4] = 0; 508 regs[5] = 0; 509 regs[6] = 0; 510 511 /* disable alarms */ 512 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); 513 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); 514 515 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, 516 sizeof(regs)); 517 if (ret) { 518 dev_err(dev, "can't set alarm time\n"); 519 return ret; 520 } 521 522 /* optionally enable ALARM1 */ 523 if (t->enabled) { 524 dev_dbg(dev, "alarm IRQ armed\n"); 525 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ 526 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]); 527 } 528 529 return 0; 530 } 531 532 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) 533 { 534 struct ds1307 *ds1307 = dev_get_drvdata(dev); 535 536 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 537 DS1337_BIT_A1IE, 538 enabled ? DS1337_BIT_A1IE : 0); 539 } 540 541 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode) 542 { 543 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE : 544 DS1307_TRICKLE_CHARGER_NO_DIODE; 545 546 setup |= DS13XX_TRICKLE_CHARGER_MAGIC; 547 548 switch (ohms) { 549 case 250: 550 setup |= DS1307_TRICKLE_CHARGER_250_OHM; 551 break; 552 case 2000: 553 setup |= DS1307_TRICKLE_CHARGER_2K_OHM; 554 break; 555 case 4000: 556 setup |= DS1307_TRICKLE_CHARGER_4K_OHM; 557 break; 558 default: 559 dev_warn(ds1307->dev, 560 "Unsupported ohm value %u in dt\n", ohms); 561 return 0; 562 } 563 return setup; 564 } 565 566 static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode) 567 { 568 /* make sure that the backup battery is enabled */ 569 u8 setup = RX8130_REG_CONTROL1_INIEN; 570 if (diode) 571 setup |= RX8130_REG_CONTROL1_CHGEN; 572 573 return setup; 574 } 575 576 static irqreturn_t rx8130_irq(int irq, void *dev_id) 577 { 578 struct ds1307 *ds1307 = dev_id; 579 u8 ctl[3]; 580 int ret; 581 582 guard(rtc_ops)(ds1307->rtc); 583 584 /* Read control registers. */ 585 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 586 sizeof(ctl)); 587 if (ret < 0) 588 return IRQ_HANDLED; 589 590 if (!(ctl[1] & RX8130_REG_FLAG_AF)) 591 return IRQ_HANDLED; 592 593 ctl[1] &= ~RX8130_REG_FLAG_AF; 594 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 595 596 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 597 sizeof(ctl)); 598 if (ret < 0) 599 return IRQ_HANDLED; 600 601 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 602 603 return IRQ_HANDLED; 604 } 605 606 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t) 607 { 608 struct ds1307 *ds1307 = dev_get_drvdata(dev); 609 u8 ald[3], ctl[3]; 610 int ret; 611 612 /* Read alarm registers. */ 613 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 614 sizeof(ald)); 615 if (ret < 0) 616 return ret; 617 618 /* Read control registers. */ 619 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 620 sizeof(ctl)); 621 if (ret < 0) 622 return ret; 623 624 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE); 625 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF); 626 627 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 628 t->time.tm_sec = -1; 629 t->time.tm_min = bcd2bin(ald[0] & 0x7f); 630 t->time.tm_hour = bcd2bin(ald[1] & 0x7f); 631 t->time.tm_wday = -1; 632 t->time.tm_mday = bcd2bin(ald[2] & 0x7f); 633 t->time.tm_mon = -1; 634 t->time.tm_year = -1; 635 t->time.tm_yday = -1; 636 t->time.tm_isdst = -1; 637 638 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n", 639 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 640 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled); 641 642 return 0; 643 } 644 645 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t) 646 { 647 struct ds1307 *ds1307 = dev_get_drvdata(dev); 648 u8 ald[3], ctl[3]; 649 int ret; 650 651 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 652 "enabled=%d pending=%d\n", __func__, 653 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 654 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 655 t->enabled, t->pending); 656 657 /* Read control registers. */ 658 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 659 sizeof(ctl)); 660 if (ret < 0) 661 return ret; 662 663 ctl[0] |= RX8130_REG_EXTENSION_WADA; 664 ctl[1] &= ~RX8130_REG_FLAG_AF; 665 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 666 667 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 668 sizeof(ctl)); 669 if (ret < 0) 670 return ret; 671 672 /* Hardware alarm precision is 1 minute! */ 673 ald[0] = bin2bcd(t->time.tm_min); 674 ald[1] = bin2bcd(t->time.tm_hour); 675 ald[2] = bin2bcd(t->time.tm_mday); 676 677 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 678 sizeof(ald)); 679 if (ret < 0) 680 return ret; 681 682 if (!t->enabled) 683 return 0; 684 685 ctl[2] |= RX8130_REG_CONTROL0_AIE; 686 687 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]); 688 } 689 690 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled) 691 { 692 struct ds1307 *ds1307 = dev_get_drvdata(dev); 693 int ret, reg; 694 695 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®); 696 if (ret < 0) 697 return ret; 698 699 if (enabled) 700 reg |= RX8130_REG_CONTROL0_AIE; 701 else 702 reg &= ~RX8130_REG_CONTROL0_AIE; 703 704 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg); 705 } 706 707 static irqreturn_t mcp794xx_irq(int irq, void *dev_id) 708 { 709 struct ds1307 *ds1307 = dev_id; 710 struct mutex *lock = &ds1307->rtc->ops_lock; 711 int reg, ret; 712 713 mutex_lock(lock); 714 715 /* Check and clear alarm 0 interrupt flag. */ 716 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®); 717 if (ret) 718 goto out; 719 if (!(reg & MCP794XX_BIT_ALMX_IF)) 720 goto out; 721 reg &= ~MCP794XX_BIT_ALMX_IF; 722 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg); 723 if (ret) 724 goto out; 725 726 /* Disable alarm 0. */ 727 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 728 MCP794XX_BIT_ALM0_EN, 0); 729 if (ret) 730 goto out; 731 732 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 733 734 out: 735 mutex_unlock(lock); 736 737 return IRQ_HANDLED; 738 } 739 740 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t) 741 { 742 struct ds1307 *ds1307 = dev_get_drvdata(dev); 743 u8 regs[10]; 744 int ret; 745 746 /* Read control and alarm 0 registers. */ 747 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 748 sizeof(regs)); 749 if (ret) 750 return ret; 751 752 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN); 753 754 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ 755 t->time.tm_sec = bcd2bin(regs[3] & 0x7f); 756 t->time.tm_min = bcd2bin(regs[4] & 0x7f); 757 t->time.tm_hour = bcd2bin(regs[5] & 0x3f); 758 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1; 759 t->time.tm_mday = bcd2bin(regs[7] & 0x3f); 760 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1; 761 t->time.tm_year = -1; 762 t->time.tm_yday = -1; 763 t->time.tm_isdst = -1; 764 765 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 766 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__, 767 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 768 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled, 769 !!(regs[6] & MCP794XX_BIT_ALMX_POL), 770 !!(regs[6] & MCP794XX_BIT_ALMX_IF), 771 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4); 772 773 return 0; 774 } 775 776 /* 777 * We may have a random RTC weekday, therefore calculate alarm weekday based 778 * on current weekday we read from the RTC timekeeping regs 779 */ 780 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm) 781 { 782 struct rtc_time tm_now; 783 int days_now, days_alarm, ret; 784 785 ret = ds1307_get_time(dev, &tm_now); 786 if (ret) 787 return ret; 788 789 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60); 790 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60); 791 792 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1; 793 } 794 795 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t) 796 { 797 struct ds1307 *ds1307 = dev_get_drvdata(dev); 798 unsigned char regs[10]; 799 int wday, ret; 800 801 wday = mcp794xx_alm_weekday(dev, &t->time); 802 if (wday < 0) 803 return wday; 804 805 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " 806 "enabled=%d pending=%d\n", __func__, 807 t->time.tm_sec, t->time.tm_min, t->time.tm_hour, 808 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, 809 t->enabled, t->pending); 810 811 /* Read control and alarm 0 registers. */ 812 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 813 sizeof(regs)); 814 if (ret) 815 return ret; 816 817 /* Set alarm 0, using 24-hour and day-of-month modes. */ 818 regs[3] = bin2bcd(t->time.tm_sec); 819 regs[4] = bin2bcd(t->time.tm_min); 820 regs[5] = bin2bcd(t->time.tm_hour); 821 regs[6] = wday; 822 regs[7] = bin2bcd(t->time.tm_mday); 823 regs[8] = bin2bcd(t->time.tm_mon + 1); 824 825 /* Clear the alarm 0 interrupt flag. */ 826 regs[6] &= ~MCP794XX_BIT_ALMX_IF; 827 /* Set alarm match: second, minute, hour, day, date, month. */ 828 regs[6] |= MCP794XX_MSK_ALMX_MATCH; 829 /* Disable interrupt. We will not enable until completely programmed */ 830 regs[0] &= ~MCP794XX_BIT_ALM0_EN; 831 832 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 833 sizeof(regs)); 834 if (ret) 835 return ret; 836 837 if (!t->enabled) 838 return 0; 839 regs[0] |= MCP794XX_BIT_ALM0_EN; 840 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]); 841 } 842 843 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled) 844 { 845 struct ds1307 *ds1307 = dev_get_drvdata(dev); 846 847 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, 848 MCP794XX_BIT_ALM0_EN, 849 enabled ? MCP794XX_BIT_ALM0_EN : 0); 850 } 851 852 static int m41txx_rtc_read_offset(struct device *dev, long *offset) 853 { 854 struct ds1307 *ds1307 = dev_get_drvdata(dev); 855 unsigned int ctrl_reg; 856 u8 val; 857 858 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 859 860 val = ctrl_reg & M41TXX_M_CALIBRATION; 861 862 /* check if positive */ 863 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN) 864 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB); 865 else 866 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB); 867 868 return 0; 869 } 870 871 static int m41txx_rtc_set_offset(struct device *dev, long offset) 872 { 873 struct ds1307 *ds1307 = dev_get_drvdata(dev); 874 unsigned int ctrl_reg; 875 876 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET)) 877 return -ERANGE; 878 879 if (offset >= 0) { 880 ctrl_reg = DIV_ROUND_CLOSEST(offset, 881 M41TXX_POS_OFFSET_STEP_PPB); 882 ctrl_reg |= M41TXX_BIT_CALIB_SIGN; 883 } else { 884 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset), 885 M41TXX_NEG_OFFSET_STEP_PPB); 886 } 887 888 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, 889 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN, 890 ctrl_reg); 891 } 892 893 #ifdef CONFIG_WATCHDOG_CORE 894 static int ds1388_wdt_start(struct watchdog_device *wdt_dev) 895 { 896 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 897 u8 regs[2]; 898 int ret; 899 900 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG, 901 DS1388_BIT_WF, 0); 902 if (ret) 903 return ret; 904 905 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 906 DS1388_BIT_WDE | DS1388_BIT_RST, 0); 907 if (ret) 908 return ret; 909 910 /* 911 * watchdog timeouts are measured in seconds. So ignore hundredths of 912 * seconds field. 913 */ 914 regs[0] = 0; 915 regs[1] = bin2bcd(wdt_dev->timeout); 916 917 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 918 sizeof(regs)); 919 if (ret) 920 return ret; 921 922 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 923 DS1388_BIT_WDE | DS1388_BIT_RST, 924 DS1388_BIT_WDE | DS1388_BIT_RST); 925 } 926 927 static int ds1388_wdt_stop(struct watchdog_device *wdt_dev) 928 { 929 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 930 931 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, 932 DS1388_BIT_WDE | DS1388_BIT_RST, 0); 933 } 934 935 static int ds1388_wdt_ping(struct watchdog_device *wdt_dev) 936 { 937 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 938 u8 regs[2]; 939 940 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 941 sizeof(regs)); 942 } 943 944 static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev, 945 unsigned int val) 946 { 947 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); 948 u8 regs[2]; 949 950 wdt_dev->timeout = val; 951 regs[0] = 0; 952 regs[1] = bin2bcd(wdt_dev->timeout); 953 954 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, 955 sizeof(regs)); 956 } 957 #endif 958 959 static const struct rtc_class_ops rx8130_rtc_ops = { 960 .read_time = ds1307_get_time, 961 .set_time = ds1307_set_time, 962 .read_alarm = rx8130_read_alarm, 963 .set_alarm = rx8130_set_alarm, 964 .alarm_irq_enable = rx8130_alarm_irq_enable, 965 }; 966 967 static const struct rtc_class_ops mcp794xx_rtc_ops = { 968 .read_time = ds1307_get_time, 969 .set_time = ds1307_set_time, 970 .read_alarm = mcp794xx_read_alarm, 971 .set_alarm = mcp794xx_set_alarm, 972 .alarm_irq_enable = mcp794xx_alarm_irq_enable, 973 }; 974 975 static const struct rtc_class_ops m41txx_rtc_ops = { 976 .read_time = ds1307_get_time, 977 .set_time = ds1307_set_time, 978 .read_alarm = ds1337_read_alarm, 979 .set_alarm = ds1337_set_alarm, 980 .alarm_irq_enable = ds1307_alarm_irq_enable, 981 .read_offset = m41txx_rtc_read_offset, 982 .set_offset = m41txx_rtc_set_offset, 983 }; 984 985 static const struct chip_desc chips[last_ds_type] = { 986 [ds_1307] = { 987 .nvram_offset = 8, 988 .nvram_size = 56, 989 }, 990 [ds_1308] = { 991 .nvram_offset = 8, 992 .nvram_size = 56, 993 }, 994 [ds_1337] = { 995 .alarm = 1, 996 .century_reg = DS1307_REG_MONTH, 997 .century_bit = DS1337_BIT_CENTURY, 998 }, 999 [ds_1338] = { 1000 .nvram_offset = 8, 1001 .nvram_size = 56, 1002 }, 1003 [ds_1339] = { 1004 .alarm = 1, 1005 .century_reg = DS1307_REG_MONTH, 1006 .century_bit = DS1337_BIT_CENTURY, 1007 .bbsqi_bit = DS1339_BIT_BBSQI, 1008 .trickle_charger_reg = 0x10, 1009 .do_trickle_setup = &do_trickle_setup_ds1339, 1010 .requires_trickle_resistor = true, 1011 .charge_default = true, 1012 }, 1013 [ds_1340] = { 1014 .century_reg = DS1307_REG_HOUR, 1015 .century_enable_bit = DS1340_BIT_CENTURY_EN, 1016 .century_bit = DS1340_BIT_CENTURY, 1017 .do_trickle_setup = &do_trickle_setup_ds1339, 1018 .trickle_charger_reg = 0x08, 1019 .requires_trickle_resistor = true, 1020 .charge_default = true, 1021 }, 1022 [ds_1341] = { 1023 .century_reg = DS1307_REG_MONTH, 1024 .century_bit = DS1337_BIT_CENTURY, 1025 }, 1026 [ds_1388] = { 1027 .offset = 1, 1028 .trickle_charger_reg = 0x0a, 1029 }, 1030 [ds_3231] = { 1031 .alarm = 1, 1032 .century_reg = DS1307_REG_MONTH, 1033 .century_bit = DS1337_BIT_CENTURY, 1034 .bbsqi_bit = DS3231_BIT_BBSQW, 1035 }, 1036 [rx_8130] = { 1037 .alarm = 1, 1038 /* this is battery backed SRAM */ 1039 .nvram_offset = 0x20, 1040 .nvram_size = 4, /* 32bit (4 word x 8 bit) */ 1041 .offset = 0x10, 1042 .irq_handler = rx8130_irq, 1043 .rtc_ops = &rx8130_rtc_ops, 1044 .trickle_charger_reg = RX8130_REG_CONTROL1, 1045 .do_trickle_setup = &do_trickle_setup_rx8130, 1046 }, 1047 [m41t0] = { 1048 .rtc_ops = &m41txx_rtc_ops, 1049 }, 1050 [m41t00] = { 1051 .rtc_ops = &m41txx_rtc_ops, 1052 }, 1053 [m41t11] = { 1054 /* this is battery backed SRAM */ 1055 .nvram_offset = 8, 1056 .nvram_size = 56, 1057 .rtc_ops = &m41txx_rtc_ops, 1058 }, 1059 [mcp794xx] = { 1060 .alarm = 1, 1061 /* this is battery backed SRAM */ 1062 .nvram_offset = 0x20, 1063 .nvram_size = 0x40, 1064 .irq_handler = mcp794xx_irq, 1065 .rtc_ops = &mcp794xx_rtc_ops, 1066 }, 1067 }; 1068 1069 static const struct i2c_device_id ds1307_id[] = { 1070 { .name = "ds1307", .driver_data = ds_1307 }, 1071 { .name = "ds1308", .driver_data = ds_1308 }, 1072 { .name = "ds1337", .driver_data = ds_1337 }, 1073 { .name = "ds1338", .driver_data = ds_1338 }, 1074 { .name = "ds1339", .driver_data = ds_1339 }, 1075 { .name = "ds1388", .driver_data = ds_1388 }, 1076 { .name = "ds1340", .driver_data = ds_1340 }, 1077 { .name = "ds1341", .driver_data = ds_1341 }, 1078 { .name = "ds3231", .driver_data = ds_3231 }, 1079 { .name = "m41t0", .driver_data = m41t0 }, 1080 { .name = "m41t00", .driver_data = m41t00 }, 1081 { .name = "m41t11", .driver_data = m41t11 }, 1082 { .name = "mcp7940x", .driver_data = mcp794xx }, 1083 { .name = "mcp7941x", .driver_data = mcp794xx }, 1084 { .name = "pt7c4338", .driver_data = ds_1307 }, 1085 { .name = "rx8025", .driver_data = rx_8025 }, 1086 { .name = "isl12057", .driver_data = ds_1337 }, 1087 { .name = "rx8130", .driver_data = rx_8130 }, 1088 { } 1089 }; 1090 MODULE_DEVICE_TABLE(i2c, ds1307_id); 1091 1092 static const struct of_device_id ds1307_of_match[] = { 1093 { 1094 .compatible = "dallas,ds1307", 1095 .data = (void *)ds_1307 1096 }, 1097 { 1098 .compatible = "dallas,ds1308", 1099 .data = (void *)ds_1308 1100 }, 1101 { 1102 .compatible = "dallas,ds1337", 1103 .data = (void *)ds_1337 1104 }, 1105 { 1106 .compatible = "dallas,ds1338", 1107 .data = (void *)ds_1338 1108 }, 1109 { 1110 .compatible = "dallas,ds1339", 1111 .data = (void *)ds_1339 1112 }, 1113 { 1114 .compatible = "dallas,ds1388", 1115 .data = (void *)ds_1388 1116 }, 1117 { 1118 .compatible = "dallas,ds1340", 1119 .data = (void *)ds_1340 1120 }, 1121 { 1122 .compatible = "dallas,ds1341", 1123 .data = (void *)ds_1341 1124 }, 1125 { 1126 .compatible = "maxim,ds3231", 1127 .data = (void *)ds_3231 1128 }, 1129 { 1130 .compatible = "st,m41t0", 1131 .data = (void *)m41t0 1132 }, 1133 { 1134 .compatible = "st,m41t00", 1135 .data = (void *)m41t00 1136 }, 1137 { 1138 .compatible = "st,m41t11", 1139 .data = (void *)m41t11 1140 }, 1141 { 1142 .compatible = "microchip,mcp7940x", 1143 .data = (void *)mcp794xx 1144 }, 1145 { 1146 .compatible = "microchip,mcp7941x", 1147 .data = (void *)mcp794xx 1148 }, 1149 { 1150 .compatible = "pericom,pt7c4338", 1151 .data = (void *)ds_1307 1152 }, 1153 { 1154 .compatible = "epson,rx8025", 1155 .data = (void *)rx_8025 1156 }, 1157 { 1158 .compatible = "isil,isl12057", 1159 .data = (void *)ds_1337 1160 }, 1161 { 1162 .compatible = "epson,rx8130", 1163 .data = (void *)rx_8130 1164 }, 1165 { } 1166 }; 1167 MODULE_DEVICE_TABLE(of, ds1307_of_match); 1168 1169 /* 1170 * The ds1337 and ds1339 both have two alarms, but we only use the first 1171 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm 1172 * signal; ds1339 chips have only one alarm signal. 1173 */ 1174 static irqreturn_t ds1307_irq(int irq, void *dev_id) 1175 { 1176 struct ds1307 *ds1307 = dev_id; 1177 struct mutex *lock = &ds1307->rtc->ops_lock; 1178 int stat, ret; 1179 1180 mutex_lock(lock); 1181 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat); 1182 if (ret) 1183 goto out; 1184 1185 if (stat & DS1337_BIT_A1I) { 1186 stat &= ~DS1337_BIT_A1I; 1187 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat); 1188 1189 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1190 DS1337_BIT_A1IE, 0); 1191 if (ret) 1192 goto out; 1193 1194 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); 1195 } 1196 1197 out: 1198 mutex_unlock(lock); 1199 1200 return IRQ_HANDLED; 1201 } 1202 1203 /*----------------------------------------------------------------------*/ 1204 1205 static const struct rtc_class_ops ds13xx_rtc_ops = { 1206 .read_time = ds1307_get_time, 1207 .set_time = ds1307_set_time, 1208 .read_alarm = ds1337_read_alarm, 1209 .set_alarm = ds1337_set_alarm, 1210 .alarm_irq_enable = ds1307_alarm_irq_enable, 1211 }; 1212 1213 static ssize_t frequency_test_store(struct device *dev, 1214 struct device_attribute *attr, 1215 const char *buf, size_t count) 1216 { 1217 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1218 bool freq_test_en; 1219 int ret; 1220 1221 ret = kstrtobool(buf, &freq_test_en); 1222 if (ret) { 1223 dev_err(dev, "Failed to store RTC Frequency Test attribute\n"); 1224 return ret; 1225 } 1226 1227 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT, 1228 freq_test_en ? M41TXX_BIT_FT : 0); 1229 1230 return count; 1231 } 1232 1233 static ssize_t frequency_test_show(struct device *dev, 1234 struct device_attribute *attr, 1235 char *buf) 1236 { 1237 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent); 1238 unsigned int ctrl_reg; 1239 1240 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg); 1241 1242 return sysfs_emit(buf, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" : "off\n"); 1243 } 1244 1245 static DEVICE_ATTR_RW(frequency_test); 1246 1247 static struct attribute *rtc_freq_test_attrs[] = { 1248 &dev_attr_frequency_test.attr, 1249 NULL, 1250 }; 1251 1252 static const struct attribute_group rtc_freq_test_attr_group = { 1253 .attrs = rtc_freq_test_attrs, 1254 }; 1255 1256 static int ds1307_add_frequency_test(struct ds1307 *ds1307) 1257 { 1258 int err; 1259 1260 switch (ds1307->type) { 1261 case m41t0: 1262 case m41t00: 1263 case m41t11: 1264 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group); 1265 if (err) 1266 return err; 1267 break; 1268 default: 1269 break; 1270 } 1271 1272 return 0; 1273 } 1274 1275 /*----------------------------------------------------------------------*/ 1276 1277 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val, 1278 size_t bytes) 1279 { 1280 struct ds1307 *ds1307 = priv; 1281 const struct chip_desc *chip = &chips[ds1307->type]; 1282 1283 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset, 1284 val, bytes); 1285 } 1286 1287 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val, 1288 size_t bytes) 1289 { 1290 struct ds1307 *ds1307 = priv; 1291 const struct chip_desc *chip = &chips[ds1307->type]; 1292 1293 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset, 1294 val, bytes); 1295 } 1296 1297 /*----------------------------------------------------------------------*/ 1298 1299 static u8 ds1307_trickle_init(struct ds1307 *ds1307, 1300 const struct chip_desc *chip) 1301 { 1302 u32 ohms, chargeable; 1303 bool diode = chip->charge_default; 1304 1305 if (!chip->do_trickle_setup) 1306 return 0; 1307 1308 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms", 1309 &ohms) && chip->requires_trickle_resistor) 1310 return 0; 1311 1312 /* aux-voltage-chargeable takes precedence over the deprecated 1313 * trickle-diode-disable 1314 */ 1315 if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable", 1316 &chargeable)) { 1317 switch (chargeable) { 1318 case 0: 1319 diode = false; 1320 break; 1321 case 1: 1322 diode = true; 1323 break; 1324 default: 1325 dev_warn(ds1307->dev, 1326 "unsupported aux-voltage-chargeable value\n"); 1327 break; 1328 } 1329 } else if (device_property_read_bool(ds1307->dev, 1330 "trickle-diode-disable")) { 1331 diode = false; 1332 } 1333 1334 return chip->do_trickle_setup(ds1307, ohms, diode); 1335 } 1336 1337 /*----------------------------------------------------------------------*/ 1338 1339 #if IS_REACHABLE(CONFIG_HWMON) 1340 1341 /* 1342 * Temperature sensor support for ds3231 devices. 1343 */ 1344 1345 #define DS3231_REG_TEMPERATURE 0x11 1346 1347 /* 1348 * A user-initiated temperature conversion is not started by this function, 1349 * so the temperature is updated once every 64 seconds. 1350 */ 1351 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC) 1352 { 1353 struct ds1307 *ds1307 = dev_get_drvdata(dev); 1354 u8 temp_buf[2]; 1355 s16 temp; 1356 int ret; 1357 1358 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE, 1359 temp_buf, sizeof(temp_buf)); 1360 if (ret) 1361 return ret; 1362 /* 1363 * Temperature is represented as a 10-bit code with a resolution of 1364 * 0.25 degree celsius and encoded in two's complement format. 1365 */ 1366 temp = (temp_buf[0] << 8) | temp_buf[1]; 1367 temp >>= 6; 1368 *mC = temp * 250; 1369 1370 return 0; 1371 } 1372 1373 static ssize_t ds3231_hwmon_show_temp(struct device *dev, 1374 struct device_attribute *attr, char *buf) 1375 { 1376 int ret; 1377 s32 temp; 1378 1379 ret = ds3231_hwmon_read_temp(dev, &temp); 1380 if (ret) 1381 return ret; 1382 1383 return sysfs_emit(buf, "%d\n", temp); 1384 } 1385 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp, 1386 NULL, 0); 1387 1388 static struct attribute *ds3231_hwmon_attrs[] = { 1389 &sensor_dev_attr_temp1_input.dev_attr.attr, 1390 NULL, 1391 }; 1392 ATTRIBUTE_GROUPS(ds3231_hwmon); 1393 1394 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1395 { 1396 struct device *dev; 1397 1398 if (ds1307->type != ds_3231) 1399 return; 1400 1401 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name, 1402 ds1307, 1403 ds3231_hwmon_groups); 1404 if (IS_ERR(dev)) { 1405 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n", 1406 PTR_ERR(dev)); 1407 } 1408 } 1409 1410 #else 1411 1412 static void ds1307_hwmon_register(struct ds1307 *ds1307) 1413 { 1414 } 1415 1416 #endif /* IS_REACHABLE(CONFIG_HWMON) */ 1417 1418 /*----------------------------------------------------------------------*/ 1419 1420 /* 1421 * Square-wave output support for DS3231 1422 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf 1423 */ 1424 #ifdef CONFIG_COMMON_CLK 1425 1426 enum { 1427 DS3231_CLK_SQW = 0, 1428 DS3231_CLK_32KHZ, 1429 }; 1430 1431 #define clk_sqw_to_ds1307(clk) \ 1432 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW]) 1433 #define clk_32khz_to_ds1307(clk) \ 1434 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ]) 1435 1436 static int ds3231_clk_sqw_rates[] = { 1437 1, 1438 1024, 1439 4096, 1440 8192, 1441 }; 1442 1443 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value) 1444 { 1445 struct mutex *lock = &ds1307->rtc->ops_lock; 1446 int ret; 1447 1448 mutex_lock(lock); 1449 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, 1450 mask, value); 1451 mutex_unlock(lock); 1452 1453 return ret; 1454 } 1455 1456 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw, 1457 unsigned long parent_rate) 1458 { 1459 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1460 int control, ret; 1461 int rate_sel = 0; 1462 1463 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1464 if (ret) 1465 return ret; 1466 if (control & DS1337_BIT_RS1) 1467 rate_sel += 1; 1468 if (control & DS1337_BIT_RS2) 1469 rate_sel += 2; 1470 1471 return ds3231_clk_sqw_rates[rate_sel]; 1472 } 1473 1474 static int ds3231_clk_sqw_determine_rate(struct clk_hw *hw, 1475 struct clk_rate_request *req) 1476 { 1477 int i; 1478 1479 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) { 1480 if (ds3231_clk_sqw_rates[i] <= req->rate) { 1481 req->rate = ds3231_clk_sqw_rates[i]; 1482 1483 return 0; 1484 } 1485 } 1486 1487 req->rate = ds3231_clk_sqw_rates[ARRAY_SIZE(ds3231_clk_sqw_rates) - 1]; 1488 1489 return 0; 1490 } 1491 1492 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate, 1493 unsigned long parent_rate) 1494 { 1495 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1496 int control = 0; 1497 int rate_sel; 1498 1499 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates); 1500 rate_sel++) { 1501 if (ds3231_clk_sqw_rates[rate_sel] == rate) 1502 break; 1503 } 1504 1505 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates)) 1506 return -EINVAL; 1507 1508 if (rate_sel & 1) 1509 control |= DS1337_BIT_RS1; 1510 if (rate_sel & 2) 1511 control |= DS1337_BIT_RS2; 1512 1513 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2, 1514 control); 1515 } 1516 1517 static int ds3231_clk_sqw_prepare(struct clk_hw *hw) 1518 { 1519 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1520 1521 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0); 1522 } 1523 1524 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw) 1525 { 1526 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1527 1528 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN); 1529 } 1530 1531 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw) 1532 { 1533 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1534 int control, ret; 1535 1536 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); 1537 if (ret) 1538 return ret; 1539 1540 return !(control & DS1337_BIT_INTCN); 1541 } 1542 1543 static const struct clk_ops ds3231_clk_sqw_ops = { 1544 .prepare = ds3231_clk_sqw_prepare, 1545 .unprepare = ds3231_clk_sqw_unprepare, 1546 .is_prepared = ds3231_clk_sqw_is_prepared, 1547 .recalc_rate = ds3231_clk_sqw_recalc_rate, 1548 .determine_rate = ds3231_clk_sqw_determine_rate, 1549 .set_rate = ds3231_clk_sqw_set_rate, 1550 }; 1551 1552 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw, 1553 unsigned long parent_rate) 1554 { 1555 return 32768; 1556 } 1557 1558 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable) 1559 { 1560 struct mutex *lock = &ds1307->rtc->ops_lock; 1561 int ret; 1562 1563 mutex_lock(lock); 1564 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS, 1565 DS3231_BIT_EN32KHZ, 1566 enable ? DS3231_BIT_EN32KHZ : 0); 1567 mutex_unlock(lock); 1568 1569 return ret; 1570 } 1571 1572 static int ds3231_clk_32khz_prepare(struct clk_hw *hw) 1573 { 1574 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1575 1576 return ds3231_clk_32khz_control(ds1307, true); 1577 } 1578 1579 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw) 1580 { 1581 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1582 1583 ds3231_clk_32khz_control(ds1307, false); 1584 } 1585 1586 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw) 1587 { 1588 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); 1589 int status, ret; 1590 1591 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status); 1592 if (ret) 1593 return ret; 1594 1595 return !!(status & DS3231_BIT_EN32KHZ); 1596 } 1597 1598 static const struct clk_ops ds3231_clk_32khz_ops = { 1599 .prepare = ds3231_clk_32khz_prepare, 1600 .unprepare = ds3231_clk_32khz_unprepare, 1601 .is_prepared = ds3231_clk_32khz_is_prepared, 1602 .recalc_rate = ds3231_clk_32khz_recalc_rate, 1603 }; 1604 1605 static const char *ds3231_clks_names[] = { 1606 [DS3231_CLK_SQW] = "ds3231_clk_sqw", 1607 [DS3231_CLK_32KHZ] = "ds3231_clk_32khz", 1608 }; 1609 1610 static struct clk_init_data ds3231_clks_init[] = { 1611 [DS3231_CLK_SQW] = { 1612 .ops = &ds3231_clk_sqw_ops, 1613 }, 1614 [DS3231_CLK_32KHZ] = { 1615 .ops = &ds3231_clk_32khz_ops, 1616 }, 1617 }; 1618 1619 static int ds3231_clks_register(struct ds1307 *ds1307) 1620 { 1621 struct device_node *node = ds1307->dev->of_node; 1622 struct clk_onecell_data *onecell; 1623 int i; 1624 1625 onecell = devm_kzalloc_obj(ds1307->dev, *onecell); 1626 if (!onecell) 1627 return -ENOMEM; 1628 1629 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init); 1630 onecell->clks = devm_kzalloc_objs(ds1307->dev, onecell->clks[0], 1631 onecell->clk_num); 1632 if (!onecell->clks) 1633 return -ENOMEM; 1634 1635 /* optional override of the clockname */ 1636 device_property_read_string_array(ds1307->dev, "clock-output-names", 1637 ds3231_clks_names, 1638 ARRAY_SIZE(ds3231_clks_names)); 1639 1640 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) { 1641 struct clk_init_data init = ds3231_clks_init[i]; 1642 1643 /* 1644 * Interrupt signal due to alarm conditions and square-wave 1645 * output share same pin, so don't initialize both. 1646 */ 1647 if (i == DS3231_CLK_SQW && test_bit(RTC_FEATURE_ALARM, ds1307->rtc->features)) 1648 continue; 1649 1650 init.name = ds3231_clks_names[i]; 1651 ds1307->clks[i].init = &init; 1652 1653 onecell->clks[i] = devm_clk_register(ds1307->dev, 1654 &ds1307->clks[i]); 1655 if (IS_ERR(onecell->clks[i])) 1656 return PTR_ERR(onecell->clks[i]); 1657 } 1658 1659 if (node) 1660 of_clk_add_provider(node, of_clk_src_onecell_get, onecell); 1661 1662 return 0; 1663 } 1664 1665 /* ds1307 RTC clock output support */ 1666 static unsigned long ds1307_clk_rates[] = { 1667 1, 1668 4096, 1669 8192, 1670 32768, 1671 }; 1672 1673 static unsigned long ds1307_clk_sqw_recalc_rate(struct clk_hw *hw, 1674 unsigned long parent_rate) 1675 { 1676 int ret; 1677 unsigned int rate_id; 1678 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1679 1680 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &rate_id); 1681 if (ret) 1682 return ret; 1683 1684 rate_id &= (DS1307_BIT_RS1 | DS1307_BIT_RS0); 1685 1686 return ds1307_clk_rates[rate_id]; 1687 } 1688 1689 static int ds1307_clk_sqw_determine_rate(struct clk_hw *hw, 1690 struct clk_rate_request *req) 1691 { 1692 int i; 1693 1694 for (i = 0; i < ARRAY_SIZE(ds1307_clk_rates); i++) { 1695 if (req->rate <= ds1307_clk_rates[i]) { 1696 req->rate = ds1307_clk_rates[i]; 1697 return 0; 1698 } 1699 } 1700 1701 /* Default rate 1Hz */ 1702 req->rate = ds1307_clk_rates[0]; 1703 1704 return 0; 1705 } 1706 1707 static int ds1307_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate, 1708 unsigned long parent_rate) 1709 { 1710 int id, ret; 1711 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1712 1713 for (id = 0; id < ARRAY_SIZE(ds1307_clk_rates); id++) { 1714 if (ds1307_clk_rates[id] == rate) 1715 break; 1716 } 1717 1718 if (id >= ARRAY_SIZE(ds1307_clk_rates)) 1719 return -EINVAL; 1720 1721 ret = regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL, 1722 DS1307_BIT_RS0 | DS1307_BIT_RS1, id); 1723 1724 return ret; 1725 } 1726 1727 static int ds1307_clk_sqw_prepare(struct clk_hw *hw) 1728 { 1729 int ret; 1730 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1731 1732 ret = regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL, 1733 DS1307_BIT_SQWE, DS1307_BIT_SQWE); 1734 1735 return ret; 1736 } 1737 1738 static void ds1307_clk_sqw_unprepare(struct clk_hw *hw) 1739 { 1740 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1741 1742 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL, 1743 DS1307_BIT_SQWE, ~DS1307_BIT_SQWE); 1744 } 1745 1746 static int ds1307_clk_sqw_is_prepared(struct clk_hw *hw) 1747 { 1748 int ret; 1749 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); 1750 unsigned int status; 1751 1752 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &status); 1753 if (ret) 1754 return ret; 1755 1756 return !!(status & DS1307_BIT_SQWE); 1757 } 1758 1759 static const struct clk_ops ds1307_clk_sqw_ops = { 1760 .prepare = ds1307_clk_sqw_prepare, 1761 .unprepare = ds1307_clk_sqw_unprepare, 1762 .is_prepared = ds1307_clk_sqw_is_prepared, 1763 .recalc_rate = ds1307_clk_sqw_recalc_rate, 1764 .set_rate = ds1307_clk_sqw_set_rate, 1765 .determine_rate = ds1307_clk_sqw_determine_rate, 1766 }; 1767 1768 static int rtc_ds1307_clks_register(struct ds1307 *ds1307) 1769 { 1770 struct device_node *node = ds1307->dev->of_node; 1771 struct clk *clk; 1772 struct clk_init_data init = {0}; 1773 1774 init.name = "ds1307_clk_sqw"; 1775 init.ops = &ds1307_clk_sqw_ops; 1776 1777 ds1307->clks[0].init = &init; 1778 1779 /* Register the clock with CCF */ 1780 clk = devm_clk_register(ds1307->dev, &ds1307->clks[0]); 1781 if (IS_ERR(clk)) 1782 return PTR_ERR(clk); 1783 1784 if (node) 1785 of_clk_add_provider(node, of_clk_src_simple_get, clk); 1786 1787 return 0; 1788 } 1789 1790 static void ds1307_clks_register(struct ds1307 *ds1307) 1791 { 1792 int ret; 1793 1794 switch (ds1307->type) { 1795 case ds_3231: 1796 ret = ds3231_clks_register(ds1307); 1797 break; 1798 1799 case ds_1307: 1800 ret = rtc_ds1307_clks_register(ds1307); 1801 break; 1802 1803 default: 1804 return; 1805 } 1806 1807 if (ret) { 1808 dev_warn(ds1307->dev, "unable to register clock device %d\n", 1809 ret); 1810 } 1811 1812 } 1813 1814 #else 1815 1816 static void ds1307_clks_register(struct ds1307 *ds1307) 1817 { 1818 } 1819 1820 #endif /* CONFIG_COMMON_CLK */ 1821 1822 #ifdef CONFIG_WATCHDOG_CORE 1823 static const struct watchdog_info ds1388_wdt_info = { 1824 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, 1825 .identity = "DS1388 watchdog", 1826 }; 1827 1828 static const struct watchdog_ops ds1388_wdt_ops = { 1829 .owner = THIS_MODULE, 1830 .start = ds1388_wdt_start, 1831 .stop = ds1388_wdt_stop, 1832 .ping = ds1388_wdt_ping, 1833 .set_timeout = ds1388_wdt_set_timeout, 1834 1835 }; 1836 1837 static void ds1307_wdt_register(struct ds1307 *ds1307) 1838 { 1839 struct watchdog_device *wdt; 1840 int err; 1841 int val; 1842 1843 if (ds1307->type != ds_1388) 1844 return; 1845 1846 wdt = devm_kzalloc_obj(ds1307->dev, *wdt); 1847 if (!wdt) 1848 return; 1849 1850 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val); 1851 if (!err && val & DS1388_BIT_WF) 1852 wdt->bootstatus = WDIOF_CARDRESET; 1853 1854 wdt->info = &ds1388_wdt_info; 1855 wdt->ops = &ds1388_wdt_ops; 1856 wdt->timeout = 99; 1857 wdt->max_timeout = 99; 1858 wdt->min_timeout = 1; 1859 1860 watchdog_init_timeout(wdt, 0, ds1307->dev); 1861 watchdog_set_drvdata(wdt, ds1307); 1862 devm_watchdog_register_device(ds1307->dev, wdt); 1863 } 1864 #else 1865 static void ds1307_wdt_register(struct ds1307 *ds1307) 1866 { 1867 } 1868 #endif /* CONFIG_WATCHDOG_CORE */ 1869 1870 static const struct regmap_config regmap_config = { 1871 .reg_bits = 8, 1872 .val_bits = 8, 1873 }; 1874 1875 static int ds1307_probe(struct i2c_client *client) 1876 { 1877 const struct i2c_device_id *id = i2c_client_get_device_id(client); 1878 struct ds1307 *ds1307; 1879 const void *match; 1880 int err = -ENODEV; 1881 int tmp; 1882 const struct chip_desc *chip; 1883 bool want_irq; 1884 bool ds1307_can_wakeup_device = false; 1885 unsigned char regs[8]; 1886 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev); 1887 u8 trickle_charger_setup = 0; 1888 1889 ds1307 = devm_kzalloc_obj(&client->dev, struct ds1307); 1890 if (!ds1307) 1891 return -ENOMEM; 1892 1893 ds1307->dev = &client->dev; 1894 ds1307->name = client->name; 1895 1896 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config); 1897 if (IS_ERR(ds1307->regmap)) { 1898 dev_err(ds1307->dev, "regmap allocation failed\n"); 1899 return PTR_ERR(ds1307->regmap); 1900 } 1901 1902 i2c_set_clientdata(client, ds1307); 1903 1904 match = device_get_match_data(&client->dev); 1905 if (match) { 1906 ds1307->type = (uintptr_t)match; 1907 chip = &chips[ds1307->type]; 1908 } else if (id) { 1909 chip = &chips[id->driver_data]; 1910 ds1307->type = id->driver_data; 1911 } else { 1912 return -ENODEV; 1913 } 1914 1915 want_irq = client->irq > 0 && chip->alarm; 1916 1917 if (!pdata) 1918 trickle_charger_setup = ds1307_trickle_init(ds1307, chip); 1919 else if (pdata->trickle_charger_setup) 1920 trickle_charger_setup = pdata->trickle_charger_setup; 1921 1922 if (trickle_charger_setup && chip->trickle_charger_reg) { 1923 dev_dbg(ds1307->dev, 1924 "writing trickle charger info 0x%x to 0x%x\n", 1925 trickle_charger_setup, chip->trickle_charger_reg); 1926 regmap_write(ds1307->regmap, chip->trickle_charger_reg, 1927 trickle_charger_setup); 1928 } 1929 1930 /* 1931 * For devices with no IRQ directly connected to the SoC, the RTC chip 1932 * can be forced as a wakeup source by stating that explicitly in 1933 * the device's .dts file using the "wakeup-source" boolean property. 1934 * If the "wakeup-source" property is set, don't request an IRQ. 1935 * This will guarantee the 'wakealarm' sysfs entry is available on the device, 1936 * if supported by the RTC. 1937 */ 1938 if (chip->alarm && device_property_read_bool(&client->dev, "wakeup-source")) 1939 ds1307_can_wakeup_device = true; 1940 1941 switch (ds1307->type) { 1942 case ds_1337: 1943 case ds_1339: 1944 case ds_1341: 1945 case ds_3231: 1946 /* get registers that the "rtc" read below won't read... */ 1947 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL, 1948 regs, 2); 1949 if (err) { 1950 dev_dbg(ds1307->dev, "read error %d\n", err); 1951 goto exit; 1952 } 1953 1954 /* oscillator off? turn it on, so clock can tick. */ 1955 if (regs[0] & DS1337_BIT_nEOSC) 1956 regs[0] &= ~DS1337_BIT_nEOSC; 1957 1958 /* 1959 * Using IRQ or defined as wakeup-source? 1960 * Disable the square wave and both alarms. 1961 * For some variants, be sure alarms can trigger when we're 1962 * running on Vbackup (BBSQI/BBSQW) 1963 */ 1964 if (want_irq || ds1307_can_wakeup_device) 1965 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit; 1966 1967 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, 1968 regs[0]); 1969 1970 /* oscillator fault? warn */ 1971 if (regs[1] & DS1337_BIT_OSF) { 1972 dev_warn(ds1307->dev, "SET TIME!\n"); 1973 } 1974 break; 1975 1976 case rx_8025: 1977 err = regmap_bulk_read(ds1307->regmap, 1978 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2); 1979 if (err) { 1980 dev_dbg(ds1307->dev, "read error %d\n", err); 1981 goto exit; 1982 } 1983 1984 /* oscillator off? turn it on, so clock can tick. */ 1985 if (!(regs[1] & RX8025_BIT_XST)) { 1986 regs[1] |= RX8025_BIT_XST; 1987 regmap_write(ds1307->regmap, 1988 RX8025_REG_CTRL2 << 4 | 0x08, 1989 regs[1]); 1990 dev_warn(ds1307->dev, 1991 "oscillator stop detected - SET TIME!\n"); 1992 } 1993 1994 if (regs[1] & RX8025_BIT_PON) { 1995 regs[1] &= ~RX8025_BIT_PON; 1996 regmap_write(ds1307->regmap, 1997 RX8025_REG_CTRL2 << 4 | 0x08, 1998 regs[1]); 1999 dev_warn(ds1307->dev, "power-on detected\n"); 2000 } 2001 2002 if (regs[1] & RX8025_BIT_VDET) { 2003 regs[1] &= ~RX8025_BIT_VDET; 2004 regmap_write(ds1307->regmap, 2005 RX8025_REG_CTRL2 << 4 | 0x08, 2006 regs[1]); 2007 dev_warn(ds1307->dev, "voltage drop detected\n"); 2008 } 2009 2010 /* make sure we are running in 24hour mode */ 2011 if (!(regs[0] & RX8025_BIT_2412)) { 2012 u8 hour; 2013 2014 /* switch to 24 hour mode */ 2015 regmap_write(ds1307->regmap, 2016 RX8025_REG_CTRL1 << 4 | 0x08, 2017 regs[0] | RX8025_BIT_2412); 2018 2019 err = regmap_bulk_read(ds1307->regmap, 2020 RX8025_REG_CTRL1 << 4 | 0x08, 2021 regs, 2); 2022 if (err) { 2023 dev_dbg(ds1307->dev, "read error %d\n", err); 2024 goto exit; 2025 } 2026 2027 /* correct hour */ 2028 hour = bcd2bin(regs[DS1307_REG_HOUR]); 2029 if (hour == 12) 2030 hour = 0; 2031 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 2032 hour += 12; 2033 2034 regmap_write(ds1307->regmap, 2035 DS1307_REG_HOUR << 4 | 0x08, hour); 2036 } 2037 break; 2038 case ds_1388: 2039 err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp); 2040 if (err) { 2041 dev_dbg(ds1307->dev, "read error %d\n", err); 2042 goto exit; 2043 } 2044 2045 /* oscillator off? turn it on, so clock can tick. */ 2046 if (tmp & DS1388_BIT_nEOSC) { 2047 tmp &= ~DS1388_BIT_nEOSC; 2048 regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp); 2049 } 2050 break; 2051 default: 2052 break; 2053 } 2054 2055 /* read RTC registers */ 2056 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 2057 sizeof(regs)); 2058 if (err) { 2059 dev_dbg(ds1307->dev, "read error %d\n", err); 2060 goto exit; 2061 } 2062 2063 if (ds1307->type == mcp794xx && 2064 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) { 2065 regmap_write(ds1307->regmap, DS1307_REG_WDAY, 2066 regs[DS1307_REG_WDAY] | 2067 MCP794XX_BIT_VBATEN); 2068 } 2069 2070 tmp = regs[DS1307_REG_HOUR]; 2071 switch (ds1307->type) { 2072 case ds_1340: 2073 case m41t0: 2074 case m41t00: 2075 case m41t11: 2076 /* 2077 * NOTE: ignores century bits; fix before deploying 2078 * systems that will run through year 2100. 2079 */ 2080 break; 2081 case rx_8025: 2082 break; 2083 default: 2084 if (!(tmp & DS1307_BIT_12HR)) 2085 break; 2086 2087 /* 2088 * Be sure we're in 24 hour mode. Multi-master systems 2089 * take note... 2090 */ 2091 tmp = bcd2bin(tmp & 0x1f); 2092 if (tmp == 12) 2093 tmp = 0; 2094 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) 2095 tmp += 12; 2096 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR, 2097 bin2bcd(tmp)); 2098 } 2099 2100 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev); 2101 if (IS_ERR(ds1307->rtc)) 2102 return PTR_ERR(ds1307->rtc); 2103 2104 if (want_irq || ds1307_can_wakeup_device) 2105 device_set_wakeup_capable(ds1307->dev, true); 2106 else 2107 clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features); 2108 2109 if (ds1307_can_wakeup_device && !want_irq) { 2110 dev_info(ds1307->dev, 2111 "'wakeup-source' is set, request for an IRQ is disabled!\n"); 2112 /* We cannot support UIE mode if we do not have an IRQ line */ 2113 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, ds1307->rtc->features); 2114 } 2115 2116 if (want_irq) { 2117 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL, 2118 chip->irq_handler ?: ds1307_irq, 2119 IRQF_SHARED | IRQF_ONESHOT, 2120 ds1307->name, ds1307); 2121 if (err) { 2122 client->irq = 0; 2123 device_set_wakeup_capable(ds1307->dev, false); 2124 clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features); 2125 dev_err(ds1307->dev, "unable to request IRQ!\n"); 2126 } else { 2127 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq); 2128 } 2129 } 2130 2131 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops; 2132 err = ds1307_add_frequency_test(ds1307); 2133 if (err) 2134 return err; 2135 2136 err = devm_rtc_register_device(ds1307->rtc); 2137 if (err) 2138 return err; 2139 2140 if (chip->nvram_size) { 2141 struct nvmem_config nvmem_cfg = { 2142 .name = "ds1307_nvram", 2143 .word_size = 1, 2144 .stride = 1, 2145 .size = chip->nvram_size, 2146 .reg_read = ds1307_nvram_read, 2147 .reg_write = ds1307_nvram_write, 2148 .priv = ds1307, 2149 }; 2150 2151 devm_rtc_nvmem_register(ds1307->rtc, &nvmem_cfg); 2152 } 2153 2154 ds1307_hwmon_register(ds1307); 2155 ds1307_clks_register(ds1307); 2156 ds1307_wdt_register(ds1307); 2157 2158 return 0; 2159 2160 exit: 2161 return err; 2162 } 2163 2164 static struct i2c_driver ds1307_driver = { 2165 .driver = { 2166 .name = "rtc-ds1307", 2167 .of_match_table = ds1307_of_match, 2168 }, 2169 .probe = ds1307_probe, 2170 .id_table = ds1307_id, 2171 }; 2172 2173 module_i2c_driver(ds1307_driver); 2174 2175 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); 2176 MODULE_LICENSE("GPL"); 2177