1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 Oleksij Rempel <linux@rempel-privat.de> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/interrupt.h> 8 #include <linux/io.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/rtc.h> 13 14 /* Miscellaneous registers */ 15 /* Interrupt Location Register */ 16 #define HW_ILR 0x00 17 #define BM_RTCALF BIT(1) 18 #define BM_RTCCIF BIT(0) 19 20 /* Clock Control Register */ 21 #define HW_CCR 0x08 22 /* Calibration counter disable */ 23 #define BM_CCALOFF BIT(4) 24 /* Reset internal oscillator divider */ 25 #define BM_CTCRST BIT(1) 26 /* Clock Enable */ 27 #define BM_CLKEN BIT(0) 28 29 /* Counter Increment Interrupt Register */ 30 #define HW_CIIR 0x0C 31 #define BM_CIIR_IMYEAR BIT(7) 32 #define BM_CIIR_IMMON BIT(6) 33 #define BM_CIIR_IMDOY BIT(5) 34 #define BM_CIIR_IMDOW BIT(4) 35 #define BM_CIIR_IMDOM BIT(3) 36 #define BM_CIIR_IMHOUR BIT(2) 37 #define BM_CIIR_IMMIN BIT(1) 38 #define BM_CIIR_IMSEC BIT(0) 39 40 /* Alarm Mask Register */ 41 #define HW_AMR 0x10 42 #define BM_AMR_IMYEAR BIT(7) 43 #define BM_AMR_IMMON BIT(6) 44 #define BM_AMR_IMDOY BIT(5) 45 #define BM_AMR_IMDOW BIT(4) 46 #define BM_AMR_IMDOM BIT(3) 47 #define BM_AMR_IMHOUR BIT(2) 48 #define BM_AMR_IMMIN BIT(1) 49 #define BM_AMR_IMSEC BIT(0) 50 #define BM_AMR_OFF 0xff 51 52 /* Consolidated time registers */ 53 #define HW_CTIME0 0x14 54 #define BM_CTIME0_DOW_S 24 55 #define BM_CTIME0_DOW_M 0x7 56 #define BM_CTIME0_HOUR_S 16 57 #define BM_CTIME0_HOUR_M 0x1f 58 #define BM_CTIME0_MIN_S 8 59 #define BM_CTIME0_MIN_M 0x3f 60 #define BM_CTIME0_SEC_S 0 61 #define BM_CTIME0_SEC_M 0x3f 62 63 #define HW_CTIME1 0x18 64 #define BM_CTIME1_YEAR_S 16 65 #define BM_CTIME1_YEAR_M 0xfff 66 #define BM_CTIME1_MON_S 8 67 #define BM_CTIME1_MON_M 0xf 68 #define BM_CTIME1_DOM_S 0 69 #define BM_CTIME1_DOM_M 0x1f 70 71 #define HW_CTIME2 0x1C 72 #define BM_CTIME2_DOY_S 0 73 #define BM_CTIME2_DOY_M 0xfff 74 75 /* Time counter registers */ 76 #define HW_SEC 0x20 77 #define HW_MIN 0x24 78 #define HW_HOUR 0x28 79 #define HW_DOM 0x2C 80 #define HW_DOW 0x30 81 #define HW_DOY 0x34 82 #define HW_MONTH 0x38 83 #define HW_YEAR 0x3C 84 85 #define HW_CALIBRATION 0x40 86 #define BM_CALDIR_BACK BIT(17) 87 #define BM_CALVAL_M 0x1ffff 88 89 /* General purpose registers */ 90 #define HW_GPREG0 0x44 91 #define HW_GPREG1 0x48 92 #define HW_GPREG2 0x4C 93 #define HW_GPREG3 0x50 94 #define HW_GPREG4 0x54 95 96 /* Alarm register group */ 97 #define HW_ALSEC 0x60 98 #define HW_ALMIN 0x64 99 #define HW_ALHOUR 0x68 100 #define HW_ALDOM 0x6C 101 #define HW_ALDOW 0x70 102 #define HW_ALDOY 0x74 103 #define HW_ALMON 0x78 104 #define HW_ALYEAR 0x7C 105 106 struct asm9260_rtc_priv { 107 struct device *dev; 108 void __iomem *iobase; 109 struct rtc_device *rtc; 110 struct clk *clk; 111 }; 112 113 static irqreturn_t asm9260_rtc_irq(int irq, void *dev_id) 114 { 115 struct asm9260_rtc_priv *priv = dev_id; 116 u32 isr; 117 unsigned long events = 0; 118 119 guard(rtc_ops)(priv->rtc); 120 isr = ioread32(priv->iobase + HW_CIIR); 121 if (!isr) { 122 return IRQ_NONE; 123 } 124 125 iowrite32(0, priv->iobase + HW_CIIR); 126 127 events |= RTC_AF | RTC_IRQF; 128 129 rtc_update_irq(priv->rtc, 1, events); 130 131 return IRQ_HANDLED; 132 } 133 134 static int asm9260_rtc_read_time(struct device *dev, struct rtc_time *tm) 135 { 136 struct asm9260_rtc_priv *priv = dev_get_drvdata(dev); 137 u32 ctime0, ctime1, ctime2; 138 139 ctime0 = ioread32(priv->iobase + HW_CTIME0); 140 ctime1 = ioread32(priv->iobase + HW_CTIME1); 141 ctime2 = ioread32(priv->iobase + HW_CTIME2); 142 143 if (ctime1 != ioread32(priv->iobase + HW_CTIME1)) { 144 /* 145 * woops, counter flipped right now. Now we are safe 146 * to reread. 147 */ 148 ctime0 = ioread32(priv->iobase + HW_CTIME0); 149 ctime1 = ioread32(priv->iobase + HW_CTIME1); 150 ctime2 = ioread32(priv->iobase + HW_CTIME2); 151 } 152 153 tm->tm_sec = (ctime0 >> BM_CTIME0_SEC_S) & BM_CTIME0_SEC_M; 154 tm->tm_min = (ctime0 >> BM_CTIME0_MIN_S) & BM_CTIME0_MIN_M; 155 tm->tm_hour = (ctime0 >> BM_CTIME0_HOUR_S) & BM_CTIME0_HOUR_M; 156 tm->tm_wday = (ctime0 >> BM_CTIME0_DOW_S) & BM_CTIME0_DOW_M; 157 158 tm->tm_mday = (ctime1 >> BM_CTIME1_DOM_S) & BM_CTIME1_DOM_M; 159 tm->tm_mon = (ctime1 >> BM_CTIME1_MON_S) & BM_CTIME1_MON_M; 160 tm->tm_year = (ctime1 >> BM_CTIME1_YEAR_S) & BM_CTIME1_YEAR_M; 161 162 tm->tm_yday = (ctime2 >> BM_CTIME2_DOY_S) & BM_CTIME2_DOY_M; 163 164 return 0; 165 } 166 167 static int asm9260_rtc_set_time(struct device *dev, struct rtc_time *tm) 168 { 169 struct asm9260_rtc_priv *priv = dev_get_drvdata(dev); 170 171 /* 172 * make sure SEC counter will not flip other counter on write time, 173 * real value will be written at the enf of sequence. 174 */ 175 iowrite32(0, priv->iobase + HW_SEC); 176 177 iowrite32(tm->tm_year, priv->iobase + HW_YEAR); 178 iowrite32(tm->tm_mon, priv->iobase + HW_MONTH); 179 iowrite32(tm->tm_mday, priv->iobase + HW_DOM); 180 iowrite32(tm->tm_wday, priv->iobase + HW_DOW); 181 iowrite32(tm->tm_yday, priv->iobase + HW_DOY); 182 iowrite32(tm->tm_hour, priv->iobase + HW_HOUR); 183 iowrite32(tm->tm_min, priv->iobase + HW_MIN); 184 iowrite32(tm->tm_sec, priv->iobase + HW_SEC); 185 186 return 0; 187 } 188 189 static int asm9260_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 190 { 191 struct asm9260_rtc_priv *priv = dev_get_drvdata(dev); 192 193 alrm->time.tm_year = ioread32(priv->iobase + HW_ALYEAR); 194 alrm->time.tm_mon = ioread32(priv->iobase + HW_ALMON); 195 alrm->time.tm_mday = ioread32(priv->iobase + HW_ALDOM); 196 alrm->time.tm_wday = ioread32(priv->iobase + HW_ALDOW); 197 alrm->time.tm_yday = ioread32(priv->iobase + HW_ALDOY); 198 alrm->time.tm_hour = ioread32(priv->iobase + HW_ALHOUR); 199 alrm->time.tm_min = ioread32(priv->iobase + HW_ALMIN); 200 alrm->time.tm_sec = ioread32(priv->iobase + HW_ALSEC); 201 202 alrm->enabled = ioread32(priv->iobase + HW_AMR) ? 1 : 0; 203 alrm->pending = ioread32(priv->iobase + HW_CIIR) ? 1 : 0; 204 205 return rtc_valid_tm(&alrm->time); 206 } 207 208 static int asm9260_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 209 { 210 struct asm9260_rtc_priv *priv = dev_get_drvdata(dev); 211 212 iowrite32(alrm->time.tm_year, priv->iobase + HW_ALYEAR); 213 iowrite32(alrm->time.tm_mon, priv->iobase + HW_ALMON); 214 iowrite32(alrm->time.tm_mday, priv->iobase + HW_ALDOM); 215 iowrite32(alrm->time.tm_wday, priv->iobase + HW_ALDOW); 216 iowrite32(alrm->time.tm_yday, priv->iobase + HW_ALDOY); 217 iowrite32(alrm->time.tm_hour, priv->iobase + HW_ALHOUR); 218 iowrite32(alrm->time.tm_min, priv->iobase + HW_ALMIN); 219 iowrite32(alrm->time.tm_sec, priv->iobase + HW_ALSEC); 220 221 iowrite32(alrm->enabled ? 0 : BM_AMR_OFF, priv->iobase + HW_AMR); 222 223 return 0; 224 } 225 226 static int asm9260_alarm_irq_enable(struct device *dev, unsigned int enabled) 227 { 228 struct asm9260_rtc_priv *priv = dev_get_drvdata(dev); 229 230 iowrite32(enabled ? 0 : BM_AMR_OFF, priv->iobase + HW_AMR); 231 return 0; 232 } 233 234 static const struct rtc_class_ops asm9260_rtc_ops = { 235 .read_time = asm9260_rtc_read_time, 236 .set_time = asm9260_rtc_set_time, 237 .read_alarm = asm9260_rtc_read_alarm, 238 .set_alarm = asm9260_rtc_set_alarm, 239 .alarm_irq_enable = asm9260_alarm_irq_enable, 240 }; 241 242 static int asm9260_rtc_probe(struct platform_device *pdev) 243 { 244 struct asm9260_rtc_priv *priv; 245 struct device *dev = &pdev->dev; 246 int irq_alarm, ret; 247 u32 ccr; 248 249 priv = devm_kzalloc_obj(dev, struct asm9260_rtc_priv); 250 if (!priv) 251 return -ENOMEM; 252 253 priv->dev = &pdev->dev; 254 platform_set_drvdata(pdev, priv); 255 256 irq_alarm = platform_get_irq(pdev, 0); 257 if (irq_alarm < 0) 258 return irq_alarm; 259 260 priv->iobase = devm_platform_ioremap_resource(pdev, 0); 261 if (IS_ERR(priv->iobase)) 262 return PTR_ERR(priv->iobase); 263 264 priv->clk = devm_clk_get(dev, "ahb"); 265 if (IS_ERR(priv->clk)) 266 return PTR_ERR(priv->clk); 267 268 ret = clk_prepare_enable(priv->clk); 269 if (ret) { 270 dev_err(dev, "Failed to enable clk!\n"); 271 return ret; 272 } 273 274 ccr = ioread32(priv->iobase + HW_CCR); 275 /* if dev is not enabled, reset it */ 276 if ((ccr & (BM_CLKEN | BM_CTCRST)) != BM_CLKEN) { 277 iowrite32(BM_CTCRST, priv->iobase + HW_CCR); 278 ccr = 0; 279 } 280 281 iowrite32(BM_CLKEN | ccr, priv->iobase + HW_CCR); 282 iowrite32(0, priv->iobase + HW_CIIR); 283 iowrite32(BM_AMR_OFF, priv->iobase + HW_AMR); 284 285 priv->rtc = devm_rtc_device_register(dev, dev_name(dev), 286 &asm9260_rtc_ops, THIS_MODULE); 287 if (IS_ERR(priv->rtc)) { 288 ret = PTR_ERR(priv->rtc); 289 dev_err(dev, "Failed to register RTC device: %d\n", ret); 290 goto err_return; 291 } 292 293 ret = devm_request_threaded_irq(dev, irq_alarm, NULL, 294 asm9260_rtc_irq, IRQF_ONESHOT, 295 dev_name(dev), priv); 296 if (ret < 0) { 297 dev_err(dev, "can't get irq %i, err %d\n", 298 irq_alarm, ret); 299 goto err_return; 300 } 301 302 return 0; 303 304 err_return: 305 clk_disable_unprepare(priv->clk); 306 return ret; 307 } 308 309 static void asm9260_rtc_remove(struct platform_device *pdev) 310 { 311 struct asm9260_rtc_priv *priv = platform_get_drvdata(pdev); 312 313 /* Disable alarm matching */ 314 iowrite32(BM_AMR_OFF, priv->iobase + HW_AMR); 315 clk_disable_unprepare(priv->clk); 316 } 317 318 static const struct of_device_id asm9260_dt_ids[] = { 319 { .compatible = "alphascale,asm9260-rtc", }, 320 {} 321 }; 322 MODULE_DEVICE_TABLE(of, asm9260_dt_ids); 323 324 static struct platform_driver asm9260_rtc_driver = { 325 .probe = asm9260_rtc_probe, 326 .remove = asm9260_rtc_remove, 327 .driver = { 328 .name = "asm9260-rtc", 329 .of_match_table = asm9260_dt_ids, 330 }, 331 }; 332 333 module_platform_driver(asm9260_rtc_driver); 334 335 MODULE_AUTHOR("Oleksij Rempel <linux@rempel-privat.de>"); 336 MODULE_DESCRIPTION("Alphascale asm9260 SoC Realtime Clock Driver (RTC)"); 337 MODULE_LICENSE("GPL"); 338