1*b5fa9d3bSJoakim Zhang // SPDX-License-Identifier: GPL-2.0-only
2*b5fa9d3bSJoakim Zhang /*
3*b5fa9d3bSJoakim Zhang * Cix Sky1 Audio Subsystem reset controller driver
4*b5fa9d3bSJoakim Zhang *
5*b5fa9d3bSJoakim Zhang * Copyright 2026 Cix Technology Group Co., Ltd.
6*b5fa9d3bSJoakim Zhang */
7*b5fa9d3bSJoakim Zhang
8*b5fa9d3bSJoakim Zhang #include <dt-bindings/reset/cix,sky1-audss-cru.h>
9*b5fa9d3bSJoakim Zhang
10*b5fa9d3bSJoakim Zhang #include <linux/auxiliary_bus.h>
11*b5fa9d3bSJoakim Zhang #include <linux/delay.h>
12*b5fa9d3bSJoakim Zhang #include <linux/device.h>
13*b5fa9d3bSJoakim Zhang #include <linux/module.h>
14*b5fa9d3bSJoakim Zhang #include <linux/regmap.h>
15*b5fa9d3bSJoakim Zhang #include <linux/reset-controller.h>
16*b5fa9d3bSJoakim Zhang
17*b5fa9d3bSJoakim Zhang #define SKY1_RESET_SLEEP_US 50
18*b5fa9d3bSJoakim Zhang
19*b5fa9d3bSJoakim Zhang #define AUDSS_SW_RST 0x78
20*b5fa9d3bSJoakim Zhang
21*b5fa9d3bSJoakim Zhang struct sky1_audss_reset_map {
22*b5fa9d3bSJoakim Zhang unsigned int offset;
23*b5fa9d3bSJoakim Zhang unsigned int mask;
24*b5fa9d3bSJoakim Zhang };
25*b5fa9d3bSJoakim Zhang
26*b5fa9d3bSJoakim Zhang struct sky1_audss_reset {
27*b5fa9d3bSJoakim Zhang struct reset_controller_dev rcdev;
28*b5fa9d3bSJoakim Zhang struct regmap *regmap;
29*b5fa9d3bSJoakim Zhang const struct sky1_audss_reset_map *map;
30*b5fa9d3bSJoakim Zhang };
31*b5fa9d3bSJoakim Zhang
32*b5fa9d3bSJoakim Zhang static const struct sky1_audss_reset_map sky1_audss_reset_map[] = {
33*b5fa9d3bSJoakim Zhang [AUDSS_I2S0_SW_RST] = { AUDSS_SW_RST, BIT(0) },
34*b5fa9d3bSJoakim Zhang [AUDSS_I2S1_SW_RST] = { AUDSS_SW_RST, BIT(1) },
35*b5fa9d3bSJoakim Zhang [AUDSS_I2S2_SW_RST] = { AUDSS_SW_RST, BIT(2) },
36*b5fa9d3bSJoakim Zhang [AUDSS_I2S3_SW_RST] = { AUDSS_SW_RST, BIT(3) },
37*b5fa9d3bSJoakim Zhang [AUDSS_I2S4_SW_RST] = { AUDSS_SW_RST, BIT(4) },
38*b5fa9d3bSJoakim Zhang [AUDSS_I2S5_SW_RST] = { AUDSS_SW_RST, BIT(5) },
39*b5fa9d3bSJoakim Zhang [AUDSS_I2S6_SW_RST] = { AUDSS_SW_RST, BIT(6) },
40*b5fa9d3bSJoakim Zhang [AUDSS_I2S7_SW_RST] = { AUDSS_SW_RST, BIT(7) },
41*b5fa9d3bSJoakim Zhang [AUDSS_I2S8_SW_RST] = { AUDSS_SW_RST, BIT(8) },
42*b5fa9d3bSJoakim Zhang [AUDSS_I2S9_SW_RST] = { AUDSS_SW_RST, BIT(9) },
43*b5fa9d3bSJoakim Zhang [AUDSS_WDT_SW_RST] = { AUDSS_SW_RST, BIT(10) },
44*b5fa9d3bSJoakim Zhang [AUDSS_TIMER_SW_RST] = { AUDSS_SW_RST, BIT(11) },
45*b5fa9d3bSJoakim Zhang [AUDSS_MB0_SW_RST] = { AUDSS_SW_RST, BIT(12) },
46*b5fa9d3bSJoakim Zhang [AUDSS_MB1_SW_RST] = { AUDSS_SW_RST, BIT(13) },
47*b5fa9d3bSJoakim Zhang [AUDSS_HDA_SW_RST] = { AUDSS_SW_RST, BIT(14) },
48*b5fa9d3bSJoakim Zhang [AUDSS_DMAC_SW_RST] = { AUDSS_SW_RST, BIT(15) },
49*b5fa9d3bSJoakim Zhang };
50*b5fa9d3bSJoakim Zhang
to_sky1_audss_reset(struct reset_controller_dev * rcdev)51*b5fa9d3bSJoakim Zhang static struct sky1_audss_reset *to_sky1_audss_reset(struct reset_controller_dev *rcdev)
52*b5fa9d3bSJoakim Zhang {
53*b5fa9d3bSJoakim Zhang return container_of(rcdev, struct sky1_audss_reset, rcdev);
54*b5fa9d3bSJoakim Zhang }
55*b5fa9d3bSJoakim Zhang
sky1_audss_reset_set(struct reset_controller_dev * rcdev,unsigned long id,bool assert)56*b5fa9d3bSJoakim Zhang static int sky1_audss_reset_set(struct reset_controller_dev *rcdev,
57*b5fa9d3bSJoakim Zhang unsigned long id, bool assert)
58*b5fa9d3bSJoakim Zhang {
59*b5fa9d3bSJoakim Zhang struct sky1_audss_reset *priv = to_sky1_audss_reset(rcdev);
60*b5fa9d3bSJoakim Zhang const struct sky1_audss_reset_map *signal = &priv->map[id];
61*b5fa9d3bSJoakim Zhang int ret;
62*b5fa9d3bSJoakim Zhang
63*b5fa9d3bSJoakim Zhang ret = regmap_assign_bits(priv->regmap, signal->offset,
64*b5fa9d3bSJoakim Zhang signal->mask, !assert);
65*b5fa9d3bSJoakim Zhang if (ret)
66*b5fa9d3bSJoakim Zhang return ret;
67*b5fa9d3bSJoakim Zhang
68*b5fa9d3bSJoakim Zhang fsleep(SKY1_RESET_SLEEP_US);
69*b5fa9d3bSJoakim Zhang return 0;
70*b5fa9d3bSJoakim Zhang }
71*b5fa9d3bSJoakim Zhang
sky1_audss_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)72*b5fa9d3bSJoakim Zhang static int sky1_audss_reset_assert(struct reset_controller_dev *rcdev,
73*b5fa9d3bSJoakim Zhang unsigned long id)
74*b5fa9d3bSJoakim Zhang {
75*b5fa9d3bSJoakim Zhang return sky1_audss_reset_set(rcdev, id, true);
76*b5fa9d3bSJoakim Zhang }
77*b5fa9d3bSJoakim Zhang
sky1_audss_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)78*b5fa9d3bSJoakim Zhang static int sky1_audss_reset_deassert(struct reset_controller_dev *rcdev,
79*b5fa9d3bSJoakim Zhang unsigned long id)
80*b5fa9d3bSJoakim Zhang {
81*b5fa9d3bSJoakim Zhang return sky1_audss_reset_set(rcdev, id, false);
82*b5fa9d3bSJoakim Zhang }
83*b5fa9d3bSJoakim Zhang
84*b5fa9d3bSJoakim Zhang static const struct reset_control_ops sky1_audss_reset_ops = {
85*b5fa9d3bSJoakim Zhang .assert = sky1_audss_reset_assert,
86*b5fa9d3bSJoakim Zhang .deassert = sky1_audss_reset_deassert,
87*b5fa9d3bSJoakim Zhang };
88*b5fa9d3bSJoakim Zhang
sky1_audss_reset_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)89*b5fa9d3bSJoakim Zhang static int sky1_audss_reset_probe(struct auxiliary_device *adev,
90*b5fa9d3bSJoakim Zhang const struct auxiliary_device_id *id)
91*b5fa9d3bSJoakim Zhang {
92*b5fa9d3bSJoakim Zhang struct sky1_audss_reset *priv;
93*b5fa9d3bSJoakim Zhang struct device *dev = &adev->dev;
94*b5fa9d3bSJoakim Zhang
95*b5fa9d3bSJoakim Zhang priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
96*b5fa9d3bSJoakim Zhang if (!priv)
97*b5fa9d3bSJoakim Zhang return -ENOMEM;
98*b5fa9d3bSJoakim Zhang
99*b5fa9d3bSJoakim Zhang priv->regmap = dev_get_regmap(dev->parent, NULL);
100*b5fa9d3bSJoakim Zhang if (!priv->regmap)
101*b5fa9d3bSJoakim Zhang return dev_err_probe(dev, -ENODEV, "failed to get parent regmap\n");
102*b5fa9d3bSJoakim Zhang
103*b5fa9d3bSJoakim Zhang priv->map = sky1_audss_reset_map;
104*b5fa9d3bSJoakim Zhang priv->rcdev.owner = THIS_MODULE;
105*b5fa9d3bSJoakim Zhang priv->rcdev.nr_resets = ARRAY_SIZE(sky1_audss_reset_map);
106*b5fa9d3bSJoakim Zhang priv->rcdev.ops = &sky1_audss_reset_ops;
107*b5fa9d3bSJoakim Zhang priv->rcdev.of_node = dev->of_node;
108*b5fa9d3bSJoakim Zhang priv->rcdev.dev = dev;
109*b5fa9d3bSJoakim Zhang
110*b5fa9d3bSJoakim Zhang return devm_reset_controller_register(dev, &priv->rcdev);
111*b5fa9d3bSJoakim Zhang }
112*b5fa9d3bSJoakim Zhang
113*b5fa9d3bSJoakim Zhang static const struct auxiliary_device_id sky1_audss_reset_ids[] = {
114*b5fa9d3bSJoakim Zhang { .name = "clk_sky1_audss.reset" },
115*b5fa9d3bSJoakim Zhang { }
116*b5fa9d3bSJoakim Zhang };
117*b5fa9d3bSJoakim Zhang MODULE_DEVICE_TABLE(auxiliary, sky1_audss_reset_ids);
118*b5fa9d3bSJoakim Zhang
119*b5fa9d3bSJoakim Zhang static struct auxiliary_driver sky1_audss_reset_driver = {
120*b5fa9d3bSJoakim Zhang .probe = sky1_audss_reset_probe,
121*b5fa9d3bSJoakim Zhang .id_table = sky1_audss_reset_ids,
122*b5fa9d3bSJoakim Zhang };
123*b5fa9d3bSJoakim Zhang module_auxiliary_driver(sky1_audss_reset_driver);
124*b5fa9d3bSJoakim Zhang
125*b5fa9d3bSJoakim Zhang MODULE_AUTHOR("Joakim Zhang <joakim.zhang@cixtech.com>");
126*b5fa9d3bSJoakim Zhang MODULE_DESCRIPTION("Cix Sky1 Audio Subsystem reset driver");
127*b5fa9d3bSJoakim Zhang MODULE_LICENSE("GPL");
128