1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L USBPHY control driver 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation 6 */ 7 8 #include <linux/io.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/reset.h> 15 #include <linux/reset-controller.h> 16 #include <linux/mfd/syscon.h> 17 18 #define RESET 0x000 19 #define VBENCTL 0x03c 20 21 #define RESET_SEL_PLLRESET BIT(12) 22 #define RESET_PLLRESET BIT(8) 23 24 #define RESET_SEL_P2RESET BIT(5) 25 #define RESET_SEL_P1RESET BIT(4) 26 #define RESET_PHYRST_2 BIT(1) 27 #define RESET_PHYRST_1 BIT(0) 28 29 #define PHY_RESET_PORT2 (RESET_SEL_P2RESET | RESET_PHYRST_2) 30 #define PHY_RESET_PORT1 (RESET_SEL_P1RESET | RESET_PHYRST_1) 31 32 #define NUM_PORTS 2 33 34 struct rzg2l_usbphy_ctrl_priv { 35 struct reset_controller_dev rcdev; 36 struct reset_control *rstc; 37 void __iomem *base; 38 struct platform_device *vdev; 39 struct regmap_field *pwrrdy; 40 41 spinlock_t lock; 42 }; 43 44 #define rcdev_to_priv(x) container_of(x, struct rzg2l_usbphy_ctrl_priv, rcdev) 45 46 static int rzg2l_usbphy_ctrl_assert(struct reset_controller_dev *rcdev, 47 unsigned long id) 48 { 49 struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev); 50 u32 port_mask = PHY_RESET_PORT1 | PHY_RESET_PORT2; 51 void __iomem *base = priv->base; 52 unsigned long flags; 53 u32 val; 54 55 spin_lock_irqsave(&priv->lock, flags); 56 val = readl(base + RESET); 57 val |= id ? PHY_RESET_PORT2 : PHY_RESET_PORT1; 58 if (port_mask == (val & port_mask)) 59 val |= RESET_PLLRESET; 60 writel(val, base + RESET); 61 spin_unlock_irqrestore(&priv->lock, flags); 62 63 return 0; 64 } 65 66 static int rzg2l_usbphy_ctrl_deassert(struct reset_controller_dev *rcdev, 67 unsigned long id) 68 { 69 struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev); 70 void __iomem *base = priv->base; 71 unsigned long flags; 72 u32 val; 73 74 spin_lock_irqsave(&priv->lock, flags); 75 val = readl(base + RESET); 76 77 val |= RESET_SEL_PLLRESET; 78 val &= ~(RESET_PLLRESET | (id ? PHY_RESET_PORT2 : PHY_RESET_PORT1)); 79 writel(val, base + RESET); 80 spin_unlock_irqrestore(&priv->lock, flags); 81 82 return 0; 83 } 84 85 static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev, 86 unsigned long id) 87 { 88 struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev); 89 u32 port_mask; 90 91 port_mask = id ? PHY_RESET_PORT2 : PHY_RESET_PORT1; 92 93 return !!(readl(priv->base + RESET) & port_mask); 94 } 95 96 /* put pll and phy into reset state */ 97 static void rzg2l_usbphy_ctrl_init(struct rzg2l_usbphy_ctrl_priv *priv) 98 { 99 unsigned long flags; 100 u32 val; 101 102 spin_lock_irqsave(&priv->lock, flags); 103 val = readl(priv->base + RESET); 104 val |= RESET_SEL_PLLRESET | RESET_PLLRESET | PHY_RESET_PORT2 | PHY_RESET_PORT1; 105 writel(val, priv->base + RESET); 106 spin_unlock_irqrestore(&priv->lock, flags); 107 } 108 109 #define RZG2L_USBPHY_CTRL_PWRRDY 1 110 111 static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = { 112 { .compatible = "renesas,rzg2l-usbphy-ctrl" }, 113 { 114 .compatible = "renesas,r9a08g045-usbphy-ctrl", 115 .data = (void *)RZG2L_USBPHY_CTRL_PWRRDY 116 }, 117 { /* Sentinel */ } 118 }; 119 MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table); 120 121 static const struct reset_control_ops rzg2l_usbphy_ctrl_reset_ops = { 122 .assert = rzg2l_usbphy_ctrl_assert, 123 .deassert = rzg2l_usbphy_ctrl_deassert, 124 .status = rzg2l_usbphy_ctrl_status, 125 }; 126 127 static const struct regmap_config rzg2l_usb_regconf = { 128 .reg_bits = 32, 129 .val_bits = 32, 130 .reg_stride = 4, 131 .max_register = 1, 132 }; 133 134 static int rzg2l_usbphy_ctrl_set_pwrrdy(struct regmap_field *pwrrdy, 135 bool power_on) 136 { 137 u32 val = power_on ? 0 : 1; 138 139 if (!pwrrdy) 140 return 0; 141 142 /* The initialization path guarantees that the mask is 1 bit long. */ 143 return regmap_field_update_bits(pwrrdy, 1, val); 144 } 145 146 static void rzg2l_usbphy_ctrl_pwrrdy_off(void *data) 147 { 148 rzg2l_usbphy_ctrl_set_pwrrdy(data, false); 149 } 150 151 static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device *dev, 152 struct rzg2l_usbphy_ctrl_priv *priv) 153 { 154 struct reg_field field; 155 struct regmap *regmap; 156 const int *data; 157 u32 args[2]; 158 int ret; 159 160 data = device_get_match_data(dev); 161 if ((uintptr_t)data != RZG2L_USBPHY_CTRL_PWRRDY) 162 return 0; 163 164 regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, 165 "renesas,sysc-pwrrdy", 166 ARRAY_SIZE(args), args); 167 if (IS_ERR(regmap)) 168 return PTR_ERR(regmap); 169 170 /* Don't allow more than one bit in mask. */ 171 if (hweight32(args[1]) != 1) 172 return -EINVAL; 173 174 field.reg = args[0]; 175 field.lsb = __ffs(args[1]); 176 field.msb = __fls(args[1]); 177 178 priv->pwrrdy = devm_regmap_field_alloc(dev, regmap, field); 179 if (IS_ERR(priv->pwrrdy)) 180 return PTR_ERR(priv->pwrrdy); 181 182 ret = rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, true); 183 if (ret) 184 return ret; 185 186 return devm_add_action_or_reset(dev, rzg2l_usbphy_ctrl_pwrrdy_off, priv->pwrrdy); 187 } 188 189 static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev) 190 { 191 struct device *dev = &pdev->dev; 192 struct rzg2l_usbphy_ctrl_priv *priv; 193 struct platform_device *vdev; 194 struct regmap *regmap; 195 int error; 196 197 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 198 if (!priv) 199 return -ENOMEM; 200 201 priv->base = devm_platform_ioremap_resource(pdev, 0); 202 if (IS_ERR(priv->base)) 203 return PTR_ERR(priv->base); 204 205 regmap = devm_regmap_init_mmio(dev, priv->base + VBENCTL, &rzg2l_usb_regconf); 206 if (IS_ERR(regmap)) 207 return PTR_ERR(regmap); 208 209 error = rzg2l_usbphy_ctrl_pwrrdy_init(dev, priv); 210 if (error) 211 return error; 212 213 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 214 if (IS_ERR(priv->rstc)) 215 return dev_err_probe(dev, PTR_ERR(priv->rstc), 216 "failed to get reset\n"); 217 218 error = reset_control_deassert(priv->rstc); 219 if (error) 220 return error; 221 222 spin_lock_init(&priv->lock); 223 dev_set_drvdata(dev, priv); 224 225 pm_runtime_enable(&pdev->dev); 226 error = pm_runtime_resume_and_get(&pdev->dev); 227 if (error < 0) { 228 dev_err_probe(&pdev->dev, error, "pm_runtime_resume_and_get failed"); 229 goto err_pm_disable_reset_deassert; 230 } 231 232 rzg2l_usbphy_ctrl_init(priv); 233 234 priv->rcdev.ops = &rzg2l_usbphy_ctrl_reset_ops; 235 priv->rcdev.of_reset_n_cells = 1; 236 priv->rcdev.nr_resets = NUM_PORTS; 237 priv->rcdev.of_node = dev->of_node; 238 priv->rcdev.dev = dev; 239 240 error = devm_reset_controller_register(dev, &priv->rcdev); 241 if (error) 242 goto err_pm_runtime_put; 243 244 vdev = platform_device_alloc("rzg2l-usb-vbus-regulator", pdev->id); 245 if (!vdev) { 246 error = -ENOMEM; 247 goto err_pm_runtime_put; 248 } 249 vdev->dev.parent = dev; 250 priv->vdev = vdev; 251 252 device_set_of_node_from_dev(&vdev->dev, dev); 253 error = platform_device_add(vdev); 254 if (error) 255 goto err_device_put; 256 257 return 0; 258 259 err_device_put: 260 platform_device_put(vdev); 261 err_pm_runtime_put: 262 pm_runtime_put(&pdev->dev); 263 err_pm_disable_reset_deassert: 264 pm_runtime_disable(&pdev->dev); 265 reset_control_assert(priv->rstc); 266 return error; 267 } 268 269 static void rzg2l_usbphy_ctrl_remove(struct platform_device *pdev) 270 { 271 struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(&pdev->dev); 272 273 platform_device_unregister(priv->vdev); 274 pm_runtime_put(&pdev->dev); 275 pm_runtime_disable(&pdev->dev); 276 reset_control_assert(priv->rstc); 277 } 278 279 static int rzg2l_usbphy_ctrl_suspend(struct device *dev) 280 { 281 struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(dev); 282 u32 val; 283 int ret; 284 285 val = readl(priv->base + RESET); 286 if (!(val & PHY_RESET_PORT2) || !(val & PHY_RESET_PORT1)) 287 WARN(1, "Suspend with resets de-asserted\n"); 288 289 pm_runtime_put_sync(dev); 290 291 ret = reset_control_assert(priv->rstc); 292 if (ret) 293 goto rpm_resume; 294 295 ret = rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, false); 296 if (ret) 297 goto reset_deassert; 298 299 return 0; 300 301 reset_deassert: 302 reset_control_deassert(priv->rstc); 303 rpm_resume: 304 pm_runtime_resume_and_get(dev); 305 return ret; 306 } 307 308 static int rzg2l_usbphy_ctrl_resume(struct device *dev) 309 { 310 struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(dev); 311 int ret; 312 313 ret = rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, true); 314 if (ret) 315 return ret; 316 317 ret = reset_control_deassert(priv->rstc); 318 if (ret) 319 goto pwrrdy_off; 320 321 ret = pm_runtime_resume_and_get(dev); 322 if (ret) 323 goto reset_assert; 324 325 rzg2l_usbphy_ctrl_init(priv); 326 327 return 0; 328 329 reset_assert: 330 reset_control_assert(priv->rstc); 331 pwrrdy_off: 332 rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, false); 333 return ret; 334 } 335 336 static DEFINE_SIMPLE_DEV_PM_OPS(rzg2l_usbphy_ctrl_pm_ops, 337 rzg2l_usbphy_ctrl_suspend, 338 rzg2l_usbphy_ctrl_resume); 339 340 static struct platform_driver rzg2l_usbphy_ctrl_driver = { 341 .driver = { 342 .name = "rzg2l_usbphy_ctrl", 343 .of_match_table = rzg2l_usbphy_ctrl_match_table, 344 .pm = pm_ptr(&rzg2l_usbphy_ctrl_pm_ops), 345 }, 346 .probe = rzg2l_usbphy_ctrl_probe, 347 .remove = rzg2l_usbphy_ctrl_remove, 348 }; 349 module_platform_driver(rzg2l_usbphy_ctrl_driver); 350 351 MODULE_LICENSE("GPL v2"); 352 MODULE_DESCRIPTION("Renesas RZ/G2L USBPHY Control"); 353 MODULE_AUTHOR("biju.das.jz@bp.renesas.com>"); 354