1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L USBPHY control driver 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation 6 */ 7 8 #include <linux/io.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/reset.h> 15 #include <linux/reset-controller.h> 16 #include <linux/mfd/syscon.h> 17 18 #define RESET 0x000 19 #define VBENCTL 0x03c 20 21 #define RESET_SEL_PLLRESET BIT(12) 22 #define RESET_PLLRESET BIT(8) 23 24 #define RESET_SEL_P2RESET BIT(5) 25 #define RESET_SEL_P1RESET BIT(4) 26 #define RESET_PHYRST_2 BIT(1) 27 #define RESET_PHYRST_1 BIT(0) 28 29 #define PHY_RESET_PORT2 (RESET_SEL_P2RESET | RESET_PHYRST_2) 30 #define PHY_RESET_PORT1 (RESET_SEL_P1RESET | RESET_PHYRST_1) 31 32 #define NUM_PORTS 2 33 34 struct rzg2l_usbphy_ctrl_priv { 35 struct reset_controller_dev rcdev; 36 struct reset_control *rstc; 37 void __iomem *base; 38 struct platform_device *vdev; 39 struct regmap_field *pwrrdy; 40 41 spinlock_t lock; 42 }; 43 44 #define rcdev_to_priv(x) container_of(x, struct rzg2l_usbphy_ctrl_priv, rcdev) 45 46 static int rzg2l_usbphy_ctrl_assert(struct reset_controller_dev *rcdev, 47 unsigned long id) 48 { 49 struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev); 50 u32 port_mask = PHY_RESET_PORT1 | PHY_RESET_PORT2; 51 void __iomem *base = priv->base; 52 unsigned long flags; 53 u32 val; 54 55 spin_lock_irqsave(&priv->lock, flags); 56 val = readl(base + RESET); 57 val |= id ? PHY_RESET_PORT2 : PHY_RESET_PORT1; 58 if (port_mask == (val & port_mask)) 59 val |= RESET_PLLRESET; 60 writel(val, base + RESET); 61 spin_unlock_irqrestore(&priv->lock, flags); 62 63 return 0; 64 } 65 66 static int rzg2l_usbphy_ctrl_deassert(struct reset_controller_dev *rcdev, 67 unsigned long id) 68 { 69 struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev); 70 void __iomem *base = priv->base; 71 unsigned long flags; 72 u32 val; 73 74 spin_lock_irqsave(&priv->lock, flags); 75 val = readl(base + RESET); 76 77 val |= RESET_SEL_PLLRESET; 78 val &= ~(RESET_PLLRESET | (id ? PHY_RESET_PORT2 : PHY_RESET_PORT1)); 79 writel(val, base + RESET); 80 spin_unlock_irqrestore(&priv->lock, flags); 81 82 return 0; 83 } 84 85 static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev, 86 unsigned long id) 87 { 88 struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev); 89 u32 port_mask; 90 91 port_mask = id ? PHY_RESET_PORT2 : PHY_RESET_PORT1; 92 93 return !!(readl(priv->base + RESET) & port_mask); 94 } 95 96 /* put pll and phy into reset state */ 97 static void rzg2l_usbphy_ctrl_init(struct rzg2l_usbphy_ctrl_priv *priv) 98 { 99 unsigned long flags; 100 u32 val; 101 102 spin_lock_irqsave(&priv->lock, flags); 103 val = readl(priv->base + RESET); 104 val |= RESET_SEL_PLLRESET | RESET_PLLRESET | PHY_RESET_PORT2 | PHY_RESET_PORT1; 105 writel(val, priv->base + RESET); 106 spin_unlock_irqrestore(&priv->lock, flags); 107 } 108 109 #define RZG2L_USBPHY_CTRL_PWRRDY 1 110 111 static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = { 112 { .compatible = "renesas,rzg2l-usbphy-ctrl" }, 113 { 114 .compatible = "renesas,r9a08g045-usbphy-ctrl", 115 .data = (void *)RZG2L_USBPHY_CTRL_PWRRDY 116 }, 117 { /* Sentinel */ } 118 }; 119 MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table); 120 121 static const struct reset_control_ops rzg2l_usbphy_ctrl_reset_ops = { 122 .assert = rzg2l_usbphy_ctrl_assert, 123 .deassert = rzg2l_usbphy_ctrl_deassert, 124 .status = rzg2l_usbphy_ctrl_status, 125 }; 126 127 static const struct regmap_config rzg2l_usb_regconf = { 128 .reg_bits = 32, 129 .val_bits = 32, 130 .reg_stride = 4, 131 .max_register = 1, 132 }; 133 134 static int rzg2l_usbphy_ctrl_set_pwrrdy(struct regmap_field *pwrrdy, 135 bool power_on) 136 { 137 u32 val = power_on ? 0 : 1; 138 139 /* The initialization path guarantees that the mask is 1 bit long. */ 140 return regmap_field_update_bits(pwrrdy, 1, val); 141 } 142 143 static void rzg2l_usbphy_ctrl_pwrrdy_off(void *data) 144 { 145 rzg2l_usbphy_ctrl_set_pwrrdy(data, false); 146 } 147 148 static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device *dev, 149 struct rzg2l_usbphy_ctrl_priv *priv) 150 { 151 struct reg_field field; 152 struct regmap *regmap; 153 const int *data; 154 u32 args[2]; 155 int ret; 156 157 data = device_get_match_data(dev); 158 if ((uintptr_t)data != RZG2L_USBPHY_CTRL_PWRRDY) 159 return 0; 160 161 regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, 162 "renesas,sysc-pwrrdy", 163 ARRAY_SIZE(args), args); 164 if (IS_ERR(regmap)) 165 return PTR_ERR(regmap); 166 167 /* Don't allow more than one bit in mask. */ 168 if (hweight32(args[1]) != 1) 169 return -EINVAL; 170 171 field.reg = args[0]; 172 field.lsb = __ffs(args[1]); 173 field.msb = __fls(args[1]); 174 175 priv->pwrrdy = devm_regmap_field_alloc(dev, regmap, field); 176 if (IS_ERR(priv->pwrrdy)) 177 return PTR_ERR(priv->pwrrdy); 178 179 ret = rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, true); 180 if (ret) 181 return ret; 182 183 return devm_add_action_or_reset(dev, rzg2l_usbphy_ctrl_pwrrdy_off, priv->pwrrdy); 184 } 185 186 static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev) 187 { 188 struct device *dev = &pdev->dev; 189 struct rzg2l_usbphy_ctrl_priv *priv; 190 struct platform_device *vdev; 191 struct regmap *regmap; 192 int error; 193 194 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 195 if (!priv) 196 return -ENOMEM; 197 198 priv->base = devm_platform_ioremap_resource(pdev, 0); 199 if (IS_ERR(priv->base)) 200 return PTR_ERR(priv->base); 201 202 regmap = devm_regmap_init_mmio(dev, priv->base + VBENCTL, &rzg2l_usb_regconf); 203 if (IS_ERR(regmap)) 204 return PTR_ERR(regmap); 205 206 error = rzg2l_usbphy_ctrl_pwrrdy_init(dev, priv); 207 if (error) 208 return error; 209 210 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 211 if (IS_ERR(priv->rstc)) 212 return dev_err_probe(dev, PTR_ERR(priv->rstc), 213 "failed to get reset\n"); 214 215 error = reset_control_deassert(priv->rstc); 216 if (error) 217 return error; 218 219 spin_lock_init(&priv->lock); 220 dev_set_drvdata(dev, priv); 221 222 pm_runtime_enable(&pdev->dev); 223 error = pm_runtime_resume_and_get(&pdev->dev); 224 if (error < 0) { 225 dev_err_probe(&pdev->dev, error, "pm_runtime_resume_and_get failed"); 226 goto err_pm_disable_reset_deassert; 227 } 228 229 rzg2l_usbphy_ctrl_init(priv); 230 231 priv->rcdev.ops = &rzg2l_usbphy_ctrl_reset_ops; 232 priv->rcdev.of_reset_n_cells = 1; 233 priv->rcdev.nr_resets = NUM_PORTS; 234 priv->rcdev.of_node = dev->of_node; 235 priv->rcdev.dev = dev; 236 237 error = devm_reset_controller_register(dev, &priv->rcdev); 238 if (error) 239 goto err_pm_runtime_put; 240 241 vdev = platform_device_alloc("rzg2l-usb-vbus-regulator", pdev->id); 242 if (!vdev) { 243 error = -ENOMEM; 244 goto err_pm_runtime_put; 245 } 246 vdev->dev.parent = dev; 247 priv->vdev = vdev; 248 249 device_set_of_node_from_dev(&vdev->dev, dev); 250 error = platform_device_add(vdev); 251 if (error) 252 goto err_device_put; 253 254 return 0; 255 256 err_device_put: 257 platform_device_put(vdev); 258 err_pm_runtime_put: 259 pm_runtime_put(&pdev->dev); 260 err_pm_disable_reset_deassert: 261 pm_runtime_disable(&pdev->dev); 262 reset_control_assert(priv->rstc); 263 return error; 264 } 265 266 static void rzg2l_usbphy_ctrl_remove(struct platform_device *pdev) 267 { 268 struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(&pdev->dev); 269 270 platform_device_unregister(priv->vdev); 271 pm_runtime_put(&pdev->dev); 272 pm_runtime_disable(&pdev->dev); 273 reset_control_assert(priv->rstc); 274 } 275 276 static int rzg2l_usbphy_ctrl_suspend(struct device *dev) 277 { 278 struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(dev); 279 u32 val; 280 int ret; 281 282 val = readl(priv->base + RESET); 283 if (!(val & PHY_RESET_PORT2) || !(val & PHY_RESET_PORT1)) 284 WARN(1, "Suspend with resets de-asserted\n"); 285 286 pm_runtime_put_sync(dev); 287 288 ret = reset_control_assert(priv->rstc); 289 if (ret) 290 goto rpm_resume; 291 292 ret = rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, false); 293 if (ret) 294 goto reset_deassert; 295 296 return 0; 297 298 reset_deassert: 299 reset_control_deassert(priv->rstc); 300 rpm_resume: 301 pm_runtime_resume_and_get(dev); 302 return ret; 303 } 304 305 static int rzg2l_usbphy_ctrl_resume(struct device *dev) 306 { 307 struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(dev); 308 int ret; 309 310 ret = rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, true); 311 if (ret) 312 return ret; 313 314 ret = reset_control_deassert(priv->rstc); 315 if (ret) 316 goto pwrrdy_off; 317 318 ret = pm_runtime_resume_and_get(dev); 319 if (ret) 320 goto reset_assert; 321 322 rzg2l_usbphy_ctrl_init(priv); 323 324 return 0; 325 326 reset_assert: 327 reset_control_assert(priv->rstc); 328 pwrrdy_off: 329 rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, false); 330 return ret; 331 } 332 333 static DEFINE_SIMPLE_DEV_PM_OPS(rzg2l_usbphy_ctrl_pm_ops, 334 rzg2l_usbphy_ctrl_suspend, 335 rzg2l_usbphy_ctrl_resume); 336 337 static struct platform_driver rzg2l_usbphy_ctrl_driver = { 338 .driver = { 339 .name = "rzg2l_usbphy_ctrl", 340 .of_match_table = rzg2l_usbphy_ctrl_match_table, 341 .pm = pm_ptr(&rzg2l_usbphy_ctrl_pm_ops), 342 }, 343 .probe = rzg2l_usbphy_ctrl_probe, 344 .remove = rzg2l_usbphy_ctrl_remove, 345 }; 346 module_platform_driver(rzg2l_usbphy_ctrl_driver); 347 348 MODULE_LICENSE("GPL v2"); 349 MODULE_DESCRIPTION("Renesas RZ/G2L USBPHY Control"); 350 MODULE_AUTHOR("biju.das.jz@bp.renesas.com>"); 351