1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2019 Nuvoton Technology corporation. 3 4 #include <linux/auxiliary_bus.h> 5 #include <linux/delay.h> 6 #include <linux/err.h> 7 #include <linux/io.h> 8 #include <linux/init.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/property.h> 12 #include <linux/reboot.h> 13 #include <linux/reset-controller.h> 14 #include <linux/slab.h> 15 #include <linux/spinlock.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/regmap.h> 18 #include <linux/of_address.h> 19 20 #include <soc/nuvoton/clock-npcm8xx.h> 21 22 /* NPCM7xx GCR registers */ 23 #define NPCM_MDLR_OFFSET 0x7C 24 #define NPCM7XX_MDLR_USBD0 BIT(9) 25 #define NPCM7XX_MDLR_USBD1 BIT(8) 26 #define NPCM7XX_MDLR_USBD2_4 BIT(21) 27 #define NPCM7XX_MDLR_USBD5_9 BIT(22) 28 29 /* NPCM8xx MDLR bits */ 30 #define NPCM8XX_MDLR_USBD0_3 BIT(9) 31 #define NPCM8XX_MDLR_USBD4_7 BIT(22) 32 #define NPCM8XX_MDLR_USBD8 BIT(24) 33 #define NPCM8XX_MDLR_USBD9 BIT(21) 34 35 #define NPCM_USB1PHYCTL_OFFSET 0x140 36 #define NPCM_USB2PHYCTL_OFFSET 0x144 37 #define NPCM_USB3PHYCTL_OFFSET 0x148 38 #define NPCM_USBXPHYCTL_RS BIT(28) 39 40 /* NPCM7xx Reset registers */ 41 #define NPCM_SWRSTR 0x14 42 #define NPCM_SWRST BIT(2) 43 44 #define NPCM_IPSRST1 0x20 45 #define NPCM_IPSRST1_USBD1 BIT(5) 46 #define NPCM_IPSRST1_USBD2 BIT(8) 47 #define NPCM_IPSRST1_USBD3 BIT(25) 48 #define NPCM_IPSRST1_USBD4 BIT(22) 49 #define NPCM_IPSRST1_USBD5 BIT(23) 50 #define NPCM_IPSRST1_USBD6 BIT(24) 51 52 #define NPCM_IPSRST2 0x24 53 #define NPCM_IPSRST2_USB_HOST BIT(26) 54 55 #define NPCM_IPSRST3 0x34 56 #define NPCM_IPSRST3_USBD0 BIT(4) 57 #define NPCM_IPSRST3_USBD7 BIT(5) 58 #define NPCM_IPSRST3_USBD8 BIT(6) 59 #define NPCM_IPSRST3_USBD9 BIT(7) 60 #define NPCM_IPSRST3_USBPHY1 BIT(24) 61 #define NPCM_IPSRST3_USBPHY2 BIT(25) 62 63 #define NPCM_IPSRST4 0x74 64 #define NPCM_IPSRST4_USBPHY3 BIT(25) 65 #define NPCM_IPSRST4_USB_HOST2 BIT(31) 66 67 #define NPCM_RC_RESETS_PER_REG 32 68 #define NPCM_MASK_RESETS GENMASK(4, 0) 69 70 enum { 71 BMC_NPCM7XX = 0, 72 BMC_NPCM8XX, 73 }; 74 75 static const u32 npxm7xx_ipsrst[] = {NPCM_IPSRST1, NPCM_IPSRST2, NPCM_IPSRST3}; 76 static const u32 npxm8xx_ipsrst[] = {NPCM_IPSRST1, NPCM_IPSRST2, NPCM_IPSRST3, 77 NPCM_IPSRST4}; 78 79 struct npcm_reset_info { 80 u32 bmc_id; 81 u32 num_ipsrst; 82 const u32 *ipsrst; 83 }; 84 85 static const struct npcm_reset_info npxm7xx_reset_info[] = { 86 {.bmc_id = BMC_NPCM7XX, .num_ipsrst = 3, .ipsrst = npxm7xx_ipsrst}}; 87 static const struct npcm_reset_info npxm8xx_reset_info[] = { 88 {.bmc_id = BMC_NPCM8XX, .num_ipsrst = 4, .ipsrst = npxm8xx_ipsrst}}; 89 90 struct npcm_rc_data { 91 struct reset_controller_dev rcdev; 92 struct notifier_block restart_nb; 93 const struct npcm_reset_info *info; 94 struct regmap *gcr_regmap; 95 u32 sw_reset_number; 96 struct device *dev; 97 void __iomem *base; 98 spinlock_t lock; 99 }; 100 101 #define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev) 102 103 static int npcm_rc_restart(struct notifier_block *nb, unsigned long mode, 104 void *cmd) 105 { 106 struct npcm_rc_data *rc = container_of(nb, struct npcm_rc_data, 107 restart_nb); 108 109 writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR); 110 mdelay(1000); 111 112 pr_emerg("%s: unable to restart system\n", __func__); 113 114 return NOTIFY_DONE; 115 } 116 117 static int npcm_rc_setclear_reset(struct reset_controller_dev *rcdev, 118 unsigned long id, bool set) 119 { 120 struct npcm_rc_data *rc = to_rc_data(rcdev); 121 unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS); 122 unsigned int ctrl_offset = id >> 8; 123 unsigned long flags; 124 u32 stat; 125 126 spin_lock_irqsave(&rc->lock, flags); 127 stat = readl(rc->base + ctrl_offset); 128 if (set) 129 writel(stat | rst_bit, rc->base + ctrl_offset); 130 else 131 writel(stat & ~rst_bit, rc->base + ctrl_offset); 132 spin_unlock_irqrestore(&rc->lock, flags); 133 134 return 0; 135 } 136 137 static int npcm_rc_assert(struct reset_controller_dev *rcdev, unsigned long id) 138 { 139 return npcm_rc_setclear_reset(rcdev, id, true); 140 } 141 142 static int npcm_rc_deassert(struct reset_controller_dev *rcdev, 143 unsigned long id) 144 { 145 return npcm_rc_setclear_reset(rcdev, id, false); 146 } 147 148 static int npcm_rc_status(struct reset_controller_dev *rcdev, 149 unsigned long id) 150 { 151 struct npcm_rc_data *rc = to_rc_data(rcdev); 152 unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS); 153 unsigned int ctrl_offset = id >> 8; 154 155 return (readl(rc->base + ctrl_offset) & rst_bit); 156 } 157 158 static int npcm_reset_xlate(struct reset_controller_dev *rcdev, 159 const struct of_phandle_args *reset_spec) 160 { 161 struct npcm_rc_data *rc = to_rc_data(rcdev); 162 unsigned int offset, bit; 163 bool offset_found = false; 164 int off_num; 165 166 offset = reset_spec->args[0]; 167 for (off_num = 0 ; off_num < rc->info->num_ipsrst ; off_num++) { 168 if (offset == rc->info->ipsrst[off_num]) { 169 offset_found = true; 170 break; 171 } 172 } 173 174 if (!offset_found) { 175 dev_err(rcdev->dev, "Error reset register (0x%x)\n", offset); 176 return -EINVAL; 177 } 178 179 bit = reset_spec->args[1]; 180 if (bit >= NPCM_RC_RESETS_PER_REG) { 181 dev_err(rcdev->dev, "Error reset number (%d)\n", bit); 182 return -EINVAL; 183 } 184 185 return (offset << 8) | bit; 186 } 187 188 static const struct of_device_id npcm_rc_match[] = { 189 { .compatible = "nuvoton,npcm750-reset", .data = &npxm7xx_reset_info}, 190 { .compatible = "nuvoton,npcm845-reset", .data = &npxm8xx_reset_info}, 191 { } 192 }; 193 194 static void npcm_usb_reset_npcm7xx(struct npcm_rc_data *rc) 195 { 196 u32 mdlr, iprst1, iprst2, iprst3; 197 u32 ipsrst1_bits = 0; 198 u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST; 199 u32 ipsrst3_bits = 0; 200 201 /* checking which USB device is enabled */ 202 regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr); 203 if (!(mdlr & NPCM7XX_MDLR_USBD0)) 204 ipsrst3_bits |= NPCM_IPSRST3_USBD0; 205 if (!(mdlr & NPCM7XX_MDLR_USBD1)) 206 ipsrst1_bits |= NPCM_IPSRST1_USBD1; 207 if (!(mdlr & NPCM7XX_MDLR_USBD2_4)) 208 ipsrst1_bits |= (NPCM_IPSRST1_USBD2 | 209 NPCM_IPSRST1_USBD3 | 210 NPCM_IPSRST1_USBD4); 211 if (!(mdlr & NPCM7XX_MDLR_USBD0)) { 212 ipsrst1_bits |= (NPCM_IPSRST1_USBD5 | 213 NPCM_IPSRST1_USBD6); 214 ipsrst3_bits |= (NPCM_IPSRST3_USBD7 | 215 NPCM_IPSRST3_USBD8 | 216 NPCM_IPSRST3_USBD9); 217 } 218 219 /* assert reset USB PHY and USB devices */ 220 iprst1 = readl(rc->base + NPCM_IPSRST1); 221 iprst2 = readl(rc->base + NPCM_IPSRST2); 222 iprst3 = readl(rc->base + NPCM_IPSRST3); 223 224 iprst1 |= ipsrst1_bits; 225 iprst2 |= ipsrst2_bits; 226 iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 | 227 NPCM_IPSRST3_USBPHY2); 228 229 writel(iprst1, rc->base + NPCM_IPSRST1); 230 writel(iprst2, rc->base + NPCM_IPSRST2); 231 writel(iprst3, rc->base + NPCM_IPSRST3); 232 233 /* clear USB PHY RS bit */ 234 regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET, 235 NPCM_USBXPHYCTL_RS, 0); 236 regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET, 237 NPCM_USBXPHYCTL_RS, 0); 238 239 /* deassert reset USB PHY */ 240 iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2); 241 writel(iprst3, rc->base + NPCM_IPSRST3); 242 243 udelay(50); 244 245 /* set USB PHY RS bit */ 246 regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET, 247 NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS); 248 regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET, 249 NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS); 250 251 /* deassert reset USB devices*/ 252 iprst1 &= ~ipsrst1_bits; 253 iprst2 &= ~ipsrst2_bits; 254 iprst3 &= ~ipsrst3_bits; 255 256 writel(iprst1, rc->base + NPCM_IPSRST1); 257 writel(iprst2, rc->base + NPCM_IPSRST2); 258 writel(iprst3, rc->base + NPCM_IPSRST3); 259 } 260 261 static void npcm_usb_reset_npcm8xx(struct npcm_rc_data *rc) 262 { 263 u32 mdlr, iprst1, iprst2, iprst3, iprst4; 264 u32 ipsrst1_bits = 0; 265 u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST; 266 u32 ipsrst3_bits = 0; 267 u32 ipsrst4_bits = NPCM_IPSRST4_USB_HOST2 | NPCM_IPSRST4_USBPHY3; 268 269 /* checking which USB device is enabled */ 270 regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr); 271 if (!(mdlr & NPCM8XX_MDLR_USBD0_3)) { 272 ipsrst3_bits |= NPCM_IPSRST3_USBD0; 273 ipsrst1_bits |= (NPCM_IPSRST1_USBD1 | 274 NPCM_IPSRST1_USBD2 | 275 NPCM_IPSRST1_USBD3); 276 } 277 if (!(mdlr & NPCM8XX_MDLR_USBD4_7)) { 278 ipsrst1_bits |= (NPCM_IPSRST1_USBD4 | 279 NPCM_IPSRST1_USBD5 | 280 NPCM_IPSRST1_USBD6); 281 ipsrst3_bits |= NPCM_IPSRST3_USBD7; 282 } 283 284 if (!(mdlr & NPCM8XX_MDLR_USBD8)) 285 ipsrst3_bits |= NPCM_IPSRST3_USBD8; 286 if (!(mdlr & NPCM8XX_MDLR_USBD9)) 287 ipsrst3_bits |= NPCM_IPSRST3_USBD9; 288 289 /* assert reset USB PHY and USB devices */ 290 iprst1 = readl(rc->base + NPCM_IPSRST1); 291 iprst2 = readl(rc->base + NPCM_IPSRST2); 292 iprst3 = readl(rc->base + NPCM_IPSRST3); 293 iprst4 = readl(rc->base + NPCM_IPSRST4); 294 295 iprst1 |= ipsrst1_bits; 296 iprst2 |= ipsrst2_bits; 297 iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 | 298 NPCM_IPSRST3_USBPHY2); 299 iprst4 |= ipsrst4_bits; 300 301 writel(iprst1, rc->base + NPCM_IPSRST1); 302 writel(iprst2, rc->base + NPCM_IPSRST2); 303 writel(iprst3, rc->base + NPCM_IPSRST3); 304 writel(iprst4, rc->base + NPCM_IPSRST4); 305 306 /* clear USB PHY RS bit */ 307 regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET, 308 NPCM_USBXPHYCTL_RS, 0); 309 regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET, 310 NPCM_USBXPHYCTL_RS, 0); 311 regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET, 312 NPCM_USBXPHYCTL_RS, 0); 313 314 /* deassert reset USB PHY */ 315 iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2); 316 writel(iprst3, rc->base + NPCM_IPSRST3); 317 iprst4 &= ~NPCM_IPSRST4_USBPHY3; 318 writel(iprst4, rc->base + NPCM_IPSRST4); 319 320 /* set USB PHY RS bit */ 321 regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET, 322 NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS); 323 regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET, 324 NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS); 325 regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET, 326 NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS); 327 328 /* deassert reset USB devices*/ 329 iprst1 &= ~ipsrst1_bits; 330 iprst2 &= ~ipsrst2_bits; 331 iprst3 &= ~ipsrst3_bits; 332 iprst4 &= ~ipsrst4_bits; 333 334 writel(iprst1, rc->base + NPCM_IPSRST1); 335 writel(iprst2, rc->base + NPCM_IPSRST2); 336 writel(iprst3, rc->base + NPCM_IPSRST3); 337 writel(iprst4, rc->base + NPCM_IPSRST4); 338 } 339 340 /* 341 * The following procedure should be observed in USB PHY, USB device and 342 * USB host initialization at BMC boot 343 */ 344 static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc) 345 { 346 struct device *dev = &pdev->dev; 347 348 rc->gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr"); 349 if (IS_ERR(rc->gcr_regmap)) { 350 dev_warn(&pdev->dev, "Failed to find nuvoton,sysgcr property, please update the device tree\n"); 351 dev_info(&pdev->dev, "Using nuvoton,npcm750-gcr for Poleg backward compatibility\n"); 352 rc->gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); 353 if (IS_ERR(rc->gcr_regmap)) { 354 dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-gcr"); 355 return PTR_ERR(rc->gcr_regmap); 356 } 357 } 358 359 rc->info = device_get_match_data(dev); 360 switch (rc->info->bmc_id) { 361 case BMC_NPCM7XX: 362 npcm_usb_reset_npcm7xx(rc); 363 break; 364 case BMC_NPCM8XX: 365 npcm_usb_reset_npcm8xx(rc); 366 break; 367 default: 368 return -ENODEV; 369 } 370 371 return 0; 372 } 373 374 static const struct reset_control_ops npcm_rc_ops = { 375 .assert = npcm_rc_assert, 376 .deassert = npcm_rc_deassert, 377 .status = npcm_rc_status, 378 }; 379 380 static void npcm_clock_unregister_adev(void *_adev) 381 { 382 struct auxiliary_device *adev = _adev; 383 384 auxiliary_device_delete(adev); 385 auxiliary_device_uninit(adev); 386 } 387 388 static void npcm_clock_adev_release(struct device *dev) 389 { 390 struct auxiliary_device *adev = to_auxiliary_dev(dev); 391 struct npcm_clock_adev *rdev = to_npcm_clock_adev(adev); 392 393 kfree(rdev); 394 } 395 396 static struct auxiliary_device *npcm_clock_adev_alloc(struct npcm_rc_data *rst_data, char *clk_name) 397 { 398 struct npcm_clock_adev *rdev; 399 struct auxiliary_device *adev; 400 int ret; 401 402 rdev = kzalloc(sizeof(*rdev), GFP_KERNEL); 403 if (!rdev) 404 return ERR_PTR(-ENOMEM); 405 406 rdev->base = rst_data->base; 407 408 adev = &rdev->adev; 409 adev->name = clk_name; 410 adev->dev.parent = rst_data->dev; 411 adev->dev.release = npcm_clock_adev_release; 412 adev->id = 555u; 413 414 ret = auxiliary_device_init(adev); 415 if (ret) { 416 kfree(rdev); 417 return ERR_PTR(ret); 418 } 419 420 return adev; 421 } 422 423 static int npcm8xx_clock_controller_register(struct npcm_rc_data *rst_data, char *clk_name) 424 { 425 struct auxiliary_device *adev; 426 int ret; 427 428 adev = npcm_clock_adev_alloc(rst_data, clk_name); 429 if (IS_ERR(adev)) 430 return PTR_ERR(adev); 431 432 ret = auxiliary_device_add(adev); 433 if (ret) { 434 auxiliary_device_uninit(adev); 435 return ret; 436 } 437 438 return devm_add_action_or_reset(rst_data->dev, npcm_clock_unregister_adev, adev); 439 } 440 441 static int npcm_rc_probe(struct platform_device *pdev) 442 { 443 struct npcm_rc_data *rc; 444 int ret; 445 446 rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL); 447 if (!rc) 448 return -ENOMEM; 449 450 rc->base = devm_platform_ioremap_resource(pdev, 0); 451 if (IS_ERR(rc->base)) 452 return PTR_ERR(rc->base); 453 454 spin_lock_init(&rc->lock); 455 456 rc->rcdev.owner = THIS_MODULE; 457 rc->rcdev.ops = &npcm_rc_ops; 458 rc->rcdev.of_node = pdev->dev.of_node; 459 rc->rcdev.of_reset_n_cells = 2; 460 rc->rcdev.of_xlate = npcm_reset_xlate; 461 rc->dev = &pdev->dev; 462 463 ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev); 464 if (ret) { 465 dev_err(&pdev->dev, "unable to register device\n"); 466 return ret; 467 } 468 469 if (npcm_usb_reset(pdev, rc)) 470 dev_warn(&pdev->dev, "NPCM USB reset failed, can cause issues with UDC and USB host\n"); 471 472 if (!of_property_read_u32(pdev->dev.of_node, "nuvoton,sw-reset-number", 473 &rc->sw_reset_number)) { 474 if (rc->sw_reset_number && rc->sw_reset_number < 5) { 475 rc->restart_nb.priority = 192; 476 rc->restart_nb.notifier_call = npcm_rc_restart; 477 ret = register_restart_handler(&rc->restart_nb); 478 if (ret) { 479 dev_warn(&pdev->dev, "failed to register restart handler\n"); 480 return ret; 481 } 482 } 483 } 484 485 switch (rc->info->bmc_id) { 486 case BMC_NPCM8XX: 487 return npcm8xx_clock_controller_register(rc, "clk-npcm8xx"); 488 default: 489 return 0; 490 } 491 } 492 493 static struct platform_driver npcm_rc_driver = { 494 .probe = npcm_rc_probe, 495 .driver = { 496 .name = "npcm-reset", 497 .of_match_table = npcm_rc_match, 498 .suppress_bind_attrs = true, 499 }, 500 }; 501 builtin_platform_driver(npcm_rc_driver); 502