1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2023 Nuvoton Technology Corp. 4 * Author: Chi-Fang Li <cfli0@nuvoton.com> 5 */ 6 7 #include <linux/bits.h> 8 #include <linux/container_of.h> 9 #include <linux/device.h> 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/reboot.h> 16 #include <linux/reset-controller.h> 17 #include <linux/spinlock.h> 18 #include <dt-bindings/reset/nuvoton,ma35d1-reset.h> 19 20 struct ma35d1_reset_data { 21 struct reset_controller_dev rcdev; 22 void __iomem *base; 23 /* protect registers against concurrent read-modify-write */ 24 spinlock_t lock; 25 }; 26 27 static const struct { 28 u32 reg_ofs; 29 u32 bit; 30 } ma35d1_reset_map[] = { 31 [MA35D1_RESET_CHIP] = {0x20, 0}, 32 [MA35D1_RESET_CA35CR0] = {0x20, 1}, 33 [MA35D1_RESET_CA35CR1] = {0x20, 2}, 34 [MA35D1_RESET_CM4] = {0x20, 3}, 35 [MA35D1_RESET_PDMA0] = {0x20, 4}, 36 [MA35D1_RESET_PDMA1] = {0x20, 5}, 37 [MA35D1_RESET_PDMA2] = {0x20, 6}, 38 [MA35D1_RESET_PDMA3] = {0x20, 7}, 39 [MA35D1_RESET_DISP] = {0x20, 9}, 40 [MA35D1_RESET_VCAP0] = {0x20, 10}, 41 [MA35D1_RESET_VCAP1] = {0x20, 11}, 42 [MA35D1_RESET_GFX] = {0x20, 12}, 43 [MA35D1_RESET_VDEC] = {0x20, 13}, 44 [MA35D1_RESET_WHC0] = {0x20, 14}, 45 [MA35D1_RESET_WHC1] = {0x20, 15}, 46 [MA35D1_RESET_GMAC0] = {0x20, 16}, 47 [MA35D1_RESET_GMAC1] = {0x20, 17}, 48 [MA35D1_RESET_HWSEM] = {0x20, 18}, 49 [MA35D1_RESET_EBI] = {0x20, 19}, 50 [MA35D1_RESET_HSUSBH0] = {0x20, 20}, 51 [MA35D1_RESET_HSUSBH1] = {0x20, 21}, 52 [MA35D1_RESET_HSUSBD] = {0x20, 22}, 53 [MA35D1_RESET_USBHL] = {0x20, 23}, 54 [MA35D1_RESET_SDH0] = {0x20, 24}, 55 [MA35D1_RESET_SDH1] = {0x20, 25}, 56 [MA35D1_RESET_NAND] = {0x20, 26}, 57 [MA35D1_RESET_GPIO] = {0x20, 27}, 58 [MA35D1_RESET_MCTLP] = {0x20, 28}, 59 [MA35D1_RESET_MCTLC] = {0x20, 29}, 60 [MA35D1_RESET_DDRPUB] = {0x20, 30}, 61 [MA35D1_RESET_TMR0] = {0x24, 2}, 62 [MA35D1_RESET_TMR1] = {0x24, 3}, 63 [MA35D1_RESET_TMR2] = {0x24, 4}, 64 [MA35D1_RESET_TMR3] = {0x24, 5}, 65 [MA35D1_RESET_I2C0] = {0x24, 8}, 66 [MA35D1_RESET_I2C1] = {0x24, 9}, 67 [MA35D1_RESET_I2C2] = {0x24, 10}, 68 [MA35D1_RESET_I2C3] = {0x24, 11}, 69 [MA35D1_RESET_QSPI0] = {0x24, 12}, 70 [MA35D1_RESET_SPI0] = {0x24, 13}, 71 [MA35D1_RESET_SPI1] = {0x24, 14}, 72 [MA35D1_RESET_SPI2] = {0x24, 15}, 73 [MA35D1_RESET_UART0] = {0x24, 16}, 74 [MA35D1_RESET_UART1] = {0x24, 17}, 75 [MA35D1_RESET_UART2] = {0x24, 18}, 76 [MA35D1_RESET_UART3] = {0x24, 19}, 77 [MA35D1_RESET_UART4] = {0x24, 20}, 78 [MA35D1_RESET_UART5] = {0x24, 21}, 79 [MA35D1_RESET_UART6] = {0x24, 22}, 80 [MA35D1_RESET_UART7] = {0x24, 23}, 81 [MA35D1_RESET_CANFD0] = {0x24, 24}, 82 [MA35D1_RESET_CANFD1] = {0x24, 25}, 83 [MA35D1_RESET_EADC0] = {0x24, 28}, 84 [MA35D1_RESET_I2S0] = {0x24, 29}, 85 [MA35D1_RESET_SC0] = {0x28, 0}, 86 [MA35D1_RESET_SC1] = {0x28, 1}, 87 [MA35D1_RESET_QSPI1] = {0x28, 4}, 88 [MA35D1_RESET_SPI3] = {0x28, 6}, 89 [MA35D1_RESET_EPWM0] = {0x28, 16}, 90 [MA35D1_RESET_EPWM1] = {0x28, 17}, 91 [MA35D1_RESET_QEI0] = {0x28, 22}, 92 [MA35D1_RESET_QEI1] = {0x28, 23}, 93 [MA35D1_RESET_ECAP0] = {0x28, 26}, 94 [MA35D1_RESET_ECAP1] = {0x28, 27}, 95 [MA35D1_RESET_CANFD2] = {0x28, 28}, 96 [MA35D1_RESET_ADC0] = {0x28, 31}, 97 [MA35D1_RESET_TMR4] = {0x2C, 0}, 98 [MA35D1_RESET_TMR5] = {0x2C, 1}, 99 [MA35D1_RESET_TMR6] = {0x2C, 2}, 100 [MA35D1_RESET_TMR7] = {0x2C, 3}, 101 [MA35D1_RESET_TMR8] = {0x2C, 4}, 102 [MA35D1_RESET_TMR9] = {0x2C, 5}, 103 [MA35D1_RESET_TMR10] = {0x2C, 6}, 104 [MA35D1_RESET_TMR11] = {0x2C, 7}, 105 [MA35D1_RESET_UART8] = {0x2C, 8}, 106 [MA35D1_RESET_UART9] = {0x2C, 9}, 107 [MA35D1_RESET_UART10] = {0x2C, 10}, 108 [MA35D1_RESET_UART11] = {0x2C, 11}, 109 [MA35D1_RESET_UART12] = {0x2C, 12}, 110 [MA35D1_RESET_UART13] = {0x2C, 13}, 111 [MA35D1_RESET_UART14] = {0x2C, 14}, 112 [MA35D1_RESET_UART15] = {0x2C, 15}, 113 [MA35D1_RESET_UART16] = {0x2C, 16}, 114 [MA35D1_RESET_I2S1] = {0x2C, 17}, 115 [MA35D1_RESET_I2C4] = {0x2C, 18}, 116 [MA35D1_RESET_I2C5] = {0x2C, 19}, 117 [MA35D1_RESET_EPWM2] = {0x2C, 20}, 118 [MA35D1_RESET_ECAP2] = {0x2C, 21}, 119 [MA35D1_RESET_QEI2] = {0x2C, 22}, 120 [MA35D1_RESET_CANFD3] = {0x2C, 23}, 121 [MA35D1_RESET_KPI] = {0x2C, 24}, 122 [MA35D1_RESET_GIC] = {0x2C, 28}, 123 [MA35D1_RESET_SSMCC] = {0x2C, 30}, 124 [MA35D1_RESET_SSPCC] = {0x2C, 31} 125 }; 126 127 static int ma35d1_restart_handler(struct sys_off_data *sys_off_data) 128 { 129 struct ma35d1_reset_data *data = sys_off_data->cb_data; 130 u32 id = MA35D1_RESET_CHIP; 131 132 writel_relaxed(BIT(ma35d1_reset_map[id].bit), 133 data->base + ma35d1_reset_map[id].reg_ofs); 134 return 0; 135 } 136 137 static int ma35d1_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) 138 { 139 struct ma35d1_reset_data *data = container_of(rcdev, struct ma35d1_reset_data, rcdev); 140 unsigned long flags; 141 u32 reg; 142 143 if (WARN_ON_ONCE(id >= ARRAY_SIZE(ma35d1_reset_map))) 144 return -EINVAL; 145 146 spin_lock_irqsave(&data->lock, flags); 147 reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); 148 if (assert) 149 reg |= BIT(ma35d1_reset_map[id].bit); 150 else 151 reg &= ~(BIT(ma35d1_reset_map[id].bit)); 152 writel_relaxed(reg, data->base + ma35d1_reset_map[id].reg_ofs); 153 spin_unlock_irqrestore(&data->lock, flags); 154 155 return 0; 156 } 157 158 static int ma35d1_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 159 { 160 return ma35d1_reset_update(rcdev, id, true); 161 } 162 163 static int ma35d1_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 164 { 165 return ma35d1_reset_update(rcdev, id, false); 166 } 167 168 static int ma35d1_reset_status(struct reset_controller_dev *rcdev, unsigned long id) 169 { 170 struct ma35d1_reset_data *data = container_of(rcdev, struct ma35d1_reset_data, rcdev); 171 u32 reg; 172 173 if (WARN_ON_ONCE(id >= ARRAY_SIZE(ma35d1_reset_map))) 174 return -EINVAL; 175 176 reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); 177 return !!(reg & BIT(ma35d1_reset_map[id].bit)); 178 } 179 180 static const struct reset_control_ops ma35d1_reset_ops = { 181 .assert = ma35d1_reset_assert, 182 .deassert = ma35d1_reset_deassert, 183 .status = ma35d1_reset_status, 184 }; 185 186 static const struct of_device_id ma35d1_reset_dt_ids[] = { 187 { .compatible = "nuvoton,ma35d1-reset" }, 188 { }, 189 }; 190 191 static int ma35d1_reset_probe(struct platform_device *pdev) 192 { 193 struct ma35d1_reset_data *reset_data; 194 struct device *dev = &pdev->dev; 195 int err; 196 197 if (!pdev->dev.of_node) { 198 dev_err(&pdev->dev, "Device tree node not found\n"); 199 return -EINVAL; 200 } 201 202 reset_data = devm_kzalloc(dev, sizeof(*reset_data), GFP_KERNEL); 203 if (!reset_data) 204 return -ENOMEM; 205 206 reset_data->base = devm_platform_ioremap_resource(pdev, 0); 207 if (IS_ERR(reset_data->base)) 208 return PTR_ERR(reset_data->base); 209 210 reset_data->rcdev.owner = THIS_MODULE; 211 reset_data->rcdev.nr_resets = MA35D1_RESET_COUNT; 212 reset_data->rcdev.ops = &ma35d1_reset_ops; 213 reset_data->rcdev.of_node = dev->of_node; 214 spin_lock_init(&reset_data->lock); 215 216 err = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, 192, 217 ma35d1_restart_handler, reset_data); 218 if (err) 219 dev_warn(&pdev->dev, "failed to register restart handler\n"); 220 221 return devm_reset_controller_register(dev, &reset_data->rcdev); 222 } 223 224 static struct platform_driver ma35d1_reset_driver = { 225 .probe = ma35d1_reset_probe, 226 .driver = { 227 .name = "ma35d1-reset", 228 .of_match_table = ma35d1_reset_dt_ids, 229 }, 230 }; 231 232 builtin_platform_driver(ma35d1_reset_driver); 233