1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Reset driver for NXP LPC18xx/43xx Reset Generation Unit (RGU). 4 * 5 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/init.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/reboot.h> 16 #include <linux/reset-controller.h> 17 #include <linux/spinlock.h> 18 19 /* LPC18xx RGU registers */ 20 #define LPC18XX_RGU_CTRL0 0x100 21 #define LPC18XX_RGU_CTRL1 0x104 22 #define LPC18XX_RGU_ACTIVE_STATUS0 0x150 23 #define LPC18XX_RGU_ACTIVE_STATUS1 0x154 24 25 #define LPC18XX_RGU_RESETS_PER_REG 32 26 27 /* Internal reset outputs */ 28 #define LPC18XX_RGU_CORE_RST 0 29 #define LPC43XX_RGU_M0SUB_RST 12 30 #define LPC43XX_RGU_M0APP_RST 56 31 32 struct lpc18xx_rgu_data { 33 struct reset_controller_dev rcdev; 34 struct clk *clk_delay; 35 struct clk *clk_reg; 36 void __iomem *base; 37 spinlock_t lock; 38 u32 delay_us; 39 }; 40 41 #define to_rgu_data(p) container_of(p, struct lpc18xx_rgu_data, rcdev) 42 43 static int lpc18xx_rgu_restart(struct sys_off_data *data) 44 { 45 struct lpc18xx_rgu_data *rc = data->cb_data; 46 47 writel(BIT(LPC18XX_RGU_CORE_RST), rc->base + LPC18XX_RGU_CTRL0); 48 mdelay(2000); 49 50 pr_emerg("%s: unable to restart system\n", __func__); 51 52 return NOTIFY_DONE; 53 } 54 55 /* 56 * The LPC18xx RGU has mostly self-deasserting resets except for the 57 * two reset lines going to the internal Cortex-M0 cores. 58 * 59 * To prevent the M0 core resets from accidentally getting deasserted 60 * status register must be check and bits in control register set to 61 * preserve the state. 62 */ 63 static int lpc18xx_rgu_setclear_reset(struct reset_controller_dev *rcdev, 64 unsigned long id, bool set) 65 { 66 struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev); 67 u32 stat_offset = LPC18XX_RGU_ACTIVE_STATUS0; 68 u32 ctrl_offset = LPC18XX_RGU_CTRL0; 69 unsigned long flags; 70 u32 stat, rst_bit; 71 72 stat_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32); 73 ctrl_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32); 74 rst_bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG); 75 76 spin_lock_irqsave(&rc->lock, flags); 77 stat = ~readl(rc->base + stat_offset); 78 if (set) 79 writel(stat | rst_bit, rc->base + ctrl_offset); 80 else 81 writel(stat & ~rst_bit, rc->base + ctrl_offset); 82 spin_unlock_irqrestore(&rc->lock, flags); 83 84 return 0; 85 } 86 87 static int lpc18xx_rgu_assert(struct reset_controller_dev *rcdev, 88 unsigned long id) 89 { 90 return lpc18xx_rgu_setclear_reset(rcdev, id, true); 91 } 92 93 static int lpc18xx_rgu_deassert(struct reset_controller_dev *rcdev, 94 unsigned long id) 95 { 96 return lpc18xx_rgu_setclear_reset(rcdev, id, false); 97 } 98 99 /* Only M0 cores require explicit reset deassert */ 100 static int lpc18xx_rgu_reset(struct reset_controller_dev *rcdev, 101 unsigned long id) 102 { 103 struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev); 104 105 lpc18xx_rgu_assert(rcdev, id); 106 udelay(rc->delay_us); 107 108 switch (id) { 109 case LPC43XX_RGU_M0SUB_RST: 110 case LPC43XX_RGU_M0APP_RST: 111 lpc18xx_rgu_setclear_reset(rcdev, id, false); 112 } 113 114 return 0; 115 } 116 117 static int lpc18xx_rgu_status(struct reset_controller_dev *rcdev, 118 unsigned long id) 119 { 120 struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev); 121 u32 bit, offset = LPC18XX_RGU_ACTIVE_STATUS0; 122 123 offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32); 124 bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG); 125 126 return !(readl(rc->base + offset) & bit); 127 } 128 129 static const struct reset_control_ops lpc18xx_rgu_ops = { 130 .reset = lpc18xx_rgu_reset, 131 .assert = lpc18xx_rgu_assert, 132 .deassert = lpc18xx_rgu_deassert, 133 .status = lpc18xx_rgu_status, 134 }; 135 136 static int lpc18xx_rgu_probe(struct platform_device *pdev) 137 { 138 struct lpc18xx_rgu_data *rc; 139 u32 fcclk, firc; 140 int ret; 141 142 rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL); 143 if (!rc) 144 return -ENOMEM; 145 146 rc->base = devm_platform_ioremap_resource(pdev, 0); 147 if (IS_ERR(rc->base)) 148 return PTR_ERR(rc->base); 149 150 rc->clk_reg = devm_clk_get_enabled(&pdev->dev, "reg"); 151 if (IS_ERR(rc->clk_reg)) 152 return dev_err_probe(&pdev->dev, PTR_ERR(rc->clk_reg), 153 "reg clock not found\n"); 154 155 rc->clk_delay = devm_clk_get_enabled(&pdev->dev, "delay"); 156 if (IS_ERR(rc->clk_delay)) 157 return dev_err_probe(&pdev->dev, PTR_ERR(rc->clk_delay), 158 "delay clock not found\n"); 159 160 fcclk = clk_get_rate(rc->clk_reg) / USEC_PER_SEC; 161 firc = clk_get_rate(rc->clk_delay) / USEC_PER_SEC; 162 if (fcclk == 0 || firc == 0) 163 rc->delay_us = 2; 164 else 165 rc->delay_us = DIV_ROUND_UP(fcclk, firc * firc); 166 167 spin_lock_init(&rc->lock); 168 169 rc->rcdev.owner = THIS_MODULE; 170 rc->rcdev.nr_resets = 64; 171 rc->rcdev.ops = &lpc18xx_rgu_ops; 172 rc->rcdev.of_node = pdev->dev.of_node; 173 174 ret = reset_controller_register(&rc->rcdev); 175 if (ret) 176 return dev_err_probe(&pdev->dev, ret, "unable to register device\n"); 177 178 ret = devm_register_sys_off_handler(&pdev->dev, SYS_OFF_MODE_RESTART, 192, 179 lpc18xx_rgu_restart, rc); 180 if (ret) 181 dev_warn(&pdev->dev, "failed to register restart handler\n"); 182 183 return 0; 184 } 185 186 static const struct of_device_id lpc18xx_rgu_match[] = { 187 { .compatible = "nxp,lpc1850-rgu" }, 188 { } 189 }; 190 191 static struct platform_driver lpc18xx_rgu_driver = { 192 .probe = lpc18xx_rgu_probe, 193 .driver = { 194 .name = "lpc18xx-reset", 195 .of_match_table = lpc18xx_rgu_match, 196 .suppress_bind_attrs = true, 197 }, 198 }; 199 builtin_platform_driver(lpc18xx_rgu_driver); 200