1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 Intel Corporation. 4 * Lei Chuanhua <Chuanhua.lei@intel.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/init.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/reboot.h> 12 #include <linux/regmap.h> 13 #include <linux/reset-controller.h> 14 15 #define RCU_RST_STAT 0x0024 16 #define RCU_RST_REQ 0x0048 17 18 #define REG_OFFSET_MASK GENMASK(31, 16) 19 #define BIT_OFFSET_MASK GENMASK(15, 8) 20 #define STAT_BIT_OFFSET_MASK GENMASK(7, 0) 21 22 #define to_reset_data(x) container_of(x, struct intel_reset_data, rcdev) 23 24 struct intel_reset_soc { 25 bool legacy; 26 u32 reset_cell_count; 27 }; 28 29 struct intel_reset_data { 30 struct reset_controller_dev rcdev; 31 const struct intel_reset_soc *soc_data; 32 struct regmap *regmap; 33 struct device *dev; 34 u32 reboot_id; 35 }; 36 37 static const struct regmap_config intel_rcu_regmap_config = { 38 .name = "intel-reset", 39 .reg_bits = 32, 40 .reg_stride = 4, 41 .val_bits = 32, 42 }; 43 44 /* 45 * Reset status register offset relative to 46 * the reset control register(X) is X + 4 47 */ 48 static u32 id_to_reg_and_bit_offsets(struct intel_reset_data *data, 49 unsigned long id, u32 *rst_req, 50 u32 *req_bit, u32 *stat_bit) 51 { 52 *rst_req = FIELD_GET(REG_OFFSET_MASK, id); 53 *req_bit = FIELD_GET(BIT_OFFSET_MASK, id); 54 55 if (data->soc_data->legacy) 56 *stat_bit = FIELD_GET(STAT_BIT_OFFSET_MASK, id); 57 else 58 *stat_bit = *req_bit; 59 60 if (data->soc_data->legacy && *rst_req == RCU_RST_REQ) 61 return RCU_RST_STAT; 62 else 63 return *rst_req + 0x4; 64 } 65 66 static int intel_set_clr_bits(struct intel_reset_data *data, unsigned long id, 67 bool set) 68 { 69 u32 rst_req, req_bit, rst_stat, stat_bit, val; 70 int ret; 71 72 rst_stat = id_to_reg_and_bit_offsets(data, id, &rst_req, 73 &req_bit, &stat_bit); 74 75 val = set ? BIT(req_bit) : 0; 76 ret = regmap_update_bits(data->regmap, rst_req, BIT(req_bit), val); 77 if (ret) 78 return ret; 79 80 return regmap_read_poll_timeout(data->regmap, rst_stat, val, 81 set == !!(val & BIT(stat_bit)), 20, 82 200); 83 } 84 85 static int intel_assert_device(struct reset_controller_dev *rcdev, 86 unsigned long id) 87 { 88 struct intel_reset_data *data = to_reset_data(rcdev); 89 int ret; 90 91 ret = intel_set_clr_bits(data, id, true); 92 if (ret) 93 dev_err(data->dev, "Reset assert failed %d\n", ret); 94 95 return ret; 96 } 97 98 static int intel_deassert_device(struct reset_controller_dev *rcdev, 99 unsigned long id) 100 { 101 struct intel_reset_data *data = to_reset_data(rcdev); 102 int ret; 103 104 ret = intel_set_clr_bits(data, id, false); 105 if (ret) 106 dev_err(data->dev, "Reset deassert failed %d\n", ret); 107 108 return ret; 109 } 110 111 static int intel_reset_status(struct reset_controller_dev *rcdev, 112 unsigned long id) 113 { 114 struct intel_reset_data *data = to_reset_data(rcdev); 115 u32 rst_req, req_bit, rst_stat, stat_bit, val; 116 int ret; 117 118 rst_stat = id_to_reg_and_bit_offsets(data, id, &rst_req, 119 &req_bit, &stat_bit); 120 ret = regmap_read(data->regmap, rst_stat, &val); 121 if (ret) 122 return ret; 123 124 return !!(val & BIT(stat_bit)); 125 } 126 127 static const struct reset_control_ops intel_reset_ops = { 128 .assert = intel_assert_device, 129 .deassert = intel_deassert_device, 130 .status = intel_reset_status, 131 }; 132 133 static int intel_reset_xlate(struct reset_controller_dev *rcdev, 134 const struct of_phandle_args *spec) 135 { 136 struct intel_reset_data *data = to_reset_data(rcdev); 137 u32 id; 138 139 if (spec->args[1] > 31) 140 return -EINVAL; 141 142 id = FIELD_PREP(REG_OFFSET_MASK, spec->args[0]); 143 id |= FIELD_PREP(BIT_OFFSET_MASK, spec->args[1]); 144 145 if (data->soc_data->legacy) { 146 if (spec->args[2] > 31) 147 return -EINVAL; 148 149 id |= FIELD_PREP(STAT_BIT_OFFSET_MASK, spec->args[2]); 150 } 151 152 return id; 153 } 154 155 static int intel_reset_restart_handler(struct sys_off_data *data) 156 { 157 struct intel_reset_data *reset_data = data->cb_data; 158 159 intel_assert_device(&reset_data->rcdev, reset_data->reboot_id); 160 161 return NOTIFY_DONE; 162 } 163 164 static int intel_reset_probe(struct platform_device *pdev) 165 { 166 struct device_node *np = pdev->dev.of_node; 167 struct device *dev = &pdev->dev; 168 struct intel_reset_data *data; 169 void __iomem *base; 170 u32 rb_id[3]; 171 int ret; 172 173 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 174 if (!data) 175 return -ENOMEM; 176 177 data->soc_data = of_device_get_match_data(dev); 178 if (!data->soc_data) 179 return -ENODEV; 180 181 base = devm_platform_ioremap_resource(pdev, 0); 182 if (IS_ERR(base)) 183 return PTR_ERR(base); 184 185 data->regmap = devm_regmap_init_mmio(dev, base, 186 &intel_rcu_regmap_config); 187 if (IS_ERR(data->regmap)) { 188 dev_err(dev, "regmap initialization failed\n"); 189 return PTR_ERR(data->regmap); 190 } 191 192 ret = device_property_read_u32_array(dev, "intel,global-reset", rb_id, 193 data->soc_data->reset_cell_count); 194 if (ret) { 195 dev_err(dev, "Failed to get global reset offset!\n"); 196 return ret; 197 } 198 199 data->dev = dev; 200 data->rcdev.of_node = np; 201 data->rcdev.owner = dev->driver->owner; 202 data->rcdev.ops = &intel_reset_ops; 203 data->rcdev.of_xlate = intel_reset_xlate; 204 data->rcdev.of_reset_n_cells = data->soc_data->reset_cell_count; 205 ret = devm_reset_controller_register(&pdev->dev, &data->rcdev); 206 if (ret) 207 return ret; 208 209 data->reboot_id = FIELD_PREP(REG_OFFSET_MASK, rb_id[0]); 210 data->reboot_id |= FIELD_PREP(BIT_OFFSET_MASK, rb_id[1]); 211 212 if (data->soc_data->legacy) 213 data->reboot_id |= FIELD_PREP(STAT_BIT_OFFSET_MASK, rb_id[2]); 214 215 devm_register_restart_handler(&pdev->dev, intel_reset_restart_handler, data); 216 217 return 0; 218 } 219 220 static const struct intel_reset_soc xrx200_data = { 221 .legacy = true, 222 .reset_cell_count = 3, 223 }; 224 225 static const struct intel_reset_soc lgm_data = { 226 .legacy = false, 227 .reset_cell_count = 2, 228 }; 229 230 static const struct of_device_id intel_reset_match[] = { 231 { .compatible = "intel,rcu-lgm", .data = &lgm_data }, 232 { .compatible = "intel,rcu-xrx200", .data = &xrx200_data }, 233 {} 234 }; 235 236 static struct platform_driver intel_reset_driver = { 237 .probe = intel_reset_probe, 238 .driver = { 239 .name = "intel-reset", 240 .of_match_table = intel_reset_match, 241 }, 242 }; 243 244 static int __init intel_reset_init(void) 245 { 246 return platform_driver_register(&intel_reset_driver); 247 } 248 249 /* 250 * RCU is system core entity which is in Always On Domain whose clocks 251 * or resource initialization happens in system core initialization. 252 * Also, it is required for most of the platform or architecture 253 * specific devices to perform reset operation as part of initialization. 254 * So perform RCU as post core initialization. 255 */ 256 postcore_initcall(intel_reset_init); 257