1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 Intel Corporation. 4 * Lei Chuanhua <Chuanhua.lei@intel.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/init.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/reboot.h> 12 #include <linux/regmap.h> 13 #include <linux/reset-controller.h> 14 15 #define RCU_RST_STAT 0x0024 16 #define RCU_RST_REQ 0x0048 17 18 #define REG_OFFSET_MASK GENMASK(31, 16) 19 #define BIT_OFFSET_MASK GENMASK(15, 8) 20 #define STAT_BIT_OFFSET_MASK GENMASK(7, 0) 21 22 #define to_reset_data(x) container_of(x, struct intel_reset_data, rcdev) 23 24 struct intel_reset_soc { 25 bool legacy; 26 u32 reset_cell_count; 27 }; 28 29 struct intel_reset_data { 30 struct reset_controller_dev rcdev; 31 struct notifier_block restart_nb; 32 const struct intel_reset_soc *soc_data; 33 struct regmap *regmap; 34 struct device *dev; 35 u32 reboot_id; 36 }; 37 38 static const struct regmap_config intel_rcu_regmap_config = { 39 .name = "intel-reset", 40 .reg_bits = 32, 41 .reg_stride = 4, 42 .val_bits = 32, 43 }; 44 45 /* 46 * Reset status register offset relative to 47 * the reset control register(X) is X + 4 48 */ 49 static u32 id_to_reg_and_bit_offsets(struct intel_reset_data *data, 50 unsigned long id, u32 *rst_req, 51 u32 *req_bit, u32 *stat_bit) 52 { 53 *rst_req = FIELD_GET(REG_OFFSET_MASK, id); 54 *req_bit = FIELD_GET(BIT_OFFSET_MASK, id); 55 56 if (data->soc_data->legacy) 57 *stat_bit = FIELD_GET(STAT_BIT_OFFSET_MASK, id); 58 else 59 *stat_bit = *req_bit; 60 61 if (data->soc_data->legacy && *rst_req == RCU_RST_REQ) 62 return RCU_RST_STAT; 63 else 64 return *rst_req + 0x4; 65 } 66 67 static int intel_set_clr_bits(struct intel_reset_data *data, unsigned long id, 68 bool set) 69 { 70 u32 rst_req, req_bit, rst_stat, stat_bit, val; 71 int ret; 72 73 rst_stat = id_to_reg_and_bit_offsets(data, id, &rst_req, 74 &req_bit, &stat_bit); 75 76 val = set ? BIT(req_bit) : 0; 77 ret = regmap_update_bits(data->regmap, rst_req, BIT(req_bit), val); 78 if (ret) 79 return ret; 80 81 return regmap_read_poll_timeout(data->regmap, rst_stat, val, 82 set == !!(val & BIT(stat_bit)), 20, 83 200); 84 } 85 86 static int intel_assert_device(struct reset_controller_dev *rcdev, 87 unsigned long id) 88 { 89 struct intel_reset_data *data = to_reset_data(rcdev); 90 int ret; 91 92 ret = intel_set_clr_bits(data, id, true); 93 if (ret) 94 dev_err(data->dev, "Reset assert failed %d\n", ret); 95 96 return ret; 97 } 98 99 static int intel_deassert_device(struct reset_controller_dev *rcdev, 100 unsigned long id) 101 { 102 struct intel_reset_data *data = to_reset_data(rcdev); 103 int ret; 104 105 ret = intel_set_clr_bits(data, id, false); 106 if (ret) 107 dev_err(data->dev, "Reset deassert failed %d\n", ret); 108 109 return ret; 110 } 111 112 static int intel_reset_status(struct reset_controller_dev *rcdev, 113 unsigned long id) 114 { 115 struct intel_reset_data *data = to_reset_data(rcdev); 116 u32 rst_req, req_bit, rst_stat, stat_bit, val; 117 int ret; 118 119 rst_stat = id_to_reg_and_bit_offsets(data, id, &rst_req, 120 &req_bit, &stat_bit); 121 ret = regmap_read(data->regmap, rst_stat, &val); 122 if (ret) 123 return ret; 124 125 return !!(val & BIT(stat_bit)); 126 } 127 128 static const struct reset_control_ops intel_reset_ops = { 129 .assert = intel_assert_device, 130 .deassert = intel_deassert_device, 131 .status = intel_reset_status, 132 }; 133 134 static int intel_reset_xlate(struct reset_controller_dev *rcdev, 135 const struct of_phandle_args *spec) 136 { 137 struct intel_reset_data *data = to_reset_data(rcdev); 138 u32 id; 139 140 if (spec->args[1] > 31) 141 return -EINVAL; 142 143 id = FIELD_PREP(REG_OFFSET_MASK, spec->args[0]); 144 id |= FIELD_PREP(BIT_OFFSET_MASK, spec->args[1]); 145 146 if (data->soc_data->legacy) { 147 if (spec->args[2] > 31) 148 return -EINVAL; 149 150 id |= FIELD_PREP(STAT_BIT_OFFSET_MASK, spec->args[2]); 151 } 152 153 return id; 154 } 155 156 static int intel_reset_restart_handler(struct notifier_block *nb, 157 unsigned long action, void *data) 158 { 159 struct intel_reset_data *reset_data; 160 161 reset_data = container_of(nb, struct intel_reset_data, restart_nb); 162 intel_assert_device(&reset_data->rcdev, reset_data->reboot_id); 163 164 return NOTIFY_DONE; 165 } 166 167 static int intel_reset_probe(struct platform_device *pdev) 168 { 169 struct device_node *np = pdev->dev.of_node; 170 struct device *dev = &pdev->dev; 171 struct intel_reset_data *data; 172 void __iomem *base; 173 u32 rb_id[3]; 174 int ret; 175 176 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 177 if (!data) 178 return -ENOMEM; 179 180 data->soc_data = of_device_get_match_data(dev); 181 if (!data->soc_data) 182 return -ENODEV; 183 184 base = devm_platform_ioremap_resource(pdev, 0); 185 if (IS_ERR(base)) 186 return PTR_ERR(base); 187 188 data->regmap = devm_regmap_init_mmio(dev, base, 189 &intel_rcu_regmap_config); 190 if (IS_ERR(data->regmap)) { 191 dev_err(dev, "regmap initialization failed\n"); 192 return PTR_ERR(data->regmap); 193 } 194 195 ret = device_property_read_u32_array(dev, "intel,global-reset", rb_id, 196 data->soc_data->reset_cell_count); 197 if (ret) { 198 dev_err(dev, "Failed to get global reset offset!\n"); 199 return ret; 200 } 201 202 data->dev = dev; 203 data->rcdev.of_node = np; 204 data->rcdev.owner = dev->driver->owner; 205 data->rcdev.ops = &intel_reset_ops; 206 data->rcdev.of_xlate = intel_reset_xlate; 207 data->rcdev.of_reset_n_cells = data->soc_data->reset_cell_count; 208 ret = devm_reset_controller_register(&pdev->dev, &data->rcdev); 209 if (ret) 210 return ret; 211 212 data->reboot_id = FIELD_PREP(REG_OFFSET_MASK, rb_id[0]); 213 data->reboot_id |= FIELD_PREP(BIT_OFFSET_MASK, rb_id[1]); 214 215 if (data->soc_data->legacy) 216 data->reboot_id |= FIELD_PREP(STAT_BIT_OFFSET_MASK, rb_id[2]); 217 218 data->restart_nb.notifier_call = intel_reset_restart_handler; 219 data->restart_nb.priority = 128; 220 register_restart_handler(&data->restart_nb); 221 222 return 0; 223 } 224 225 static const struct intel_reset_soc xrx200_data = { 226 .legacy = true, 227 .reset_cell_count = 3, 228 }; 229 230 static const struct intel_reset_soc lgm_data = { 231 .legacy = false, 232 .reset_cell_count = 2, 233 }; 234 235 static const struct of_device_id intel_reset_match[] = { 236 { .compatible = "intel,rcu-lgm", .data = &lgm_data }, 237 { .compatible = "intel,rcu-xrx200", .data = &xrx200_data }, 238 {} 239 }; 240 241 static struct platform_driver intel_reset_driver = { 242 .probe = intel_reset_probe, 243 .driver = { 244 .name = "intel-reset", 245 .of_match_table = intel_reset_match, 246 }, 247 }; 248 249 static int __init intel_reset_init(void) 250 { 251 return platform_driver_register(&intel_reset_driver); 252 } 253 254 /* 255 * RCU is system core entity which is in Always On Domain whose clocks 256 * or resource initialization happens in system core initialization. 257 * Also, it is required for most of the platform or architecture 258 * specific devices to perform reset operation as part of initialization. 259 * So perform RCU as post core initialization. 260 */ 261 postcore_initcall(intel_reset_init); 262