1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2024 ASPEED Technology Inc. 4 */ 5 6 #include <linux/auxiliary_bus.h> 7 #include <linux/cleanup.h> 8 #include <linux/device.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/reset-controller.h> 12 #include <linux/slab.h> 13 14 #include <dt-bindings/reset/aspeed,ast2700-scu.h> 15 16 #define SCU0_RESET_CTRL1 0x200 17 #define SCU0_RESET_CTRL2 0x220 18 #define SCU1_RESET_CTRL1 0x200 19 #define SCU1_RESET_CTRL2 0x220 20 #define SCU1_PCIE3_CTRL 0x908 21 22 struct ast2700_reset_signal { 23 bool dedicated_clr; /* dedicated reset clr offset */ 24 u32 offset, bit; 25 }; 26 27 struct aspeed_reset_info { 28 unsigned int nr_resets; 29 const struct ast2700_reset_signal *signal; 30 }; 31 32 struct aspeed_reset { 33 struct reset_controller_dev rcdev; 34 struct aspeed_reset_info *info; 35 spinlock_t lock; /* Protect read-modify-write cycle */ 36 void __iomem *base; 37 }; 38 39 static const struct ast2700_reset_signal ast2700_reset0_signals[] = { 40 [SCU0_RESET_SDRAM] = { true, SCU0_RESET_CTRL1, BIT(0) }, 41 [SCU0_RESET_DDRPHY] = { true, SCU0_RESET_CTRL1, BIT(1) }, 42 [SCU0_RESET_RSA] = { true, SCU0_RESET_CTRL1, BIT(2) }, 43 [SCU0_RESET_SHA3] = { true, SCU0_RESET_CTRL1, BIT(3) }, 44 [SCU0_RESET_HACE] = { true, SCU0_RESET_CTRL1, BIT(4) }, 45 [SCU0_RESET_SOC] = { true, SCU0_RESET_CTRL1, BIT(5) }, 46 [SCU0_RESET_VIDEO] = { true, SCU0_RESET_CTRL1, BIT(6) }, 47 [SCU0_RESET_2D] = { true, SCU0_RESET_CTRL1, BIT(7) }, 48 [SCU0_RESET_PCIS] = { true, SCU0_RESET_CTRL1, BIT(8) }, 49 [SCU0_RESET_RVAS0] = { true, SCU0_RESET_CTRL1, BIT(9) }, 50 [SCU0_RESET_RVAS1] = { true, SCU0_RESET_CTRL1, BIT(10) }, 51 [SCU0_RESET_SM3] = { true, SCU0_RESET_CTRL1, BIT(11) }, 52 [SCU0_RESET_SM4] = { true, SCU0_RESET_CTRL1, BIT(12) }, 53 [SCU0_RESET_CRT0] = { true, SCU0_RESET_CTRL1, BIT(13) }, 54 [SCU0_RESET_ECC] = { true, SCU0_RESET_CTRL1, BIT(14) }, 55 [SCU0_RESET_DP_PCI] = { true, SCU0_RESET_CTRL1, BIT(15) }, 56 [SCU0_RESET_UFS] = { true, SCU0_RESET_CTRL1, BIT(16) }, 57 [SCU0_RESET_EMMC] = { true, SCU0_RESET_CTRL1, BIT(17) }, 58 [SCU0_RESET_PCIE1RST] = { true, SCU0_RESET_CTRL1, BIT(18) }, 59 [SCU0_RESET_PCIE1RSTOE] = { true, SCU0_RESET_CTRL1, BIT(19) }, 60 [SCU0_RESET_PCIE0RST] = { true, SCU0_RESET_CTRL1, BIT(20) }, 61 [SCU0_RESET_PCIE0RSTOE] = { true, SCU0_RESET_CTRL1, BIT(21) }, 62 [SCU0_RESET_JTAG] = { true, SCU0_RESET_CTRL1, BIT(22) }, 63 [SCU0_RESET_MCTP0] = { true, SCU0_RESET_CTRL1, BIT(23) }, 64 [SCU0_RESET_MCTP1] = { true, SCU0_RESET_CTRL1, BIT(24) }, 65 [SCU0_RESET_XDMA0] = { true, SCU0_RESET_CTRL1, BIT(25) }, 66 [SCU0_RESET_XDMA1] = { true, SCU0_RESET_CTRL1, BIT(26) }, 67 [SCU0_RESET_H2X1] = { true, SCU0_RESET_CTRL1, BIT(27) }, 68 [SCU0_RESET_DP] = { true, SCU0_RESET_CTRL1, BIT(28) }, 69 [SCU0_RESET_DP_MCU] = { true, SCU0_RESET_CTRL1, BIT(29) }, 70 [SCU0_RESET_SSP] = { true, SCU0_RESET_CTRL1, BIT(30) }, 71 [SCU0_RESET_H2X0] = { true, SCU0_RESET_CTRL1, BIT(31) }, 72 [SCU0_RESET_PORTA_VHUB] = { true, SCU0_RESET_CTRL2, BIT(0) }, 73 [SCU0_RESET_PORTA_PHY3] = { true, SCU0_RESET_CTRL2, BIT(1) }, 74 [SCU0_RESET_PORTA_XHCI] = { true, SCU0_RESET_CTRL2, BIT(2) }, 75 [SCU0_RESET_PORTB_VHUB] = { true, SCU0_RESET_CTRL2, BIT(3) }, 76 [SCU0_RESET_PORTB_PHY3] = { true, SCU0_RESET_CTRL2, BIT(4) }, 77 [SCU0_RESET_PORTB_XHCI] = { true, SCU0_RESET_CTRL2, BIT(5) }, 78 [SCU0_RESET_PORTA_VHUB_EHCI] = { true, SCU0_RESET_CTRL2, BIT(6) }, 79 [SCU0_RESET_PORTB_VHUB_EHCI] = { true, SCU0_RESET_CTRL2, BIT(7) }, 80 [SCU0_RESET_UHCI] = { true, SCU0_RESET_CTRL2, BIT(8) }, 81 [SCU0_RESET_TSP] = { true, SCU0_RESET_CTRL2, BIT(9) }, 82 [SCU0_RESET_E2M0] = { true, SCU0_RESET_CTRL2, BIT(10) }, 83 [SCU0_RESET_E2M1] = { true, SCU0_RESET_CTRL2, BIT(11) }, 84 [SCU0_RESET_VLINK] = { true, SCU0_RESET_CTRL2, BIT(12) }, 85 }; 86 87 static const struct ast2700_reset_signal ast2700_reset1_signals[] = { 88 [SCU1_RESET_LPC0] = { true, SCU1_RESET_CTRL1, BIT(0) }, 89 [SCU1_RESET_LPC1] = { true, SCU1_RESET_CTRL1, BIT(1) }, 90 [SCU1_RESET_MII] = { true, SCU1_RESET_CTRL1, BIT(2) }, 91 [SCU1_RESET_PECI] = { true, SCU1_RESET_CTRL1, BIT(3) }, 92 [SCU1_RESET_PWM] = { true, SCU1_RESET_CTRL1, BIT(4) }, 93 [SCU1_RESET_MAC0] = { true, SCU1_RESET_CTRL1, BIT(5) }, 94 [SCU1_RESET_MAC1] = { true, SCU1_RESET_CTRL1, BIT(6) }, 95 [SCU1_RESET_MAC2] = { true, SCU1_RESET_CTRL1, BIT(7) }, 96 [SCU1_RESET_ADC] = { true, SCU1_RESET_CTRL1, BIT(8) }, 97 [SCU1_RESET_SD] = { true, SCU1_RESET_CTRL1, BIT(9) }, 98 [SCU1_RESET_ESPI0] = { true, SCU1_RESET_CTRL1, BIT(10) }, 99 [SCU1_RESET_ESPI1] = { true, SCU1_RESET_CTRL1, BIT(11) }, 100 [SCU1_RESET_JTAG1] = { true, SCU1_RESET_CTRL1, BIT(12) }, 101 [SCU1_RESET_SPI0] = { true, SCU1_RESET_CTRL1, BIT(13) }, 102 [SCU1_RESET_SPI1] = { true, SCU1_RESET_CTRL1, BIT(14) }, 103 [SCU1_RESET_SPI2] = { true, SCU1_RESET_CTRL1, BIT(15) }, 104 [SCU1_RESET_I3C0] = { true, SCU1_RESET_CTRL1, BIT(16) }, 105 [SCU1_RESET_I3C1] = { true, SCU1_RESET_CTRL1, BIT(17) }, 106 [SCU1_RESET_I3C2] = { true, SCU1_RESET_CTRL1, BIT(18) }, 107 [SCU1_RESET_I3C3] = { true, SCU1_RESET_CTRL1, BIT(19) }, 108 [SCU1_RESET_I3C4] = { true, SCU1_RESET_CTRL1, BIT(20) }, 109 [SCU1_RESET_I3C5] = { true, SCU1_RESET_CTRL1, BIT(21) }, 110 [SCU1_RESET_I3C6] = { true, SCU1_RESET_CTRL1, BIT(22) }, 111 [SCU1_RESET_I3C7] = { true, SCU1_RESET_CTRL1, BIT(23) }, 112 [SCU1_RESET_I3C8] = { true, SCU1_RESET_CTRL1, BIT(24) }, 113 [SCU1_RESET_I3C9] = { true, SCU1_RESET_CTRL1, BIT(25) }, 114 [SCU1_RESET_I3C10] = { true, SCU1_RESET_CTRL1, BIT(26) }, 115 [SCU1_RESET_I3C11] = { true, SCU1_RESET_CTRL1, BIT(27) }, 116 [SCU1_RESET_I3C12] = { true, SCU1_RESET_CTRL1, BIT(28) }, 117 [SCU1_RESET_I3C13] = { true, SCU1_RESET_CTRL1, BIT(29) }, 118 [SCU1_RESET_I3C14] = { true, SCU1_RESET_CTRL1, BIT(30) }, 119 [SCU1_RESET_I3C15] = { true, SCU1_RESET_CTRL1, BIT(31) }, 120 [SCU1_RESET_MCU0] = { true, SCU1_RESET_CTRL2, BIT(0) }, 121 [SCU1_RESET_MCU1] = { true, SCU1_RESET_CTRL2, BIT(1) }, 122 [SCU1_RESET_H2A_SPI1] = { true, SCU1_RESET_CTRL2, BIT(2) }, 123 [SCU1_RESET_H2A_SPI2] = { true, SCU1_RESET_CTRL2, BIT(3) }, 124 [SCU1_RESET_UART0] = { true, SCU1_RESET_CTRL2, BIT(4) }, 125 [SCU1_RESET_UART1] = { true, SCU1_RESET_CTRL2, BIT(5) }, 126 [SCU1_RESET_UART2] = { true, SCU1_RESET_CTRL2, BIT(6) }, 127 [SCU1_RESET_UART3] = { true, SCU1_RESET_CTRL2, BIT(7) }, 128 [SCU1_RESET_I2C_FILTER] = { true, SCU1_RESET_CTRL2, BIT(8) }, 129 [SCU1_RESET_CALIPTRA] = { true, SCU1_RESET_CTRL2, BIT(9) }, 130 [SCU1_RESET_XDMA] = { true, SCU1_RESET_CTRL2, BIT(10) }, 131 [SCU1_RESET_FSI] = { true, SCU1_RESET_CTRL2, BIT(12) }, 132 [SCU1_RESET_CAN] = { true, SCU1_RESET_CTRL2, BIT(13) }, 133 [SCU1_RESET_MCTP] = { true, SCU1_RESET_CTRL2, BIT(14) }, 134 [SCU1_RESET_I2C] = { true, SCU1_RESET_CTRL2, BIT(15) }, 135 [SCU1_RESET_UART6] = { true, SCU1_RESET_CTRL2, BIT(16) }, 136 [SCU1_RESET_UART7] = { true, SCU1_RESET_CTRL2, BIT(17) }, 137 [SCU1_RESET_UART8] = { true, SCU1_RESET_CTRL2, BIT(18) }, 138 [SCU1_RESET_UART9] = { true, SCU1_RESET_CTRL2, BIT(19) }, 139 [SCU1_RESET_LTPI0] = { true, SCU1_RESET_CTRL2, BIT(20) }, 140 [SCU1_RESET_VGAL] = { true, SCU1_RESET_CTRL2, BIT(21) }, 141 [SCU1_RESET_LTPI1] = { true, SCU1_RESET_CTRL2, BIT(22) }, 142 [SCU1_RESET_ACE] = { true, SCU1_RESET_CTRL2, BIT(23) }, 143 [SCU1_RESET_E2M] = { true, SCU1_RESET_CTRL2, BIT(24) }, 144 [SCU1_RESET_UHCI] = { true, SCU1_RESET_CTRL2, BIT(25) }, 145 [SCU1_RESET_PORTC_USB2UART] = { true, SCU1_RESET_CTRL2, BIT(26) }, 146 [SCU1_RESET_PORTC_VHUB_EHCI] = { true, SCU1_RESET_CTRL2, BIT(27) }, 147 [SCU1_RESET_PORTD_USB2UART] = { true, SCU1_RESET_CTRL2, BIT(28) }, 148 [SCU1_RESET_PORTD_VHUB_EHCI] = { true, SCU1_RESET_CTRL2, BIT(29) }, 149 [SCU1_RESET_H2X] = { true, SCU1_RESET_CTRL2, BIT(30) }, 150 [SCU1_RESET_I3CDMA] = { true, SCU1_RESET_CTRL2, BIT(31) }, 151 [SCU1_RESET_PCIE2RST] = { false, SCU1_PCIE3_CTRL, BIT(0) }, 152 }; 153 154 static inline struct aspeed_reset *to_aspeed_reset(struct reset_controller_dev *rcdev) 155 { 156 return container_of(rcdev, struct aspeed_reset, rcdev); 157 } 158 159 static int aspeed_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 160 { 161 struct aspeed_reset *rc = to_aspeed_reset(rcdev); 162 void __iomem *reg_offset = rc->base + rc->info->signal[id].offset; 163 164 if (rc->info->signal[id].dedicated_clr) { 165 writel(rc->info->signal[id].bit, reg_offset); 166 } else { 167 guard(spinlock_irqsave)(&rc->lock); 168 writel(readl(reg_offset) & ~rc->info->signal[id].bit, reg_offset); 169 } 170 171 return 0; 172 } 173 174 static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 175 { 176 struct aspeed_reset *rc = to_aspeed_reset(rcdev); 177 void __iomem *reg_offset = rc->base + rc->info->signal[id].offset; 178 179 if (rc->info->signal[id].dedicated_clr) { 180 writel(rc->info->signal[id].bit, reg_offset + 0x04); 181 } else { 182 guard(spinlock_irqsave)(&rc->lock); 183 writel(readl(reg_offset) | rc->info->signal[id].bit, reg_offset); 184 } 185 186 return 0; 187 } 188 189 static int aspeed_reset_status(struct reset_controller_dev *rcdev, unsigned long id) 190 { 191 struct aspeed_reset *rc = to_aspeed_reset(rcdev); 192 void __iomem *reg_offset = rc->base + rc->info->signal[id].offset; 193 194 return (readl(reg_offset) & rc->info->signal[id].bit) ? 1 : 0; 195 } 196 197 static const struct reset_control_ops aspeed_reset_ops = { 198 .assert = aspeed_reset_assert, 199 .deassert = aspeed_reset_deassert, 200 .status = aspeed_reset_status, 201 }; 202 203 static int aspeed_reset_probe(struct auxiliary_device *adev, 204 const struct auxiliary_device_id *id) 205 { 206 struct aspeed_reset *reset; 207 struct device *dev = &adev->dev; 208 209 reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); 210 if (!reset) 211 return -ENOMEM; 212 213 spin_lock_init(&reset->lock); 214 215 reset->info = (struct aspeed_reset_info *)id->driver_data; 216 reset->rcdev.owner = THIS_MODULE; 217 reset->rcdev.nr_resets = reset->info->nr_resets; 218 reset->rcdev.ops = &aspeed_reset_ops; 219 reset->rcdev.of_node = dev->parent->of_node; 220 reset->rcdev.dev = dev; 221 reset->rcdev.of_reset_n_cells = 1; 222 reset->base = (void __iomem *)adev->dev.platform_data; 223 224 return devm_reset_controller_register(dev, &reset->rcdev); 225 } 226 227 static const struct aspeed_reset_info ast2700_reset0_info = { 228 .nr_resets = ARRAY_SIZE(ast2700_reset0_signals), 229 .signal = ast2700_reset0_signals, 230 }; 231 232 static const struct aspeed_reset_info ast2700_reset1_info = { 233 .nr_resets = ARRAY_SIZE(ast2700_reset1_signals), 234 .signal = ast2700_reset1_signals, 235 }; 236 237 static const struct auxiliary_device_id aspeed_reset_ids[] = { 238 { .name = "clk_ast2700.reset0", .driver_data = (kernel_ulong_t)&ast2700_reset0_info }, 239 { .name = "clk_ast2700.reset1", .driver_data = (kernel_ulong_t)&ast2700_reset1_info }, 240 { } 241 }; 242 MODULE_DEVICE_TABLE(auxiliary, aspeed_reset_ids); 243 244 static struct auxiliary_driver aspeed_reset_driver = { 245 .probe = aspeed_reset_probe, 246 .id_table = aspeed_reset_ids, 247 }; 248 249 module_auxiliary_driver(aspeed_reset_driver); 250 251 MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>"); 252 MODULE_DESCRIPTION("ASPEED SoC Reset Controller Driver"); 253 MODULE_LICENSE("GPL"); 254