1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2025 Arm Ltd. 3 4 #ifndef MPAM_INTERNAL_H 5 #define MPAM_INTERNAL_H 6 7 #include <linux/arm_mpam.h> 8 #include <linux/cpumask.h> 9 #include <linux/io.h> 10 #include <linux/llist.h> 11 #include <linux/mutex.h> 12 #include <linux/srcu.h> 13 #include <linux/types.h> 14 15 #define MPAM_MSC_MAX_NUM_RIS 16 16 17 struct platform_device; 18 19 /* 20 * Structures protected by SRCU may not be freed for a surprising amount of 21 * time (especially if perf is running). To ensure the MPAM error interrupt can 22 * tear down all the structures, build a list of objects that can be garbage 23 * collected once synchronize_srcu() has returned. 24 * If pdev is non-NULL, use devm_kfree(). 25 */ 26 struct mpam_garbage { 27 /* member of mpam_garbage */ 28 struct llist_node llist; 29 30 void *to_free; 31 struct platform_device *pdev; 32 }; 33 34 struct mpam_msc { 35 /* member of mpam_all_msc */ 36 struct list_head all_msc_list; 37 38 int id; 39 struct platform_device *pdev; 40 41 /* Not modified after mpam_is_enabled() becomes true */ 42 enum mpam_msc_iface iface; 43 u32 nrdy_usec; 44 cpumask_t accessibility; 45 46 /* 47 * probe_lock is only taken during discovery. After discovery these 48 * properties become read-only and the lists are protected by SRCU. 49 */ 50 struct mutex probe_lock; 51 bool probed; 52 u16 partid_max; 53 u8 pmg_max; 54 unsigned long ris_idxs; 55 u32 ris_max; 56 57 /* mpam_msc_ris of this component */ 58 struct list_head ris; 59 60 /* 61 * part_sel_lock protects access to the MSC hardware registers that are 62 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary 63 * by RIS). 64 * If needed, take msc->probe_lock first. 65 */ 66 struct mutex part_sel_lock; 67 68 void __iomem *mapped_hwpage; 69 size_t mapped_hwpage_sz; 70 71 struct mpam_garbage garbage; 72 }; 73 74 struct mpam_class { 75 /* mpam_components in this class */ 76 struct list_head components; 77 78 cpumask_t affinity; 79 80 u8 level; 81 enum mpam_class_types type; 82 83 /* member of mpam_classes */ 84 struct list_head classes_list; 85 86 struct mpam_garbage garbage; 87 }; 88 89 struct mpam_component { 90 u32 comp_id; 91 92 /* mpam_vmsc in this component */ 93 struct list_head vmsc; 94 95 cpumask_t affinity; 96 97 /* member of mpam_class:components */ 98 struct list_head class_list; 99 100 /* parent: */ 101 struct mpam_class *class; 102 103 struct mpam_garbage garbage; 104 }; 105 106 struct mpam_vmsc { 107 /* member of mpam_component:vmsc_list */ 108 struct list_head comp_list; 109 110 /* mpam_msc_ris in this vmsc */ 111 struct list_head ris; 112 113 /* All RIS in this vMSC are members of this MSC */ 114 struct mpam_msc *msc; 115 116 /* parent: */ 117 struct mpam_component *comp; 118 119 struct mpam_garbage garbage; 120 }; 121 122 struct mpam_msc_ris { 123 u8 ris_idx; 124 125 cpumask_t affinity; 126 127 /* member of mpam_vmsc:ris */ 128 struct list_head vmsc_list; 129 130 /* member of mpam_msc:ris */ 131 struct list_head msc_list; 132 133 /* parent: */ 134 struct mpam_vmsc *vmsc; 135 136 struct mpam_garbage garbage; 137 }; 138 139 /* List of all classes - protected by srcu*/ 140 extern struct srcu_struct mpam_srcu; 141 extern struct list_head mpam_classes; 142 143 /* System wide partid/pmg values */ 144 extern u16 mpam_partid_max; 145 extern u8 mpam_pmg_max; 146 147 /* Scheduled work callback to enable mpam once all MSC have been probed */ 148 void mpam_enable(struct work_struct *work); 149 void mpam_disable(struct work_struct *work); 150 151 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, 152 cpumask_t *affinity); 153 154 /* 155 * MPAM MSCs have the following register layout. See: 156 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System 157 * Component Specification. 158 * https://developer.arm.com/documentation/ihi0099/aa/ 159 */ 160 #define MPAM_ARCHITECTURE_V1 0x10 161 162 /* Memory mapped control pages */ 163 /* ID Register offsets in the memory mapped page */ 164 #define MPAMF_IDR 0x0000 /* features id register */ 165 #define MPAMF_IIDR 0x0018 /* implementer id register */ 166 #define MPAMF_AIDR 0x0020 /* architectural id register */ 167 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ 168 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ 169 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ 170 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ 171 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ 172 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ 173 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ 174 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ 175 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ 176 177 /* Configuration and Status Register offsets in the memory mapped page */ 178 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ 179 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */ 180 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ 181 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ 182 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ 183 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ 184 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ 185 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ 186 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ 187 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */ 188 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ 189 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ 190 191 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ 192 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ 193 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ 194 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ 195 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ 196 #define MSMON_CSU 0x0840 /* current cache-usage */ 197 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ 198 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */ 199 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ 200 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ 201 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */ 202 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ 203 #define MPAMF_ESR 0x00F8 /* error status register */ 204 #define MPAMF_ECR 0x00F0 /* error control register */ 205 206 /* MPAMF_IDR - MPAM features ID register */ 207 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) 208 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16) 209 #define MPAMF_IDR_HAS_CCAP_PART BIT(24) 210 #define MPAMF_IDR_HAS_CPOR_PART BIT(25) 211 #define MPAMF_IDR_HAS_MBW_PART BIT(26) 212 #define MPAMF_IDR_HAS_PRI_PART BIT(27) 213 #define MPAMF_IDR_EXT BIT(28) 214 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29) 215 #define MPAMF_IDR_HAS_MSMON BIT(30) 216 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31) 217 #define MPAMF_IDR_HAS_RIS BIT(32) 218 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38) 219 #define MPAMF_IDR_HAS_ESR BIT(39) 220 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56) 221 222 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ 223 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) 224 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) 225 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) 226 227 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ 228 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) 229 230 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ 231 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) 232 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) 233 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) 234 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) 235 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30) 236 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) 237 238 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ 239 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) 240 #define MPAMF_MBW_IDR_HAS_MIN BIT(10) 241 #define MPAMF_MBW_IDR_HAS_MAX BIT(11) 242 #define MPAMF_MBW_IDR_HAS_PBM BIT(12) 243 #define MPAMF_MBW_IDR_HAS_PROP BIT(13) 244 #define MPAMF_MBW_IDR_WINDWR BIT(14) 245 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) 246 247 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ 248 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) 249 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) 250 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) 251 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) 252 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) 253 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) 254 255 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ 256 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) 257 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) 258 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) 259 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) 260 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) 261 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) 262 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30) 263 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) 264 265 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ 266 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) 267 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) 268 #define MPAMF_MBWUMON_IDR_LWD BIT(29) 269 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) 270 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) 271 272 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ 273 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) 274 275 /* MPAMF_IIDR - MPAM implementation ID register */ 276 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) 277 #define MPAMF_IIDR_REVISION GENMASK(15, 12) 278 #define MPAMF_IIDR_VARIANT GENMASK(19, 16) 279 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) 280 281 /* MPAMF_AIDR - MPAM architecture ID register */ 282 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) 283 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) 284 285 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ 286 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) 287 #define MPAMCFG_PART_SEL_INTERNAL BIT(16) 288 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) 289 290 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */ 291 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) 292 293 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */ 294 #define MPAMCFG_CMAX_SOFTLIM BIT(31) 295 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0) 296 297 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */ 298 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0) 299 300 /* 301 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration 302 * register 303 */ 304 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) 305 306 /* 307 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration 308 * register 309 */ 310 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) 311 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) 312 313 /* 314 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width 315 * register 316 */ 317 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) 318 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) 319 320 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */ 321 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0) 322 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16) 323 324 /* 325 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning 326 * configuration register 327 */ 328 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) 329 #define MPAMCFG_MBW_PROP_EN BIT(31) 330 331 /* 332 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register 333 */ 334 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) 335 #define MPAMCFG_INTPARTID_INTERNAL BIT(16) 336 337 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */ 338 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) 339 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) 340 341 /* MPAMF_ESR - MPAM Error Status Register */ 342 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0) 343 #define MPAMF_ESR_PMG GENMASK(23, 16) 344 #define MPAMF_ESR_ERRCODE GENMASK(27, 24) 345 #define MPAMF_ESR_OVRWR BIT(31) 346 #define MPAMF_ESR_RIS GENMASK(35, 32) 347 348 /* MPAMF_ECR - MPAM Error Control Register */ 349 #define MPAMF_ECR_INTEN BIT(0) 350 351 /* Error conditions in accessing memory mapped registers */ 352 #define MPAM_ERRCODE_NONE 0 353 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1 354 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2 355 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 356 #define MPAM_ERRCODE_REQ_PMG_RANGE 4 357 #define MPAM_ERRCODE_MONITOR_RANGE 5 358 #define MPAM_ERRCODE_INTPARTID_RANGE 6 359 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 360 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8 361 #define MPAM_ERRCODE_RIS_NO_CONTROL 9 362 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10 363 #define MPAM_ERRCODE_RIS_NO_MONITOR 11 364 365 /* 366 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage 367 * usage monitor control register 368 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory 369 * bandwidth usage monitor control register 370 */ 371 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) 372 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) 373 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) 374 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) 375 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19) 376 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) 377 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) 378 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) 379 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) 380 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) 381 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) 382 #define MSMON_CFG_x_CTL_EN BIT(31) 383 384 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 385 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 386 387 /* 388 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage 389 * usage monitor filter register 390 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory 391 * bandwidth usage monitor filter register 392 */ 393 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) 394 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) 395 396 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) 397 #define MSMON_CFG_CSU_FLT_XCL BIT(31) 398 399 /* 400 * MSMON_CSU - Memory system performance monitor cache storage usage monitor 401 * register 402 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage 403 * capture register 404 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage 405 * monitor register 406 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage 407 * capture register 408 */ 409 #define MSMON___VALUE GENMASK(30, 0) 410 #define MSMON___NRDY BIT(31) 411 #define MSMON___L_NRDY BIT(63) 412 #define MSMON___L_VALUE GENMASK(43, 0) 413 #define MSMON___LWD_VALUE GENMASK(62, 0) 414 415 /* 416 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event 417 * generation register 418 */ 419 #define MSMON_CAPT_EVNT_NOW BIT(0) 420 421 #endif /* MPAM_INTERNAL_H */ 422