1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2025 Arm Ltd. 3 4 #ifndef MPAM_INTERNAL_H 5 #define MPAM_INTERNAL_H 6 7 #include <linux/arm_mpam.h> 8 #include <linux/cpumask.h> 9 #include <linux/io.h> 10 #include <linux/llist.h> 11 #include <linux/mutex.h> 12 #include <linux/srcu.h> 13 #include <linux/types.h> 14 15 #define MPAM_MSC_MAX_NUM_RIS 16 16 17 struct platform_device; 18 19 /* 20 * Structures protected by SRCU may not be freed for a surprising amount of 21 * time (especially if perf is running). To ensure the MPAM error interrupt can 22 * tear down all the structures, build a list of objects that can be garbage 23 * collected once synchronize_srcu() has returned. 24 * If pdev is non-NULL, use devm_kfree(). 25 */ 26 struct mpam_garbage { 27 /* member of mpam_garbage */ 28 struct llist_node llist; 29 30 void *to_free; 31 struct platform_device *pdev; 32 }; 33 34 struct mpam_msc { 35 /* member of mpam_all_msc */ 36 struct list_head all_msc_list; 37 38 int id; 39 struct platform_device *pdev; 40 41 /* Not modified after mpam_is_enabled() becomes true */ 42 enum mpam_msc_iface iface; 43 u32 nrdy_usec; 44 cpumask_t accessibility; 45 46 /* 47 * probe_lock is only taken during discovery. After discovery these 48 * properties become read-only and the lists are protected by SRCU. 49 */ 50 struct mutex probe_lock; 51 unsigned long ris_idxs; 52 u32 ris_max; 53 54 /* mpam_msc_ris of this component */ 55 struct list_head ris; 56 57 /* 58 * part_sel_lock protects access to the MSC hardware registers that are 59 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary 60 * by RIS). 61 * If needed, take msc->probe_lock first. 62 */ 63 struct mutex part_sel_lock; 64 65 void __iomem *mapped_hwpage; 66 size_t mapped_hwpage_sz; 67 68 struct mpam_garbage garbage; 69 }; 70 71 struct mpam_class { 72 /* mpam_components in this class */ 73 struct list_head components; 74 75 cpumask_t affinity; 76 77 u8 level; 78 enum mpam_class_types type; 79 80 /* member of mpam_classes */ 81 struct list_head classes_list; 82 83 struct mpam_garbage garbage; 84 }; 85 86 struct mpam_component { 87 u32 comp_id; 88 89 /* mpam_vmsc in this component */ 90 struct list_head vmsc; 91 92 cpumask_t affinity; 93 94 /* member of mpam_class:components */ 95 struct list_head class_list; 96 97 /* parent: */ 98 struct mpam_class *class; 99 100 struct mpam_garbage garbage; 101 }; 102 103 struct mpam_vmsc { 104 /* member of mpam_component:vmsc_list */ 105 struct list_head comp_list; 106 107 /* mpam_msc_ris in this vmsc */ 108 struct list_head ris; 109 110 /* All RIS in this vMSC are members of this MSC */ 111 struct mpam_msc *msc; 112 113 /* parent: */ 114 struct mpam_component *comp; 115 116 struct mpam_garbage garbage; 117 }; 118 119 struct mpam_msc_ris { 120 u8 ris_idx; 121 122 cpumask_t affinity; 123 124 /* member of mpam_vmsc:ris */ 125 struct list_head vmsc_list; 126 127 /* member of mpam_msc:ris */ 128 struct list_head msc_list; 129 130 /* parent: */ 131 struct mpam_vmsc *vmsc; 132 133 struct mpam_garbage garbage; 134 }; 135 136 /* List of all classes - protected by srcu*/ 137 extern struct srcu_struct mpam_srcu; 138 extern struct list_head mpam_classes; 139 140 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, 141 cpumask_t *affinity); 142 143 /* 144 * MPAM MSCs have the following register layout. See: 145 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System 146 * Component Specification. 147 * https://developer.arm.com/documentation/ihi0099/aa/ 148 */ 149 #define MPAM_ARCHITECTURE_V1 0x10 150 151 /* Memory mapped control pages */ 152 /* ID Register offsets in the memory mapped page */ 153 #define MPAMF_IDR 0x0000 /* features id register */ 154 #define MPAMF_IIDR 0x0018 /* implementer id register */ 155 #define MPAMF_AIDR 0x0020 /* architectural id register */ 156 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ 157 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ 158 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ 159 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ 160 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ 161 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ 162 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ 163 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ 164 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ 165 166 /* Configuration and Status Register offsets in the memory mapped page */ 167 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ 168 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */ 169 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ 170 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ 171 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ 172 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ 173 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ 174 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ 175 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ 176 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */ 177 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ 178 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ 179 180 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ 181 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ 182 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ 183 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ 184 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ 185 #define MSMON_CSU 0x0840 /* current cache-usage */ 186 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ 187 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */ 188 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ 189 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ 190 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */ 191 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ 192 #define MPAMF_ESR 0x00F8 /* error status register */ 193 #define MPAMF_ECR 0x00F0 /* error control register */ 194 195 /* MPAMF_IDR - MPAM features ID register */ 196 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) 197 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16) 198 #define MPAMF_IDR_HAS_CCAP_PART BIT(24) 199 #define MPAMF_IDR_HAS_CPOR_PART BIT(25) 200 #define MPAMF_IDR_HAS_MBW_PART BIT(26) 201 #define MPAMF_IDR_HAS_PRI_PART BIT(27) 202 #define MPAMF_IDR_EXT BIT(28) 203 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29) 204 #define MPAMF_IDR_HAS_MSMON BIT(30) 205 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31) 206 #define MPAMF_IDR_HAS_RIS BIT(32) 207 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38) 208 #define MPAMF_IDR_HAS_ESR BIT(39) 209 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56) 210 211 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ 212 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) 213 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) 214 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) 215 216 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ 217 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) 218 219 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ 220 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) 221 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) 222 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) 223 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) 224 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30) 225 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) 226 227 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ 228 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) 229 #define MPAMF_MBW_IDR_HAS_MIN BIT(10) 230 #define MPAMF_MBW_IDR_HAS_MAX BIT(11) 231 #define MPAMF_MBW_IDR_HAS_PBM BIT(12) 232 #define MPAMF_MBW_IDR_HAS_PROP BIT(13) 233 #define MPAMF_MBW_IDR_WINDWR BIT(14) 234 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) 235 236 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ 237 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) 238 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) 239 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) 240 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) 241 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) 242 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) 243 244 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ 245 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) 246 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) 247 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) 248 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) 249 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) 250 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) 251 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30) 252 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) 253 254 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ 255 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) 256 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) 257 #define MPAMF_MBWUMON_IDR_LWD BIT(29) 258 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) 259 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) 260 261 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ 262 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) 263 264 /* MPAMF_IIDR - MPAM implementation ID register */ 265 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) 266 #define MPAMF_IIDR_REVISION GENMASK(15, 12) 267 #define MPAMF_IIDR_VARIANT GENMASK(19, 16) 268 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) 269 270 /* MPAMF_AIDR - MPAM architecture ID register */ 271 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) 272 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) 273 274 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ 275 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) 276 #define MPAMCFG_PART_SEL_INTERNAL BIT(16) 277 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) 278 279 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */ 280 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) 281 282 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */ 283 #define MPAMCFG_CMAX_SOFTLIM BIT(31) 284 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0) 285 286 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */ 287 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0) 288 289 /* 290 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration 291 * register 292 */ 293 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) 294 295 /* 296 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration 297 * register 298 */ 299 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) 300 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) 301 302 /* 303 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width 304 * register 305 */ 306 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) 307 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) 308 309 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */ 310 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0) 311 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16) 312 313 /* 314 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning 315 * configuration register 316 */ 317 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) 318 #define MPAMCFG_MBW_PROP_EN BIT(31) 319 320 /* 321 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register 322 */ 323 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) 324 #define MPAMCFG_INTPARTID_INTERNAL BIT(16) 325 326 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */ 327 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) 328 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) 329 330 /* MPAMF_ESR - MPAM Error Status Register */ 331 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0) 332 #define MPAMF_ESR_PMG GENMASK(23, 16) 333 #define MPAMF_ESR_ERRCODE GENMASK(27, 24) 334 #define MPAMF_ESR_OVRWR BIT(31) 335 #define MPAMF_ESR_RIS GENMASK(35, 32) 336 337 /* MPAMF_ECR - MPAM Error Control Register */ 338 #define MPAMF_ECR_INTEN BIT(0) 339 340 /* Error conditions in accessing memory mapped registers */ 341 #define MPAM_ERRCODE_NONE 0 342 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1 343 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2 344 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 345 #define MPAM_ERRCODE_REQ_PMG_RANGE 4 346 #define MPAM_ERRCODE_MONITOR_RANGE 5 347 #define MPAM_ERRCODE_INTPARTID_RANGE 6 348 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 349 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8 350 #define MPAM_ERRCODE_RIS_NO_CONTROL 9 351 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10 352 #define MPAM_ERRCODE_RIS_NO_MONITOR 11 353 354 /* 355 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage 356 * usage monitor control register 357 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory 358 * bandwidth usage monitor control register 359 */ 360 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) 361 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) 362 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) 363 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) 364 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19) 365 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) 366 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) 367 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) 368 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) 369 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) 370 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) 371 #define MSMON_CFG_x_CTL_EN BIT(31) 372 373 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 374 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 375 376 /* 377 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage 378 * usage monitor filter register 379 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory 380 * bandwidth usage monitor filter register 381 */ 382 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) 383 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) 384 385 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) 386 #define MSMON_CFG_CSU_FLT_XCL BIT(31) 387 388 /* 389 * MSMON_CSU - Memory system performance monitor cache storage usage monitor 390 * register 391 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage 392 * capture register 393 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage 394 * monitor register 395 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage 396 * capture register 397 */ 398 #define MSMON___VALUE GENMASK(30, 0) 399 #define MSMON___NRDY BIT(31) 400 #define MSMON___L_NRDY BIT(63) 401 #define MSMON___L_VALUE GENMASK(43, 0) 402 #define MSMON___LWD_VALUE GENMASK(62, 0) 403 404 /* 405 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event 406 * generation register 407 */ 408 #define MSMON_CAPT_EVNT_NOW BIT(0) 409 410 #endif /* MPAM_INTERNAL_H */ 411