1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2025 Arm Ltd. 3 4 #ifndef MPAM_INTERNAL_H 5 #define MPAM_INTERNAL_H 6 7 #include <linux/arm_mpam.h> 8 #include <linux/cpumask.h> 9 #include <linux/io.h> 10 #include <linux/llist.h> 11 #include <linux/mutex.h> 12 #include <linux/srcu.h> 13 #include <linux/types.h> 14 15 #define MPAM_MSC_MAX_NUM_RIS 16 16 17 struct platform_device; 18 19 /* 20 * Structures protected by SRCU may not be freed for a surprising amount of 21 * time (especially if perf is running). To ensure the MPAM error interrupt can 22 * tear down all the structures, build a list of objects that can be garbage 23 * collected once synchronize_srcu() has returned. 24 * If pdev is non-NULL, use devm_kfree(). 25 */ 26 struct mpam_garbage { 27 /* member of mpam_garbage */ 28 struct llist_node llist; 29 30 void *to_free; 31 struct platform_device *pdev; 32 }; 33 34 struct mpam_msc { 35 /* member of mpam_all_msc */ 36 struct list_head all_msc_list; 37 38 int id; 39 struct platform_device *pdev; 40 41 /* Not modified after mpam_is_enabled() becomes true */ 42 enum mpam_msc_iface iface; 43 u32 nrdy_usec; 44 cpumask_t accessibility; 45 46 /* 47 * probe_lock is only taken during discovery. After discovery these 48 * properties become read-only and the lists are protected by SRCU. 49 */ 50 struct mutex probe_lock; 51 bool probed; 52 unsigned long ris_idxs; 53 u32 ris_max; 54 55 /* mpam_msc_ris of this component */ 56 struct list_head ris; 57 58 /* 59 * part_sel_lock protects access to the MSC hardware registers that are 60 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary 61 * by RIS). 62 * If needed, take msc->probe_lock first. 63 */ 64 struct mutex part_sel_lock; 65 66 void __iomem *mapped_hwpage; 67 size_t mapped_hwpage_sz; 68 69 struct mpam_garbage garbage; 70 }; 71 72 struct mpam_class { 73 /* mpam_components in this class */ 74 struct list_head components; 75 76 cpumask_t affinity; 77 78 u8 level; 79 enum mpam_class_types type; 80 81 /* member of mpam_classes */ 82 struct list_head classes_list; 83 84 struct mpam_garbage garbage; 85 }; 86 87 struct mpam_component { 88 u32 comp_id; 89 90 /* mpam_vmsc in this component */ 91 struct list_head vmsc; 92 93 cpumask_t affinity; 94 95 /* member of mpam_class:components */ 96 struct list_head class_list; 97 98 /* parent: */ 99 struct mpam_class *class; 100 101 struct mpam_garbage garbage; 102 }; 103 104 struct mpam_vmsc { 105 /* member of mpam_component:vmsc_list */ 106 struct list_head comp_list; 107 108 /* mpam_msc_ris in this vmsc */ 109 struct list_head ris; 110 111 /* All RIS in this vMSC are members of this MSC */ 112 struct mpam_msc *msc; 113 114 /* parent: */ 115 struct mpam_component *comp; 116 117 struct mpam_garbage garbage; 118 }; 119 120 struct mpam_msc_ris { 121 u8 ris_idx; 122 123 cpumask_t affinity; 124 125 /* member of mpam_vmsc:ris */ 126 struct list_head vmsc_list; 127 128 /* member of mpam_msc:ris */ 129 struct list_head msc_list; 130 131 /* parent: */ 132 struct mpam_vmsc *vmsc; 133 134 struct mpam_garbage garbage; 135 }; 136 137 /* List of all classes - protected by srcu*/ 138 extern struct srcu_struct mpam_srcu; 139 extern struct list_head mpam_classes; 140 141 /* Scheduled work callback to enable mpam once all MSC have been probed */ 142 void mpam_enable(struct work_struct *work); 143 void mpam_disable(struct work_struct *work); 144 145 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, 146 cpumask_t *affinity); 147 148 /* 149 * MPAM MSCs have the following register layout. See: 150 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System 151 * Component Specification. 152 * https://developer.arm.com/documentation/ihi0099/aa/ 153 */ 154 #define MPAM_ARCHITECTURE_V1 0x10 155 156 /* Memory mapped control pages */ 157 /* ID Register offsets in the memory mapped page */ 158 #define MPAMF_IDR 0x0000 /* features id register */ 159 #define MPAMF_IIDR 0x0018 /* implementer id register */ 160 #define MPAMF_AIDR 0x0020 /* architectural id register */ 161 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ 162 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ 163 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ 164 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ 165 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ 166 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ 167 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ 168 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ 169 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ 170 171 /* Configuration and Status Register offsets in the memory mapped page */ 172 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ 173 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */ 174 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ 175 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ 176 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ 177 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ 178 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ 179 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ 180 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ 181 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */ 182 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ 183 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ 184 185 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ 186 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ 187 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ 188 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ 189 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ 190 #define MSMON_CSU 0x0840 /* current cache-usage */ 191 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ 192 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */ 193 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ 194 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ 195 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */ 196 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ 197 #define MPAMF_ESR 0x00F8 /* error status register */ 198 #define MPAMF_ECR 0x00F0 /* error control register */ 199 200 /* MPAMF_IDR - MPAM features ID register */ 201 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) 202 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16) 203 #define MPAMF_IDR_HAS_CCAP_PART BIT(24) 204 #define MPAMF_IDR_HAS_CPOR_PART BIT(25) 205 #define MPAMF_IDR_HAS_MBW_PART BIT(26) 206 #define MPAMF_IDR_HAS_PRI_PART BIT(27) 207 #define MPAMF_IDR_EXT BIT(28) 208 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29) 209 #define MPAMF_IDR_HAS_MSMON BIT(30) 210 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31) 211 #define MPAMF_IDR_HAS_RIS BIT(32) 212 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38) 213 #define MPAMF_IDR_HAS_ESR BIT(39) 214 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56) 215 216 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ 217 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) 218 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) 219 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) 220 221 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ 222 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) 223 224 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ 225 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) 226 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) 227 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) 228 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) 229 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30) 230 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) 231 232 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ 233 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) 234 #define MPAMF_MBW_IDR_HAS_MIN BIT(10) 235 #define MPAMF_MBW_IDR_HAS_MAX BIT(11) 236 #define MPAMF_MBW_IDR_HAS_PBM BIT(12) 237 #define MPAMF_MBW_IDR_HAS_PROP BIT(13) 238 #define MPAMF_MBW_IDR_WINDWR BIT(14) 239 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) 240 241 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ 242 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) 243 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) 244 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) 245 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) 246 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) 247 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) 248 249 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ 250 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) 251 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) 252 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) 253 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) 254 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) 255 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) 256 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30) 257 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) 258 259 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ 260 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) 261 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) 262 #define MPAMF_MBWUMON_IDR_LWD BIT(29) 263 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) 264 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) 265 266 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ 267 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) 268 269 /* MPAMF_IIDR - MPAM implementation ID register */ 270 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) 271 #define MPAMF_IIDR_REVISION GENMASK(15, 12) 272 #define MPAMF_IIDR_VARIANT GENMASK(19, 16) 273 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) 274 275 /* MPAMF_AIDR - MPAM architecture ID register */ 276 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) 277 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) 278 279 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ 280 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) 281 #define MPAMCFG_PART_SEL_INTERNAL BIT(16) 282 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) 283 284 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */ 285 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) 286 287 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */ 288 #define MPAMCFG_CMAX_SOFTLIM BIT(31) 289 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0) 290 291 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */ 292 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0) 293 294 /* 295 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration 296 * register 297 */ 298 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) 299 300 /* 301 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration 302 * register 303 */ 304 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) 305 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) 306 307 /* 308 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width 309 * register 310 */ 311 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) 312 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) 313 314 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */ 315 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0) 316 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16) 317 318 /* 319 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning 320 * configuration register 321 */ 322 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) 323 #define MPAMCFG_MBW_PROP_EN BIT(31) 324 325 /* 326 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register 327 */ 328 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) 329 #define MPAMCFG_INTPARTID_INTERNAL BIT(16) 330 331 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */ 332 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) 333 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) 334 335 /* MPAMF_ESR - MPAM Error Status Register */ 336 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0) 337 #define MPAMF_ESR_PMG GENMASK(23, 16) 338 #define MPAMF_ESR_ERRCODE GENMASK(27, 24) 339 #define MPAMF_ESR_OVRWR BIT(31) 340 #define MPAMF_ESR_RIS GENMASK(35, 32) 341 342 /* MPAMF_ECR - MPAM Error Control Register */ 343 #define MPAMF_ECR_INTEN BIT(0) 344 345 /* Error conditions in accessing memory mapped registers */ 346 #define MPAM_ERRCODE_NONE 0 347 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1 348 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2 349 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 350 #define MPAM_ERRCODE_REQ_PMG_RANGE 4 351 #define MPAM_ERRCODE_MONITOR_RANGE 5 352 #define MPAM_ERRCODE_INTPARTID_RANGE 6 353 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 354 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8 355 #define MPAM_ERRCODE_RIS_NO_CONTROL 9 356 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10 357 #define MPAM_ERRCODE_RIS_NO_MONITOR 11 358 359 /* 360 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage 361 * usage monitor control register 362 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory 363 * bandwidth usage monitor control register 364 */ 365 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) 366 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) 367 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) 368 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) 369 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19) 370 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) 371 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) 372 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) 373 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) 374 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) 375 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) 376 #define MSMON_CFG_x_CTL_EN BIT(31) 377 378 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 379 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 380 381 /* 382 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage 383 * usage monitor filter register 384 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory 385 * bandwidth usage monitor filter register 386 */ 387 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) 388 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) 389 390 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) 391 #define MSMON_CFG_CSU_FLT_XCL BIT(31) 392 393 /* 394 * MSMON_CSU - Memory system performance monitor cache storage usage monitor 395 * register 396 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage 397 * capture register 398 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage 399 * monitor register 400 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage 401 * capture register 402 */ 403 #define MSMON___VALUE GENMASK(30, 0) 404 #define MSMON___NRDY BIT(31) 405 #define MSMON___L_NRDY BIT(63) 406 #define MSMON___L_VALUE GENMASK(43, 0) 407 #define MSMON___LWD_VALUE GENMASK(62, 0) 408 409 /* 410 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event 411 * generation register 412 */ 413 #define MSMON_CAPT_EVNT_NOW BIT(0) 414 415 #endif /* MPAM_INTERNAL_H */ 416