1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2025 Arm Ltd. 3 4 #ifndef MPAM_INTERNAL_H 5 #define MPAM_INTERNAL_H 6 7 #include <linux/arm_mpam.h> 8 #include <linux/bitmap.h> 9 #include <linux/cpumask.h> 10 #include <linux/io.h> 11 #include <linux/llist.h> 12 #include <linux/mutex.h> 13 #include <linux/srcu.h> 14 #include <linux/spinlock.h> 15 #include <linux/srcu.h> 16 #include <linux/types.h> 17 18 #define MPAM_MSC_MAX_NUM_RIS 16 19 20 struct platform_device; 21 22 /* 23 * Structures protected by SRCU may not be freed for a surprising amount of 24 * time (especially if perf is running). To ensure the MPAM error interrupt can 25 * tear down all the structures, build a list of objects that can be garbage 26 * collected once synchronize_srcu() has returned. 27 * If pdev is non-NULL, use devm_kfree(). 28 */ 29 struct mpam_garbage { 30 /* member of mpam_garbage */ 31 struct llist_node llist; 32 33 void *to_free; 34 struct platform_device *pdev; 35 }; 36 37 struct mpam_msc { 38 /* member of mpam_all_msc */ 39 struct list_head all_msc_list; 40 41 int id; 42 struct platform_device *pdev; 43 44 /* Not modified after mpam_is_enabled() becomes true */ 45 enum mpam_msc_iface iface; 46 u32 nrdy_usec; 47 cpumask_t accessibility; 48 49 /* 50 * probe_lock is only taken during discovery. After discovery these 51 * properties become read-only and the lists are protected by SRCU. 52 */ 53 struct mutex probe_lock; 54 bool probed; 55 u16 partid_max; 56 u8 pmg_max; 57 unsigned long ris_idxs; 58 u32 ris_max; 59 60 /* mpam_msc_ris of this component */ 61 struct list_head ris; 62 63 /* 64 * part_sel_lock protects access to the MSC hardware registers that are 65 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary 66 * by RIS). 67 * If needed, take msc->probe_lock first. 68 */ 69 struct mutex part_sel_lock; 70 71 /* 72 * mon_sel_lock protects access to the MSC hardware registers that are 73 * affected by MPAMCFG_MON_SEL, and the mbwu_state. 74 * Access to mon_sel is needed from both process and interrupt contexts, 75 * but is complicated by firmware-backed platforms that can't make any 76 * access unless they can sleep. 77 * Always use the mpam_mon_sel_lock() helpers. 78 * Accesses to mon_sel need to be able to fail if they occur in the wrong 79 * context. 80 * If needed, take msc->probe_lock first. 81 */ 82 raw_spinlock_t _mon_sel_lock; 83 unsigned long _mon_sel_flags; 84 85 void __iomem *mapped_hwpage; 86 size_t mapped_hwpage_sz; 87 88 struct mpam_garbage garbage; 89 }; 90 91 /* Returning false here means accesses to mon_sel must fail and report an error. */ 92 static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) 93 { 94 /* Locking will require updating to support a firmware backed interface */ 95 if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO)) 96 return false; 97 98 raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); 99 return true; 100 } 101 102 static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) 103 { 104 raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); 105 } 106 107 static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) 108 { 109 lockdep_assert_held_once(&msc->_mon_sel_lock); 110 } 111 112 static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) 113 { 114 raw_spin_lock_init(&msc->_mon_sel_lock); 115 } 116 117 /* Bits for mpam features bitmaps */ 118 enum mpam_device_features { 119 mpam_feat_cpor_part, 120 mpam_feat_mbw_part, 121 mpam_feat_mbw_min, 122 mpam_feat_mbw_max, 123 mpam_feat_msmon, 124 mpam_feat_msmon_csu, 125 mpam_feat_msmon_csu_hw_nrdy, 126 mpam_feat_msmon_mbwu, 127 mpam_feat_msmon_mbwu_hw_nrdy, 128 MPAM_FEATURE_LAST 129 }; 130 131 struct mpam_props { 132 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 133 134 u16 cpbm_wd; 135 u16 mbw_pbm_bits; 136 u16 bwa_wd; 137 u16 num_csu_mon; 138 u16 num_mbwu_mon; 139 }; 140 141 #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features) 142 #define mpam_set_feature(_feat, x) set_bit(_feat, (x)->features) 143 144 struct mpam_class { 145 /* mpam_components in this class */ 146 struct list_head components; 147 148 cpumask_t affinity; 149 150 u8 level; 151 enum mpam_class_types type; 152 153 /* member of mpam_classes */ 154 struct list_head classes_list; 155 156 struct mpam_garbage garbage; 157 }; 158 159 struct mpam_component { 160 u32 comp_id; 161 162 /* mpam_vmsc in this component */ 163 struct list_head vmsc; 164 165 cpumask_t affinity; 166 167 /* member of mpam_class:components */ 168 struct list_head class_list; 169 170 /* parent: */ 171 struct mpam_class *class; 172 173 struct mpam_garbage garbage; 174 }; 175 176 struct mpam_vmsc { 177 /* member of mpam_component:vmsc_list */ 178 struct list_head comp_list; 179 180 /* mpam_msc_ris in this vmsc */ 181 struct list_head ris; 182 183 struct mpam_props props; 184 185 /* All RIS in this vMSC are members of this MSC */ 186 struct mpam_msc *msc; 187 188 /* parent: */ 189 struct mpam_component *comp; 190 191 struct mpam_garbage garbage; 192 }; 193 194 struct mpam_msc_ris { 195 u8 ris_idx; 196 u64 idr; 197 struct mpam_props props; 198 199 cpumask_t affinity; 200 201 /* member of mpam_vmsc:ris */ 202 struct list_head vmsc_list; 203 204 /* member of mpam_msc:ris */ 205 struct list_head msc_list; 206 207 /* parent: */ 208 struct mpam_vmsc *vmsc; 209 210 struct mpam_garbage garbage; 211 }; 212 213 /* List of all classes - protected by srcu*/ 214 extern struct srcu_struct mpam_srcu; 215 extern struct list_head mpam_classes; 216 217 /* System wide partid/pmg values */ 218 extern u16 mpam_partid_max; 219 extern u8 mpam_pmg_max; 220 221 /* Scheduled work callback to enable mpam once all MSC have been probed */ 222 void mpam_enable(struct work_struct *work); 223 void mpam_disable(struct work_struct *work); 224 225 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, 226 cpumask_t *affinity); 227 228 /* 229 * MPAM MSCs have the following register layout. See: 230 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System 231 * Component Specification. 232 * https://developer.arm.com/documentation/ihi0099/aa/ 233 */ 234 #define MPAM_ARCHITECTURE_V1 0x10 235 236 /* Memory mapped control pages */ 237 /* ID Register offsets in the memory mapped page */ 238 #define MPAMF_IDR 0x0000 /* features id register */ 239 #define MPAMF_IIDR 0x0018 /* implementer id register */ 240 #define MPAMF_AIDR 0x0020 /* architectural id register */ 241 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ 242 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ 243 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ 244 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ 245 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ 246 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ 247 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ 248 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ 249 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ 250 251 /* Configuration and Status Register offsets in the memory mapped page */ 252 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ 253 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */ 254 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ 255 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ 256 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ 257 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ 258 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ 259 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ 260 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ 261 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */ 262 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ 263 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ 264 265 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ 266 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ 267 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ 268 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ 269 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ 270 #define MSMON_CSU 0x0840 /* current cache-usage */ 271 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ 272 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */ 273 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ 274 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ 275 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */ 276 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ 277 #define MPAMF_ESR 0x00F8 /* error status register */ 278 #define MPAMF_ECR 0x00F0 /* error control register */ 279 280 /* MPAMF_IDR - MPAM features ID register */ 281 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) 282 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16) 283 #define MPAMF_IDR_HAS_CCAP_PART BIT(24) 284 #define MPAMF_IDR_HAS_CPOR_PART BIT(25) 285 #define MPAMF_IDR_HAS_MBW_PART BIT(26) 286 #define MPAMF_IDR_HAS_PRI_PART BIT(27) 287 #define MPAMF_IDR_EXT BIT(28) 288 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29) 289 #define MPAMF_IDR_HAS_MSMON BIT(30) 290 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31) 291 #define MPAMF_IDR_HAS_RIS BIT(32) 292 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38) 293 #define MPAMF_IDR_HAS_ESR BIT(39) 294 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56) 295 296 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ 297 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) 298 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) 299 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) 300 301 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ 302 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) 303 304 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ 305 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) 306 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) 307 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) 308 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) 309 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30) 310 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) 311 312 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ 313 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) 314 #define MPAMF_MBW_IDR_HAS_MIN BIT(10) 315 #define MPAMF_MBW_IDR_HAS_MAX BIT(11) 316 #define MPAMF_MBW_IDR_HAS_PBM BIT(12) 317 #define MPAMF_MBW_IDR_HAS_PROP BIT(13) 318 #define MPAMF_MBW_IDR_WINDWR BIT(14) 319 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) 320 321 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ 322 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) 323 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) 324 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) 325 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) 326 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) 327 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) 328 329 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ 330 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) 331 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) 332 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) 333 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) 334 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) 335 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) 336 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30) 337 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) 338 339 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ 340 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) 341 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) 342 #define MPAMF_MBWUMON_IDR_LWD BIT(29) 343 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) 344 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) 345 346 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ 347 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) 348 349 /* MPAMF_IIDR - MPAM implementation ID register */ 350 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) 351 #define MPAMF_IIDR_REVISION GENMASK(15, 12) 352 #define MPAMF_IIDR_VARIANT GENMASK(19, 16) 353 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) 354 355 /* MPAMF_AIDR - MPAM architecture ID register */ 356 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) 357 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) 358 359 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ 360 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) 361 #define MPAMCFG_PART_SEL_INTERNAL BIT(16) 362 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) 363 364 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */ 365 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) 366 367 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */ 368 #define MPAMCFG_CMAX_SOFTLIM BIT(31) 369 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0) 370 371 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */ 372 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0) 373 374 /* 375 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration 376 * register 377 */ 378 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) 379 380 /* 381 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration 382 * register 383 */ 384 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) 385 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) 386 387 /* 388 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width 389 * register 390 */ 391 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) 392 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) 393 394 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */ 395 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0) 396 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16) 397 398 /* 399 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning 400 * configuration register 401 */ 402 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) 403 #define MPAMCFG_MBW_PROP_EN BIT(31) 404 405 /* 406 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register 407 */ 408 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) 409 #define MPAMCFG_INTPARTID_INTERNAL BIT(16) 410 411 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */ 412 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) 413 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) 414 415 /* MPAMF_ESR - MPAM Error Status Register */ 416 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0) 417 #define MPAMF_ESR_PMG GENMASK(23, 16) 418 #define MPAMF_ESR_ERRCODE GENMASK(27, 24) 419 #define MPAMF_ESR_OVRWR BIT(31) 420 #define MPAMF_ESR_RIS GENMASK(35, 32) 421 422 /* MPAMF_ECR - MPAM Error Control Register */ 423 #define MPAMF_ECR_INTEN BIT(0) 424 425 /* Error conditions in accessing memory mapped registers */ 426 #define MPAM_ERRCODE_NONE 0 427 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1 428 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2 429 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 430 #define MPAM_ERRCODE_REQ_PMG_RANGE 4 431 #define MPAM_ERRCODE_MONITOR_RANGE 5 432 #define MPAM_ERRCODE_INTPARTID_RANGE 6 433 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 434 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8 435 #define MPAM_ERRCODE_RIS_NO_CONTROL 9 436 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10 437 #define MPAM_ERRCODE_RIS_NO_MONITOR 11 438 439 /* 440 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage 441 * usage monitor control register 442 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory 443 * bandwidth usage monitor control register 444 */ 445 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) 446 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) 447 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) 448 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) 449 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19) 450 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) 451 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) 452 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) 453 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) 454 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) 455 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) 456 #define MSMON_CFG_x_CTL_EN BIT(31) 457 458 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 459 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 460 461 /* 462 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage 463 * usage monitor filter register 464 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory 465 * bandwidth usage monitor filter register 466 */ 467 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) 468 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) 469 470 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) 471 #define MSMON_CFG_CSU_FLT_XCL BIT(31) 472 473 /* 474 * MSMON_CSU - Memory system performance monitor cache storage usage monitor 475 * register 476 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage 477 * capture register 478 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage 479 * monitor register 480 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage 481 * capture register 482 */ 483 #define MSMON___VALUE GENMASK(30, 0) 484 #define MSMON___NRDY BIT(31) 485 #define MSMON___L_NRDY BIT(63) 486 #define MSMON___L_VALUE GENMASK(43, 0) 487 #define MSMON___LWD_VALUE GENMASK(62, 0) 488 489 /* 490 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event 491 * generation register 492 */ 493 #define MSMON_CAPT_EVNT_NOW BIT(0) 494 495 #endif /* MPAM_INTERNAL_H */ 496