1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2025 Arm Ltd. 3 4 #ifndef MPAM_INTERNAL_H 5 #define MPAM_INTERNAL_H 6 7 #include <linux/arm_mpam.h> 8 #include <linux/atomic.h> 9 #include <linux/bitmap.h> 10 #include <linux/cpumask.h> 11 #include <linux/io.h> 12 #include <linux/jump_label.h> 13 #include <linux/llist.h> 14 #include <linux/mutex.h> 15 #include <linux/srcu.h> 16 #include <linux/spinlock.h> 17 #include <linux/srcu.h> 18 #include <linux/types.h> 19 20 #define MPAM_MSC_MAX_NUM_RIS 16 21 22 struct platform_device; 23 24 DECLARE_STATIC_KEY_FALSE(mpam_enabled); 25 26 static inline bool mpam_is_enabled(void) 27 { 28 return static_branch_likely(&mpam_enabled); 29 } 30 31 /* 32 * Structures protected by SRCU may not be freed for a surprising amount of 33 * time (especially if perf is running). To ensure the MPAM error interrupt can 34 * tear down all the structures, build a list of objects that can be garbage 35 * collected once synchronize_srcu() has returned. 36 * If pdev is non-NULL, use devm_kfree(). 37 */ 38 struct mpam_garbage { 39 /* member of mpam_garbage */ 40 struct llist_node llist; 41 42 void *to_free; 43 struct platform_device *pdev; 44 }; 45 46 struct mpam_msc { 47 /* member of mpam_all_msc */ 48 struct list_head all_msc_list; 49 50 int id; 51 struct platform_device *pdev; 52 53 /* Not modified after mpam_is_enabled() becomes true */ 54 enum mpam_msc_iface iface; 55 u32 nrdy_usec; 56 cpumask_t accessibility; 57 bool has_extd_esr; 58 59 int reenable_error_ppi; 60 struct mpam_msc * __percpu *error_dev_id; 61 62 atomic_t online_refs; 63 64 /* 65 * probe_lock is only taken during discovery. After discovery these 66 * properties become read-only and the lists are protected by SRCU. 67 */ 68 struct mutex probe_lock; 69 bool probed; 70 u16 partid_max; 71 u8 pmg_max; 72 unsigned long ris_idxs; 73 u32 ris_max; 74 75 /* 76 * error_irq_lock is taken when registering/unregistering the error 77 * interrupt and maniupulating the below flags. 78 */ 79 struct mutex error_irq_lock; 80 bool error_irq_req; 81 bool error_irq_hw_enabled; 82 83 /* mpam_msc_ris of this component */ 84 struct list_head ris; 85 86 /* 87 * part_sel_lock protects access to the MSC hardware registers that are 88 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary 89 * by RIS). 90 * If needed, take msc->probe_lock first. 91 */ 92 struct mutex part_sel_lock; 93 94 /* cfg_lock protects the msc configuration. */ 95 struct mutex cfg_lock; 96 97 /* 98 * mon_sel_lock protects access to the MSC hardware registers that are 99 * affected by MPAMCFG_MON_SEL, and the mbwu_state. 100 * Access to mon_sel is needed from both process and interrupt contexts, 101 * but is complicated by firmware-backed platforms that can't make any 102 * access unless they can sleep. 103 * Always use the mpam_mon_sel_lock() helpers. 104 * Accesses to mon_sel need to be able to fail if they occur in the wrong 105 * context. 106 * If needed, take msc->probe_lock first. 107 */ 108 raw_spinlock_t _mon_sel_lock; 109 unsigned long _mon_sel_flags; 110 111 void __iomem *mapped_hwpage; 112 size_t mapped_hwpage_sz; 113 114 struct mpam_garbage garbage; 115 }; 116 117 /* Returning false here means accesses to mon_sel must fail and report an error. */ 118 static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) 119 { 120 /* Locking will require updating to support a firmware backed interface */ 121 if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO)) 122 return false; 123 124 raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); 125 return true; 126 } 127 128 static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) 129 { 130 raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); 131 } 132 133 static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) 134 { 135 lockdep_assert_held_once(&msc->_mon_sel_lock); 136 } 137 138 static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) 139 { 140 raw_spin_lock_init(&msc->_mon_sel_lock); 141 } 142 143 /* Bits for mpam features bitmaps */ 144 enum mpam_device_features { 145 mpam_feat_cpor_part, 146 mpam_feat_cmax_softlim, 147 mpam_feat_cmax_cmax, 148 mpam_feat_cmax_cmin, 149 mpam_feat_cmax_cassoc, 150 mpam_feat_mbw_part, 151 mpam_feat_mbw_min, 152 mpam_feat_mbw_max, 153 mpam_feat_mbw_prop, 154 mpam_feat_intpri_part, 155 mpam_feat_intpri_part_0_low, 156 mpam_feat_dspri_part, 157 mpam_feat_dspri_part_0_low, 158 mpam_feat_msmon, 159 mpam_feat_msmon_csu, 160 mpam_feat_msmon_csu_capture, 161 mpam_feat_msmon_csu_xcl, 162 mpam_feat_msmon_csu_hw_nrdy, 163 mpam_feat_msmon_mbwu, 164 mpam_feat_msmon_mbwu_capture, 165 mpam_feat_msmon_mbwu_rwbw, 166 mpam_feat_msmon_mbwu_hw_nrdy, 167 mpam_feat_partid_nrw, 168 MPAM_FEATURE_LAST 169 }; 170 171 struct mpam_props { 172 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 173 174 u16 cpbm_wd; 175 u16 mbw_pbm_bits; 176 u16 bwa_wd; 177 u16 cmax_wd; 178 u16 cassoc_wd; 179 u16 intpri_wd; 180 u16 dspri_wd; 181 u16 num_csu_mon; 182 u16 num_mbwu_mon; 183 }; 184 185 #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features) 186 #define mpam_set_feature(_feat, x) set_bit(_feat, (x)->features) 187 #define mpam_clear_feature(_feat, x) clear_bit(_feat, (x)->features) 188 189 /* The values for MSMON_CFG_MBWU_FLT.RWBW */ 190 enum mon_filter_options { 191 COUNT_BOTH = 0, 192 COUNT_WRITE = 1, 193 COUNT_READ = 2, 194 }; 195 196 struct mon_cfg { 197 u16 mon; 198 u8 pmg; 199 bool match_pmg; 200 bool csu_exclude_clean; 201 u32 partid; 202 enum mon_filter_options opts; 203 }; 204 205 struct mpam_class { 206 /* mpam_components in this class */ 207 struct list_head components; 208 209 cpumask_t affinity; 210 211 struct mpam_props props; 212 u32 nrdy_usec; 213 u8 level; 214 enum mpam_class_types type; 215 216 /* member of mpam_classes */ 217 struct list_head classes_list; 218 219 struct ida ida_csu_mon; 220 struct ida ida_mbwu_mon; 221 222 struct mpam_garbage garbage; 223 }; 224 225 struct mpam_config { 226 /* Which configuration values are valid. */ 227 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 228 229 u32 cpbm; 230 u32 mbw_pbm; 231 u16 mbw_max; 232 233 bool reset_cpbm; 234 bool reset_mbw_pbm; 235 bool reset_mbw_max; 236 237 struct mpam_garbage garbage; 238 }; 239 240 struct mpam_component { 241 u32 comp_id; 242 243 /* mpam_vmsc in this component */ 244 struct list_head vmsc; 245 246 cpumask_t affinity; 247 248 /* 249 * Array of configuration values, indexed by partid. 250 * Read from cpuhp callbacks, hold the cpuhp lock when writing. 251 */ 252 struct mpam_config *cfg; 253 254 /* member of mpam_class:components */ 255 struct list_head class_list; 256 257 /* parent: */ 258 struct mpam_class *class; 259 260 struct mpam_garbage garbage; 261 }; 262 263 struct mpam_vmsc { 264 /* member of mpam_component:vmsc_list */ 265 struct list_head comp_list; 266 267 /* mpam_msc_ris in this vmsc */ 268 struct list_head ris; 269 270 struct mpam_props props; 271 272 /* All RIS in this vMSC are members of this MSC */ 273 struct mpam_msc *msc; 274 275 /* parent: */ 276 struct mpam_component *comp; 277 278 struct mpam_garbage garbage; 279 }; 280 281 struct mpam_msc_ris { 282 u8 ris_idx; 283 u64 idr; 284 struct mpam_props props; 285 bool in_reset_state; 286 287 cpumask_t affinity; 288 289 /* member of mpam_vmsc:ris */ 290 struct list_head vmsc_list; 291 292 /* member of mpam_msc:ris */ 293 struct list_head msc_list; 294 295 /* parent: */ 296 struct mpam_vmsc *vmsc; 297 298 struct mpam_garbage garbage; 299 }; 300 301 static inline int mpam_alloc_csu_mon(struct mpam_class *class) 302 { 303 struct mpam_props *cprops = &class->props; 304 305 if (!mpam_has_feature(mpam_feat_msmon_csu, cprops)) 306 return -EOPNOTSUPP; 307 308 return ida_alloc_max(&class->ida_csu_mon, cprops->num_csu_mon - 1, 309 GFP_KERNEL); 310 } 311 312 static inline void mpam_free_csu_mon(struct mpam_class *class, int csu_mon) 313 { 314 ida_free(&class->ida_csu_mon, csu_mon); 315 } 316 317 static inline int mpam_alloc_mbwu_mon(struct mpam_class *class) 318 { 319 struct mpam_props *cprops = &class->props; 320 321 if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops)) 322 return -EOPNOTSUPP; 323 324 return ida_alloc_max(&class->ida_mbwu_mon, cprops->num_mbwu_mon - 1, 325 GFP_KERNEL); 326 } 327 328 static inline void mpam_free_mbwu_mon(struct mpam_class *class, int mbwu_mon) 329 { 330 ida_free(&class->ida_mbwu_mon, mbwu_mon); 331 } 332 333 /* List of all classes - protected by srcu*/ 334 extern struct srcu_struct mpam_srcu; 335 extern struct list_head mpam_classes; 336 337 /* System wide partid/pmg values */ 338 extern u16 mpam_partid_max; 339 extern u8 mpam_pmg_max; 340 341 /* Scheduled work callback to enable mpam once all MSC have been probed */ 342 void mpam_enable(struct work_struct *work); 343 void mpam_disable(struct work_struct *work); 344 345 int mpam_apply_config(struct mpam_component *comp, u16 partid, 346 struct mpam_config *cfg); 347 348 int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx, 349 enum mpam_device_features, u64 *val); 350 351 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, 352 cpumask_t *affinity); 353 354 /* 355 * MPAM MSCs have the following register layout. See: 356 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System 357 * Component Specification. 358 * https://developer.arm.com/documentation/ihi0099/aa/ 359 */ 360 #define MPAM_ARCHITECTURE_V1 0x10 361 362 /* Memory mapped control pages */ 363 /* ID Register offsets in the memory mapped page */ 364 #define MPAMF_IDR 0x0000 /* features id register */ 365 #define MPAMF_IIDR 0x0018 /* implementer id register */ 366 #define MPAMF_AIDR 0x0020 /* architectural id register */ 367 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ 368 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ 369 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ 370 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ 371 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ 372 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ 373 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ 374 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ 375 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ 376 377 /* Configuration and Status Register offsets in the memory mapped page */ 378 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ 379 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */ 380 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ 381 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ 382 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ 383 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ 384 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ 385 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ 386 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ 387 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */ 388 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ 389 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ 390 391 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ 392 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ 393 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ 394 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ 395 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ 396 #define MSMON_CSU 0x0840 /* current cache-usage */ 397 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ 398 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */ 399 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ 400 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ 401 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */ 402 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ 403 #define MPAMF_ESR 0x00F8 /* error status register */ 404 #define MPAMF_ECR 0x00F0 /* error control register */ 405 406 /* MPAMF_IDR - MPAM features ID register */ 407 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) 408 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16) 409 #define MPAMF_IDR_HAS_CCAP_PART BIT(24) 410 #define MPAMF_IDR_HAS_CPOR_PART BIT(25) 411 #define MPAMF_IDR_HAS_MBW_PART BIT(26) 412 #define MPAMF_IDR_HAS_PRI_PART BIT(27) 413 #define MPAMF_IDR_EXT BIT(28) 414 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29) 415 #define MPAMF_IDR_HAS_MSMON BIT(30) 416 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31) 417 #define MPAMF_IDR_HAS_RIS BIT(32) 418 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38) 419 #define MPAMF_IDR_HAS_ESR BIT(39) 420 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56) 421 422 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ 423 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) 424 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) 425 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) 426 427 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ 428 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) 429 430 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ 431 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) 432 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) 433 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) 434 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) 435 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30) 436 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) 437 438 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ 439 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) 440 #define MPAMF_MBW_IDR_HAS_MIN BIT(10) 441 #define MPAMF_MBW_IDR_HAS_MAX BIT(11) 442 #define MPAMF_MBW_IDR_HAS_PBM BIT(12) 443 #define MPAMF_MBW_IDR_HAS_PROP BIT(13) 444 #define MPAMF_MBW_IDR_WINDWR BIT(14) 445 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) 446 447 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ 448 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) 449 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) 450 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) 451 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) 452 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) 453 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) 454 455 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ 456 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) 457 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) 458 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) 459 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) 460 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) 461 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) 462 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30) 463 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) 464 465 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ 466 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) 467 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) 468 #define MPAMF_MBWUMON_IDR_LWD BIT(29) 469 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) 470 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) 471 472 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ 473 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) 474 475 /* MPAMF_IIDR - MPAM implementation ID register */ 476 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) 477 #define MPAMF_IIDR_REVISION GENMASK(15, 12) 478 #define MPAMF_IIDR_VARIANT GENMASK(19, 16) 479 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) 480 481 /* MPAMF_AIDR - MPAM architecture ID register */ 482 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) 483 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) 484 485 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ 486 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) 487 #define MPAMCFG_PART_SEL_INTERNAL BIT(16) 488 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) 489 490 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */ 491 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) 492 493 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */ 494 #define MPAMCFG_CMAX_SOFTLIM BIT(31) 495 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0) 496 497 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */ 498 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0) 499 500 /* 501 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration 502 * register 503 */ 504 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) 505 506 /* 507 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration 508 * register 509 */ 510 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) 511 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) 512 513 /* 514 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width 515 * register 516 */ 517 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) 518 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) 519 520 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */ 521 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0) 522 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16) 523 524 /* 525 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning 526 * configuration register 527 */ 528 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) 529 #define MPAMCFG_MBW_PROP_EN BIT(31) 530 531 /* 532 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register 533 */ 534 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) 535 #define MPAMCFG_INTPARTID_INTERNAL BIT(16) 536 537 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */ 538 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) 539 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) 540 541 /* MPAMF_ESR - MPAM Error Status Register */ 542 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0) 543 #define MPAMF_ESR_PMG GENMASK(23, 16) 544 #define MPAMF_ESR_ERRCODE GENMASK(27, 24) 545 #define MPAMF_ESR_OVRWR BIT(31) 546 #define MPAMF_ESR_RIS GENMASK(35, 32) 547 548 /* MPAMF_ECR - MPAM Error Control Register */ 549 #define MPAMF_ECR_INTEN BIT(0) 550 551 /* Error conditions in accessing memory mapped registers */ 552 #define MPAM_ERRCODE_NONE 0 553 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1 554 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2 555 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 556 #define MPAM_ERRCODE_REQ_PMG_RANGE 4 557 #define MPAM_ERRCODE_MONITOR_RANGE 5 558 #define MPAM_ERRCODE_INTPARTID_RANGE 6 559 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 560 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8 561 #define MPAM_ERRCODE_RIS_NO_CONTROL 9 562 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10 563 #define MPAM_ERRCODE_RIS_NO_MONITOR 11 564 565 /* 566 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage 567 * usage monitor control register 568 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory 569 * bandwidth usage monitor control register 570 */ 571 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) 572 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) 573 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) 574 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) 575 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19) 576 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) 577 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) 578 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) 579 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) 580 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) 581 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) 582 #define MSMON_CFG_x_CTL_EN BIT(31) 583 584 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 585 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 586 587 /* 588 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage 589 * usage monitor filter register 590 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory 591 * bandwidth usage monitor filter register 592 */ 593 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) 594 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) 595 596 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) 597 #define MSMON_CFG_CSU_FLT_XCL BIT(31) 598 599 /* 600 * MSMON_CSU - Memory system performance monitor cache storage usage monitor 601 * register 602 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage 603 * capture register 604 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage 605 * monitor register 606 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage 607 * capture register 608 */ 609 #define MSMON___VALUE GENMASK(30, 0) 610 #define MSMON___NRDY BIT(31) 611 #define MSMON___L_NRDY BIT(63) 612 #define MSMON___L_VALUE GENMASK(43, 0) 613 #define MSMON___LWD_VALUE GENMASK(62, 0) 614 615 /* 616 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event 617 * generation register 618 */ 619 #define MSMON_CAPT_EVNT_NOW BIT(0) 620 621 #endif /* MPAM_INTERNAL_H */ 622