1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2025 Arm Ltd. 3 4 #ifndef MPAM_INTERNAL_H 5 #define MPAM_INTERNAL_H 6 7 #include <linux/arm_mpam.h> 8 #include <linux/atomic.h> 9 #include <linux/bitmap.h> 10 #include <linux/cpumask.h> 11 #include <linux/io.h> 12 #include <linux/jump_label.h> 13 #include <linux/llist.h> 14 #include <linux/mutex.h> 15 #include <linux/srcu.h> 16 #include <linux/spinlock.h> 17 #include <linux/srcu.h> 18 #include <linux/types.h> 19 20 #define MPAM_MSC_MAX_NUM_RIS 16 21 22 struct platform_device; 23 24 DECLARE_STATIC_KEY_FALSE(mpam_enabled); 25 26 #ifdef CONFIG_MPAM_KUNIT_TEST 27 #define PACKED_FOR_KUNIT __packed 28 #else 29 #define PACKED_FOR_KUNIT 30 #endif 31 32 static inline bool mpam_is_enabled(void) 33 { 34 return static_branch_likely(&mpam_enabled); 35 } 36 37 /* 38 * Structures protected by SRCU may not be freed for a surprising amount of 39 * time (especially if perf is running). To ensure the MPAM error interrupt can 40 * tear down all the structures, build a list of objects that can be garbage 41 * collected once synchronize_srcu() has returned. 42 * If pdev is non-NULL, use devm_kfree(). 43 */ 44 struct mpam_garbage { 45 /* member of mpam_garbage */ 46 struct llist_node llist; 47 48 void *to_free; 49 struct platform_device *pdev; 50 }; 51 52 struct mpam_msc { 53 /* member of mpam_all_msc */ 54 struct list_head all_msc_list; 55 56 int id; 57 struct platform_device *pdev; 58 59 /* Not modified after mpam_is_enabled() becomes true */ 60 enum mpam_msc_iface iface; 61 u32 nrdy_usec; 62 cpumask_t accessibility; 63 bool has_extd_esr; 64 65 int reenable_error_ppi; 66 struct mpam_msc * __percpu *error_dev_id; 67 68 atomic_t online_refs; 69 70 /* 71 * probe_lock is only taken during discovery. After discovery these 72 * properties become read-only and the lists are protected by SRCU. 73 */ 74 struct mutex probe_lock; 75 bool probed; 76 u16 partid_max; 77 u8 pmg_max; 78 unsigned long ris_idxs; 79 u32 ris_max; 80 81 /* 82 * error_irq_lock is taken when registering/unregistering the error 83 * interrupt and maniupulating the below flags. 84 */ 85 struct mutex error_irq_lock; 86 bool error_irq_req; 87 bool error_irq_hw_enabled; 88 89 /* mpam_msc_ris of this component */ 90 struct list_head ris; 91 92 /* 93 * part_sel_lock protects access to the MSC hardware registers that are 94 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary 95 * by RIS). 96 * If needed, take msc->probe_lock first. 97 */ 98 struct mutex part_sel_lock; 99 100 /* 101 * cfg_lock protects the msc configuration and guards against mbwu_state 102 * save and restore racing. 103 */ 104 struct mutex cfg_lock; 105 106 /* 107 * mon_sel_lock protects access to the MSC hardware registers that are 108 * affected by MPAMCFG_MON_SEL, and the mbwu_state. 109 * Access to mon_sel is needed from both process and interrupt contexts, 110 * but is complicated by firmware-backed platforms that can't make any 111 * access unless they can sleep. 112 * Always use the mpam_mon_sel_lock() helpers. 113 * Accesses to mon_sel need to be able to fail if they occur in the wrong 114 * context. 115 * If needed, take msc->probe_lock first. 116 */ 117 raw_spinlock_t _mon_sel_lock; 118 unsigned long _mon_sel_flags; 119 120 void __iomem *mapped_hwpage; 121 size_t mapped_hwpage_sz; 122 123 struct mpam_garbage garbage; 124 }; 125 126 /* Returning false here means accesses to mon_sel must fail and report an error. */ 127 static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) 128 { 129 /* Locking will require updating to support a firmware backed interface */ 130 if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO)) 131 return false; 132 133 raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); 134 return true; 135 } 136 137 static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) 138 { 139 raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); 140 } 141 142 static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) 143 { 144 lockdep_assert_held_once(&msc->_mon_sel_lock); 145 } 146 147 static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) 148 { 149 raw_spin_lock_init(&msc->_mon_sel_lock); 150 } 151 152 /* Bits for mpam features bitmaps */ 153 enum mpam_device_features { 154 mpam_feat_cpor_part, 155 mpam_feat_cmax_softlim, 156 mpam_feat_cmax_cmax, 157 mpam_feat_cmax_cmin, 158 mpam_feat_cmax_cassoc, 159 mpam_feat_mbw_part, 160 mpam_feat_mbw_min, 161 mpam_feat_mbw_max, 162 mpam_feat_mbw_prop, 163 mpam_feat_intpri_part, 164 mpam_feat_intpri_part_0_low, 165 mpam_feat_dspri_part, 166 mpam_feat_dspri_part_0_low, 167 mpam_feat_msmon, 168 mpam_feat_msmon_csu, 169 mpam_feat_msmon_csu_capture, 170 mpam_feat_msmon_csu_xcl, 171 mpam_feat_msmon_csu_hw_nrdy, 172 mpam_feat_msmon_mbwu, 173 mpam_feat_msmon_mbwu_31counter, 174 mpam_feat_msmon_mbwu_44counter, 175 mpam_feat_msmon_mbwu_63counter, 176 mpam_feat_msmon_mbwu_capture, 177 mpam_feat_msmon_mbwu_rwbw, 178 mpam_feat_msmon_mbwu_hw_nrdy, 179 mpam_feat_partid_nrw, 180 MPAM_FEATURE_LAST 181 }; 182 183 struct mpam_props { 184 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 185 186 u16 cpbm_wd; 187 u16 mbw_pbm_bits; 188 u16 bwa_wd; 189 u16 cmax_wd; 190 u16 cassoc_wd; 191 u16 intpri_wd; 192 u16 dspri_wd; 193 u16 num_csu_mon; 194 u16 num_mbwu_mon; 195 196 /* 197 * Kunit tests use memset() to set up feature combinations that should be 198 * removed, and will false-positive if the compiler introduces padding that 199 * isn't cleared during sanitisation. 200 */ 201 } PACKED_FOR_KUNIT; 202 203 #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features) 204 #define mpam_set_feature(_feat, x) set_bit(_feat, (x)->features) 205 #define mpam_clear_feature(_feat, x) clear_bit(_feat, (x)->features) 206 207 /* The values for MSMON_CFG_MBWU_FLT.RWBW */ 208 enum mon_filter_options { 209 COUNT_BOTH = 0, 210 COUNT_WRITE = 1, 211 COUNT_READ = 2, 212 }; 213 214 struct mon_cfg { 215 u16 mon; 216 u8 pmg; 217 bool match_pmg; 218 bool csu_exclude_clean; 219 u32 partid; 220 enum mon_filter_options opts; 221 }; 222 223 /* Changes to msmon_mbwu_state are protected by the msc's mon_sel_lock. */ 224 struct msmon_mbwu_state { 225 bool enabled; 226 bool reset_on_next_read; 227 struct mon_cfg cfg; 228 229 /* 230 * The value to add to the new reading to account for power management, 231 * and overflow. 232 */ 233 u64 correction; 234 235 struct mpam_garbage garbage; 236 }; 237 238 struct mpam_class { 239 /* mpam_components in this class */ 240 struct list_head components; 241 242 cpumask_t affinity; 243 244 struct mpam_props props; 245 u32 nrdy_usec; 246 u8 level; 247 enum mpam_class_types type; 248 249 /* member of mpam_classes */ 250 struct list_head classes_list; 251 252 struct ida ida_csu_mon; 253 struct ida ida_mbwu_mon; 254 255 struct mpam_garbage garbage; 256 }; 257 258 struct mpam_config { 259 /* Which configuration values are valid. */ 260 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 261 262 u32 cpbm; 263 u32 mbw_pbm; 264 u16 mbw_max; 265 266 bool reset_cpbm; 267 bool reset_mbw_pbm; 268 bool reset_mbw_max; 269 270 struct mpam_garbage garbage; 271 }; 272 273 struct mpam_component { 274 u32 comp_id; 275 276 /* mpam_vmsc in this component */ 277 struct list_head vmsc; 278 279 cpumask_t affinity; 280 281 /* 282 * Array of configuration values, indexed by partid. 283 * Read from cpuhp callbacks, hold the cpuhp lock when writing. 284 */ 285 struct mpam_config *cfg; 286 287 /* member of mpam_class:components */ 288 struct list_head class_list; 289 290 /* parent: */ 291 struct mpam_class *class; 292 293 struct mpam_garbage garbage; 294 }; 295 296 struct mpam_vmsc { 297 /* member of mpam_component:vmsc_list */ 298 struct list_head comp_list; 299 300 /* mpam_msc_ris in this vmsc */ 301 struct list_head ris; 302 303 struct mpam_props props; 304 305 /* All RIS in this vMSC are members of this MSC */ 306 struct mpam_msc *msc; 307 308 /* parent: */ 309 struct mpam_component *comp; 310 311 struct mpam_garbage garbage; 312 }; 313 314 struct mpam_msc_ris { 315 u8 ris_idx; 316 u64 idr; 317 struct mpam_props props; 318 bool in_reset_state; 319 320 cpumask_t affinity; 321 322 /* member of mpam_vmsc:ris */ 323 struct list_head vmsc_list; 324 325 /* member of mpam_msc:ris */ 326 struct list_head msc_list; 327 328 /* parent: */ 329 struct mpam_vmsc *vmsc; 330 331 /* msmon mbwu configuration is preserved over reset */ 332 struct msmon_mbwu_state *mbwu_state; 333 334 struct mpam_garbage garbage; 335 }; 336 337 static inline int mpam_alloc_csu_mon(struct mpam_class *class) 338 { 339 struct mpam_props *cprops = &class->props; 340 341 if (!mpam_has_feature(mpam_feat_msmon_csu, cprops)) 342 return -EOPNOTSUPP; 343 344 return ida_alloc_max(&class->ida_csu_mon, cprops->num_csu_mon - 1, 345 GFP_KERNEL); 346 } 347 348 static inline void mpam_free_csu_mon(struct mpam_class *class, int csu_mon) 349 { 350 ida_free(&class->ida_csu_mon, csu_mon); 351 } 352 353 static inline int mpam_alloc_mbwu_mon(struct mpam_class *class) 354 { 355 struct mpam_props *cprops = &class->props; 356 357 if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops)) 358 return -EOPNOTSUPP; 359 360 return ida_alloc_max(&class->ida_mbwu_mon, cprops->num_mbwu_mon - 1, 361 GFP_KERNEL); 362 } 363 364 static inline void mpam_free_mbwu_mon(struct mpam_class *class, int mbwu_mon) 365 { 366 ida_free(&class->ida_mbwu_mon, mbwu_mon); 367 } 368 369 /* List of all classes - protected by srcu*/ 370 extern struct srcu_struct mpam_srcu; 371 extern struct list_head mpam_classes; 372 373 /* System wide partid/pmg values */ 374 extern u16 mpam_partid_max; 375 extern u8 mpam_pmg_max; 376 377 /* Scheduled work callback to enable mpam once all MSC have been probed */ 378 void mpam_enable(struct work_struct *work); 379 void mpam_disable(struct work_struct *work); 380 381 int mpam_apply_config(struct mpam_component *comp, u16 partid, 382 struct mpam_config *cfg); 383 384 int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx, 385 enum mpam_device_features, u64 *val); 386 void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ctx); 387 388 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, 389 cpumask_t *affinity); 390 391 /* 392 * MPAM MSCs have the following register layout. See: 393 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System 394 * Component Specification. 395 * https://developer.arm.com/documentation/ihi0099/aa/ 396 */ 397 #define MPAM_ARCHITECTURE_V1 0x10 398 399 /* Memory mapped control pages */ 400 /* ID Register offsets in the memory mapped page */ 401 #define MPAMF_IDR 0x0000 /* features id register */ 402 #define MPAMF_IIDR 0x0018 /* implementer id register */ 403 #define MPAMF_AIDR 0x0020 /* architectural id register */ 404 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ 405 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ 406 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ 407 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ 408 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ 409 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ 410 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ 411 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ 412 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ 413 414 /* Configuration and Status Register offsets in the memory mapped page */ 415 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ 416 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */ 417 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ 418 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ 419 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ 420 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ 421 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ 422 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ 423 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ 424 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */ 425 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ 426 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ 427 428 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ 429 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ 430 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ 431 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ 432 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ 433 #define MSMON_CSU 0x0840 /* current cache-usage */ 434 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ 435 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */ 436 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ 437 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ 438 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */ 439 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ 440 #define MPAMF_ESR 0x00F8 /* error status register */ 441 #define MPAMF_ECR 0x00F0 /* error control register */ 442 443 /* MPAMF_IDR - MPAM features ID register */ 444 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) 445 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16) 446 #define MPAMF_IDR_HAS_CCAP_PART BIT(24) 447 #define MPAMF_IDR_HAS_CPOR_PART BIT(25) 448 #define MPAMF_IDR_HAS_MBW_PART BIT(26) 449 #define MPAMF_IDR_HAS_PRI_PART BIT(27) 450 #define MPAMF_IDR_EXT BIT(28) 451 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29) 452 #define MPAMF_IDR_HAS_MSMON BIT(30) 453 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31) 454 #define MPAMF_IDR_HAS_RIS BIT(32) 455 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38) 456 #define MPAMF_IDR_HAS_ESR BIT(39) 457 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56) 458 459 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ 460 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) 461 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) 462 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) 463 464 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ 465 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) 466 467 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ 468 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) 469 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) 470 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) 471 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) 472 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30) 473 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) 474 475 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ 476 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) 477 #define MPAMF_MBW_IDR_HAS_MIN BIT(10) 478 #define MPAMF_MBW_IDR_HAS_MAX BIT(11) 479 #define MPAMF_MBW_IDR_HAS_PBM BIT(12) 480 #define MPAMF_MBW_IDR_HAS_PROP BIT(13) 481 #define MPAMF_MBW_IDR_WINDWR BIT(14) 482 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) 483 484 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ 485 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) 486 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) 487 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) 488 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) 489 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) 490 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) 491 492 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ 493 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) 494 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) 495 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) 496 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) 497 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) 498 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) 499 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30) 500 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) 501 502 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ 503 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) 504 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) 505 #define MPAMF_MBWUMON_IDR_LWD BIT(29) 506 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) 507 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) 508 509 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ 510 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) 511 512 /* MPAMF_IIDR - MPAM implementation ID register */ 513 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) 514 #define MPAMF_IIDR_REVISION GENMASK(15, 12) 515 #define MPAMF_IIDR_VARIANT GENMASK(19, 16) 516 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) 517 518 /* MPAMF_AIDR - MPAM architecture ID register */ 519 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) 520 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) 521 522 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ 523 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) 524 #define MPAMCFG_PART_SEL_INTERNAL BIT(16) 525 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) 526 527 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */ 528 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) 529 530 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */ 531 #define MPAMCFG_CMAX_SOFTLIM BIT(31) 532 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0) 533 534 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */ 535 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0) 536 537 /* 538 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration 539 * register 540 */ 541 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) 542 543 /* 544 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration 545 * register 546 */ 547 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) 548 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) 549 550 /* 551 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width 552 * register 553 */ 554 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) 555 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) 556 557 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */ 558 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0) 559 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16) 560 561 /* 562 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning 563 * configuration register 564 */ 565 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) 566 #define MPAMCFG_MBW_PROP_EN BIT(31) 567 568 /* 569 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register 570 */ 571 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) 572 #define MPAMCFG_INTPARTID_INTERNAL BIT(16) 573 574 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */ 575 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) 576 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) 577 578 /* MPAMF_ESR - MPAM Error Status Register */ 579 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0) 580 #define MPAMF_ESR_PMG GENMASK(23, 16) 581 #define MPAMF_ESR_ERRCODE GENMASK(27, 24) 582 #define MPAMF_ESR_OVRWR BIT(31) 583 #define MPAMF_ESR_RIS GENMASK(35, 32) 584 585 /* MPAMF_ECR - MPAM Error Control Register */ 586 #define MPAMF_ECR_INTEN BIT(0) 587 588 /* Error conditions in accessing memory mapped registers */ 589 #define MPAM_ERRCODE_NONE 0 590 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1 591 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2 592 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 593 #define MPAM_ERRCODE_REQ_PMG_RANGE 4 594 #define MPAM_ERRCODE_MONITOR_RANGE 5 595 #define MPAM_ERRCODE_INTPARTID_RANGE 6 596 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 597 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8 598 #define MPAM_ERRCODE_RIS_NO_CONTROL 9 599 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10 600 #define MPAM_ERRCODE_RIS_NO_MONITOR 11 601 602 /* 603 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage 604 * usage monitor control register 605 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory 606 * bandwidth usage monitor control register 607 */ 608 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) 609 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) 610 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) 611 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) 612 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19) 613 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) 614 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) 615 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) 616 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) 617 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) 618 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) 619 #define MSMON_CFG_x_CTL_EN BIT(31) 620 621 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 622 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 623 624 /* 625 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage 626 * usage monitor filter register 627 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory 628 * bandwidth usage monitor filter register 629 */ 630 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) 631 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) 632 633 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) 634 #define MSMON_CFG_CSU_FLT_XCL BIT(31) 635 636 /* 637 * MSMON_CSU - Memory system performance monitor cache storage usage monitor 638 * register 639 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage 640 * capture register 641 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage 642 * monitor register 643 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage 644 * capture register 645 */ 646 #define MSMON___VALUE GENMASK(30, 0) 647 #define MSMON___NRDY BIT(31) 648 #define MSMON___L_NRDY BIT(63) 649 #define MSMON___L_VALUE GENMASK(43, 0) 650 #define MSMON___LWD_VALUE GENMASK(62, 0) 651 652 /* 653 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event 654 * generation register 655 */ 656 #define MSMON_CAPT_EVNT_NOW BIT(0) 657 658 #endif /* MPAM_INTERNAL_H */ 659