1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2025 Arm Ltd. 3 4 #ifndef MPAM_INTERNAL_H 5 #define MPAM_INTERNAL_H 6 7 #include <linux/arm_mpam.h> 8 #include <linux/atomic.h> 9 #include <linux/bitmap.h> 10 #include <linux/cpumask.h> 11 #include <linux/io.h> 12 #include <linux/jump_label.h> 13 #include <linux/llist.h> 14 #include <linux/mutex.h> 15 #include <linux/resctrl.h> 16 #include <linux/spinlock.h> 17 #include <linux/srcu.h> 18 #include <linux/types.h> 19 20 #include <asm/mpam.h> 21 22 #define MPAM_MSC_MAX_NUM_RIS 16 23 24 struct platform_device; 25 26 #ifdef CONFIG_MPAM_KUNIT_TEST 27 #define PACKED_FOR_KUNIT __packed 28 #else 29 #define PACKED_FOR_KUNIT 30 #endif 31 32 /* 33 * This 'mon' values must not alias an actual monitor, so must be larger than 34 * U16_MAX, but not be confused with an errno value, so smaller than 35 * (u32)-SZ_4K. 36 * USE_PRE_ALLOCATED is used to avoid confusion with an actual monitor. 37 */ 38 #define USE_PRE_ALLOCATED (U16_MAX + 1) 39 40 static inline bool mpam_is_enabled(void) 41 { 42 return static_branch_likely(&mpam_enabled); 43 } 44 45 /* 46 * Structures protected by SRCU may not be freed for a surprising amount of 47 * time (especially if perf is running). To ensure the MPAM error interrupt can 48 * tear down all the structures, build a list of objects that can be garbage 49 * collected once synchronize_srcu() has returned. 50 * If pdev is non-NULL, use devm_kfree(). 51 */ 52 struct mpam_garbage { 53 /* member of mpam_garbage */ 54 struct llist_node llist; 55 56 void *to_free; 57 struct platform_device *pdev; 58 }; 59 60 struct mpam_msc { 61 /* member of mpam_all_msc */ 62 struct list_head all_msc_list; 63 64 int id; 65 struct platform_device *pdev; 66 67 /* Not modified after mpam_is_enabled() becomes true */ 68 enum mpam_msc_iface iface; 69 u32 nrdy_usec; 70 cpumask_t accessibility; 71 bool has_extd_esr; 72 73 int reenable_error_ppi; 74 struct mpam_msc * __percpu *error_dev_id; 75 76 atomic_t online_refs; 77 78 /* 79 * probe_lock is only taken during discovery. After discovery these 80 * properties become read-only and the lists are protected by SRCU. 81 */ 82 struct mutex probe_lock; 83 bool probed; 84 u16 partid_max; 85 u8 pmg_max; 86 unsigned long ris_idxs; 87 u32 ris_max; 88 u32 iidr; 89 u16 quirks; 90 91 /* 92 * error_irq_lock is taken when registering/unregistering the error 93 * interrupt and maniupulating the below flags. 94 */ 95 struct mutex error_irq_lock; 96 bool error_irq_req; 97 bool error_irq_hw_enabled; 98 99 /* mpam_msc_ris of this component */ 100 struct list_head ris; 101 102 /* 103 * part_sel_lock protects access to the MSC hardware registers that are 104 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary 105 * by RIS). 106 * If needed, take msc->probe_lock first. 107 */ 108 struct mutex part_sel_lock; 109 110 /* 111 * cfg_lock protects the msc configuration and guards against mbwu_state 112 * save and restore racing. 113 */ 114 struct mutex cfg_lock; 115 116 /* 117 * mon_sel_lock protects access to the MSC hardware registers that are 118 * affected by MPAMCFG_MON_SEL, and the mbwu_state. 119 * Access to mon_sel is needed from both process and interrupt contexts, 120 * but is complicated by firmware-backed platforms that can't make any 121 * access unless they can sleep. 122 * Always use the mpam_mon_sel_lock() helpers. 123 * Accesses to mon_sel need to be able to fail if they occur in the wrong 124 * context. 125 * If needed, take msc->probe_lock first. 126 */ 127 raw_spinlock_t _mon_sel_lock; 128 unsigned long _mon_sel_flags; 129 130 void __iomem *mapped_hwpage; 131 size_t mapped_hwpage_sz; 132 133 /* Values only used on some platforms for quirks */ 134 u32 t241_id; 135 136 struct mpam_garbage garbage; 137 }; 138 139 /* Returning false here means accesses to mon_sel must fail and report an error. */ 140 static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) 141 { 142 /* Locking will require updating to support a firmware backed interface */ 143 if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO)) 144 return false; 145 146 raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); 147 return true; 148 } 149 150 static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) 151 { 152 raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); 153 } 154 155 static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) 156 { 157 lockdep_assert_held_once(&msc->_mon_sel_lock); 158 } 159 160 static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) 161 { 162 raw_spin_lock_init(&msc->_mon_sel_lock); 163 } 164 165 /* Bits for mpam features bitmaps */ 166 enum mpam_device_features { 167 mpam_feat_cpor_part, 168 mpam_feat_cmax_softlim, 169 mpam_feat_cmax_cmax, 170 mpam_feat_cmax_cmin, 171 mpam_feat_cmax_cassoc, 172 mpam_feat_mbw_part, 173 mpam_feat_mbw_min, 174 mpam_feat_mbw_max, 175 mpam_feat_mbw_prop, 176 mpam_feat_intpri_part, 177 mpam_feat_intpri_part_0_low, 178 mpam_feat_dspri_part, 179 mpam_feat_dspri_part_0_low, 180 mpam_feat_msmon, 181 mpam_feat_msmon_csu, 182 mpam_feat_msmon_csu_capture, 183 mpam_feat_msmon_csu_xcl, 184 mpam_feat_msmon_mbwu, 185 mpam_feat_msmon_mbwu_31counter, 186 mpam_feat_msmon_mbwu_44counter, 187 mpam_feat_msmon_mbwu_63counter, 188 mpam_feat_msmon_mbwu_capture, 189 mpam_feat_msmon_mbwu_rwbw, 190 mpam_feat_partid_nrw, 191 MPAM_FEATURE_LAST 192 }; 193 194 struct mpam_props { 195 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 196 197 u16 cpbm_wd; 198 u16 mbw_pbm_bits; 199 u16 bwa_wd; 200 u16 cmax_wd; 201 u16 cassoc_wd; 202 u16 intpri_wd; 203 u16 dspri_wd; 204 u16 num_csu_mon; 205 u16 num_mbwu_mon; 206 207 /* 208 * Kunit tests use memset() to set up feature combinations that should be 209 * removed, and will false-positive if the compiler introduces padding that 210 * isn't cleared during sanitisation. 211 */ 212 } PACKED_FOR_KUNIT; 213 214 #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features) 215 /* 216 * The non-atomic get/set operations are used because if struct mpam_props is 217 * packed, the alignment requirements for atomics aren't met. 218 */ 219 #define mpam_set_feature(_feat, x) __set_bit(_feat, (x)->features) 220 #define mpam_clear_feature(_feat, x) __clear_bit(_feat, (x)->features) 221 222 /* Workaround bits for msc->quirks */ 223 enum mpam_device_quirks { 224 T241_SCRUB_SHADOW_REGS, 225 T241_FORCE_MBW_MIN_TO_ONE, 226 T241_MBW_COUNTER_SCALE_64, 227 IGNORE_CSU_NRDY, 228 MPAM_QUIRK_LAST 229 }; 230 231 #define mpam_has_quirk(_quirk, x) ((1 << (_quirk) & (x)->quirks)) 232 #define mpam_set_quirk(_quirk, x) ((x)->quirks |= (1 << (_quirk))) 233 234 struct mpam_quirk { 235 int (*init)(struct mpam_msc *msc, const struct mpam_quirk *quirk); 236 237 u32 iidr; 238 u32 iidr_mask; 239 240 enum mpam_device_quirks workaround; 241 }; 242 243 #define MPAM_IIDR_MATCH_ONE (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0xfff) | \ 244 FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0xf) | \ 245 FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0xf) | \ 246 FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0xfff)) 247 248 #define MPAM_IIDR_NVIDIA_T241 (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0x241) | \ 249 FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0) | \ 250 FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0) | \ 251 FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x36b)) 252 253 #define MPAM_IIDR_ARM_CMN_650 (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0) | \ 254 FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0) | \ 255 FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0) | \ 256 FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x43b)) 257 258 /* The values for MSMON_CFG_MBWU_FLT.RWBW */ 259 enum mon_filter_options { 260 COUNT_BOTH = 0, 261 COUNT_WRITE = 1, 262 COUNT_READ = 2, 263 }; 264 265 struct mon_cfg { 266 /* 267 * mon must be large enough to hold out of range values like 268 * USE_PRE_ALLOCATED 269 */ 270 u32 mon; 271 u8 pmg; 272 bool match_pmg; 273 bool csu_exclude_clean; 274 u32 partid; 275 enum mon_filter_options opts; 276 }; 277 278 /* Changes to msmon_mbwu_state are protected by the msc's mon_sel_lock. */ 279 struct msmon_mbwu_state { 280 bool enabled; 281 bool reset_on_next_read; 282 struct mon_cfg cfg; 283 284 /* 285 * The value to add to the new reading to account for power management, 286 * and overflow. 287 */ 288 u64 correction; 289 290 struct mpam_garbage garbage; 291 }; 292 293 struct mpam_class { 294 /* mpam_components in this class */ 295 struct list_head components; 296 297 cpumask_t affinity; 298 299 struct mpam_props props; 300 u32 nrdy_usec; 301 u16 quirks; 302 u8 level; 303 enum mpam_class_types type; 304 305 /* member of mpam_classes */ 306 struct list_head classes_list; 307 308 struct ida ida_csu_mon; 309 struct ida ida_mbwu_mon; 310 311 struct mpam_garbage garbage; 312 }; 313 314 struct mpam_config { 315 /* Which configuration values are valid. */ 316 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 317 318 u32 cpbm; 319 u32 mbw_pbm; 320 u16 mbw_max; 321 322 struct mpam_garbage garbage; 323 }; 324 325 struct mpam_component { 326 u32 comp_id; 327 328 /* mpam_vmsc in this component */ 329 struct list_head vmsc; 330 331 cpumask_t affinity; 332 333 /* 334 * Array of configuration values, indexed by partid. 335 * Read from cpuhp callbacks, hold the cpuhp lock when writing. 336 */ 337 struct mpam_config *cfg; 338 339 /* member of mpam_class:components */ 340 struct list_head class_list; 341 342 /* parent: */ 343 struct mpam_class *class; 344 345 struct mpam_garbage garbage; 346 }; 347 348 struct mpam_vmsc { 349 /* member of mpam_component:vmsc_list */ 350 struct list_head comp_list; 351 352 /* mpam_msc_ris in this vmsc */ 353 struct list_head ris; 354 355 struct mpam_props props; 356 357 /* All RIS in this vMSC are members of this MSC */ 358 struct mpam_msc *msc; 359 360 /* parent: */ 361 struct mpam_component *comp; 362 363 struct mpam_garbage garbage; 364 }; 365 366 struct mpam_msc_ris { 367 u8 ris_idx; 368 u64 idr; 369 struct mpam_props props; 370 bool in_reset_state; 371 372 cpumask_t affinity; 373 374 /* member of mpam_vmsc:ris */ 375 struct list_head vmsc_list; 376 377 /* member of mpam_msc:ris */ 378 struct list_head msc_list; 379 380 /* parent: */ 381 struct mpam_vmsc *vmsc; 382 383 /* msmon mbwu configuration is preserved over reset */ 384 struct msmon_mbwu_state *mbwu_state; 385 386 struct mpam_garbage garbage; 387 }; 388 389 struct mpam_resctrl_dom { 390 struct mpam_component *ctrl_comp; 391 392 /* 393 * There is no single mon_comp because different events may be backed 394 * by different class/components. mon_comp is indexed by the event 395 * number. 396 */ 397 struct mpam_component *mon_comp[QOS_NUM_EVENTS]; 398 399 struct rdt_ctrl_domain resctrl_ctrl_dom; 400 struct rdt_l3_mon_domain resctrl_mon_dom; 401 }; 402 403 struct mpam_resctrl_res { 404 struct mpam_class *class; 405 struct rdt_resource resctrl_res; 406 bool cdp_enabled; 407 }; 408 409 struct mpam_resctrl_mon { 410 struct mpam_class *class; 411 412 /* Array of allocated MBWU monitors, indexed by (closid, rmid). */ 413 int *mbwu_idx_to_mon; 414 415 /* Array of assigned MBWU monitors, indexed by resctrl's cntr_id. */ 416 int *assigned_counters; 417 }; 418 419 static inline int mpam_alloc_csu_mon(struct mpam_class *class) 420 { 421 struct mpam_props *cprops = &class->props; 422 423 if (!mpam_has_feature(mpam_feat_msmon_csu, cprops)) 424 return -EOPNOTSUPP; 425 426 return ida_alloc_max(&class->ida_csu_mon, cprops->num_csu_mon - 1, 427 GFP_KERNEL); 428 } 429 430 static inline void mpam_free_csu_mon(struct mpam_class *class, int csu_mon) 431 { 432 ida_free(&class->ida_csu_mon, csu_mon); 433 } 434 435 static inline int mpam_alloc_mbwu_mon(struct mpam_class *class) 436 { 437 struct mpam_props *cprops = &class->props; 438 439 if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops)) 440 return -EOPNOTSUPP; 441 442 return ida_alloc_max(&class->ida_mbwu_mon, cprops->num_mbwu_mon - 1, 443 GFP_KERNEL); 444 } 445 446 static inline void mpam_free_mbwu_mon(struct mpam_class *class, int mbwu_mon) 447 { 448 ida_free(&class->ida_mbwu_mon, mbwu_mon); 449 } 450 451 /* List of all classes - protected by srcu*/ 452 extern struct srcu_struct mpam_srcu; 453 extern struct list_head mpam_classes; 454 455 /* System wide partid/pmg values */ 456 extern u16 mpam_partid_max; 457 extern u8 mpam_pmg_max; 458 459 /* Scheduled work callback to enable mpam once all MSC have been probed */ 460 void mpam_enable(struct work_struct *work); 461 void mpam_disable(struct work_struct *work); 462 463 /* Reset all the RIS in a class under cpus_read_lock() */ 464 void mpam_reset_class_locked(struct mpam_class *class); 465 466 int mpam_apply_config(struct mpam_component *comp, u16 partid, 467 struct mpam_config *cfg); 468 469 int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx, 470 enum mpam_device_features, u64 *val); 471 void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ctx); 472 473 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, 474 cpumask_t *affinity); 475 476 #ifdef CONFIG_RESCTRL_FS 477 int mpam_resctrl_setup(void); 478 void mpam_resctrl_exit(void); 479 int mpam_resctrl_online_cpu(unsigned int cpu); 480 void mpam_resctrl_offline_cpu(unsigned int cpu); 481 void mpam_resctrl_teardown_class(struct mpam_class *class); 482 #else 483 static inline int mpam_resctrl_setup(void) { return 0; } 484 static inline void mpam_resctrl_exit(void) { } 485 static inline int mpam_resctrl_online_cpu(unsigned int cpu) { return 0; } 486 static inline void mpam_resctrl_offline_cpu(unsigned int cpu) { } 487 static inline void mpam_resctrl_teardown_class(struct mpam_class *class) { } 488 #endif /* CONFIG_RESCTRL_FS */ 489 490 /* 491 * MPAM MSCs have the following register layout. See: 492 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System 493 * Component Specification. 494 * https://developer.arm.com/documentation/ihi0099/aa/ 495 */ 496 #define MPAM_ARCHITECTURE_V1 0x10 497 498 /* Memory mapped control pages */ 499 /* ID Register offsets in the memory mapped page */ 500 #define MPAMF_IDR 0x0000 /* features id register */ 501 #define MPAMF_IIDR 0x0018 /* implementer id register */ 502 #define MPAMF_AIDR 0x0020 /* architectural id register */ 503 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ 504 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ 505 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ 506 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ 507 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ 508 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ 509 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ 510 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ 511 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ 512 513 /* Configuration and Status Register offsets in the memory mapped page */ 514 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ 515 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */ 516 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ 517 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ 518 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ 519 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ 520 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ 521 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ 522 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ 523 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */ 524 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ 525 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ 526 527 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ 528 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ 529 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ 530 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ 531 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ 532 #define MSMON_CSU 0x0840 /* current cache-usage */ 533 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ 534 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */ 535 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ 536 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ 537 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */ 538 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ 539 #define MPAMF_ESR 0x00F8 /* error status register */ 540 #define MPAMF_ECR 0x00F0 /* error control register */ 541 542 /* MPAMF_IDR - MPAM features ID register */ 543 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) 544 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16) 545 #define MPAMF_IDR_HAS_CCAP_PART BIT(24) 546 #define MPAMF_IDR_HAS_CPOR_PART BIT(25) 547 #define MPAMF_IDR_HAS_MBW_PART BIT(26) 548 #define MPAMF_IDR_HAS_PRI_PART BIT(27) 549 #define MPAMF_IDR_EXT BIT(28) 550 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29) 551 #define MPAMF_IDR_HAS_MSMON BIT(30) 552 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31) 553 #define MPAMF_IDR_HAS_RIS BIT(32) 554 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38) 555 #define MPAMF_IDR_HAS_ESR BIT(39) 556 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56) 557 558 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ 559 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) 560 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) 561 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) 562 563 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ 564 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) 565 566 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ 567 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) 568 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) 569 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) 570 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) 571 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30) 572 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) 573 574 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ 575 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) 576 #define MPAMF_MBW_IDR_HAS_MIN BIT(10) 577 #define MPAMF_MBW_IDR_HAS_MAX BIT(11) 578 #define MPAMF_MBW_IDR_HAS_PBM BIT(12) 579 #define MPAMF_MBW_IDR_HAS_PROP BIT(13) 580 #define MPAMF_MBW_IDR_WINDWR BIT(14) 581 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) 582 583 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ 584 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) 585 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) 586 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) 587 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) 588 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) 589 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) 590 591 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ 592 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) 593 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) 594 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) 595 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) 596 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) 597 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) 598 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30) 599 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) 600 601 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ 602 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) 603 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) 604 #define MPAMF_MBWUMON_IDR_LWD BIT(29) 605 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) 606 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) 607 608 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ 609 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) 610 611 /* MPAMF_IIDR - MPAM implementation ID register */ 612 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) 613 #define MPAMF_IIDR_REVISION GENMASK(15, 12) 614 #define MPAMF_IIDR_VARIANT GENMASK(19, 16) 615 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) 616 617 /* MPAMF_AIDR - MPAM architecture ID register */ 618 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) 619 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) 620 621 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ 622 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) 623 #define MPAMCFG_PART_SEL_INTERNAL BIT(16) 624 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) 625 626 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */ 627 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) 628 629 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */ 630 #define MPAMCFG_CMAX_SOFTLIM BIT(31) 631 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0) 632 633 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */ 634 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0) 635 636 /* 637 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration 638 * register 639 */ 640 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) 641 642 /* 643 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration 644 * register 645 */ 646 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) 647 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) 648 649 /* 650 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width 651 * register 652 */ 653 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) 654 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) 655 656 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */ 657 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0) 658 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16) 659 660 /* 661 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning 662 * configuration register 663 */ 664 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) 665 #define MPAMCFG_MBW_PROP_EN BIT(31) 666 667 /* 668 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register 669 */ 670 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) 671 #define MPAMCFG_INTPARTID_INTERNAL BIT(16) 672 673 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */ 674 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) 675 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) 676 677 /* MPAMF_ESR - MPAM Error Status Register */ 678 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0) 679 #define MPAMF_ESR_PMG GENMASK(23, 16) 680 #define MPAMF_ESR_ERRCODE GENMASK(27, 24) 681 #define MPAMF_ESR_OVRWR BIT(31) 682 #define MPAMF_ESR_RIS GENMASK(35, 32) 683 684 /* MPAMF_ECR - MPAM Error Control Register */ 685 #define MPAMF_ECR_INTEN BIT(0) 686 687 /* Error conditions in accessing memory mapped registers */ 688 #define MPAM_ERRCODE_NONE 0 689 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1 690 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2 691 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 692 #define MPAM_ERRCODE_REQ_PMG_RANGE 4 693 #define MPAM_ERRCODE_MONITOR_RANGE 5 694 #define MPAM_ERRCODE_INTPARTID_RANGE 6 695 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 696 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8 697 #define MPAM_ERRCODE_RIS_NO_CONTROL 9 698 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10 699 #define MPAM_ERRCODE_RIS_NO_MONITOR 11 700 701 /* 702 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage 703 * usage monitor control register 704 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory 705 * bandwidth usage monitor control register 706 */ 707 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) 708 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) 709 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) 710 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) 711 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19) 712 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) 713 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) 714 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) 715 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) 716 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) 717 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) 718 #define MSMON_CFG_x_CTL_EN BIT(31) 719 720 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 721 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 722 723 /* 724 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage 725 * usage monitor filter register 726 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory 727 * bandwidth usage monitor filter register 728 */ 729 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) 730 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) 731 732 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) 733 #define MSMON_CFG_CSU_FLT_XCL BIT(31) 734 735 /* 736 * MSMON_CSU - Memory system performance monitor cache storage usage monitor 737 * register 738 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage 739 * capture register 740 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage 741 * monitor register 742 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage 743 * capture register 744 */ 745 #define MSMON___VALUE GENMASK(30, 0) 746 #define MSMON___NRDY BIT(31) 747 #define MSMON___L_NRDY BIT(63) 748 #define MSMON___L_VALUE GENMASK(43, 0) 749 #define MSMON___LWD_VALUE GENMASK(62, 0) 750 751 /* 752 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event 753 * generation register 754 */ 755 #define MSMON_CAPT_EVNT_NOW BIT(0) 756 757 #endif /* MPAM_INTERNAL_H */ 758