1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2025 Arm Ltd. 3 4 #ifndef MPAM_INTERNAL_H 5 #define MPAM_INTERNAL_H 6 7 #include <linux/arm_mpam.h> 8 #include <linux/atomic.h> 9 #include <linux/bitmap.h> 10 #include <linux/cpumask.h> 11 #include <linux/io.h> 12 #include <linux/jump_label.h> 13 #include <linux/llist.h> 14 #include <linux/mailbox_client.h> 15 #include <linux/mutex.h> 16 #include <linux/resctrl.h> 17 #include <linux/spinlock.h> 18 #include <linux/srcu.h> 19 #include <linux/types.h> 20 21 #include <asm/mpam.h> 22 23 #define MPAM_MSC_MAX_NUM_RIS 16 24 25 struct platform_device; 26 27 #ifdef CONFIG_MPAM_KUNIT_TEST 28 #define PACKED_FOR_KUNIT __packed 29 #else 30 #define PACKED_FOR_KUNIT 31 #endif 32 33 /* 34 * This 'mon' values must not alias an actual monitor, so must be larger than 35 * U16_MAX, but not be confused with an errno value, so smaller than 36 * (u32)-SZ_4K. 37 * USE_PRE_ALLOCATED is used to avoid confusion with an actual monitor. 38 */ 39 #define USE_PRE_ALLOCATED (U16_MAX + 1) 40 41 static inline bool mpam_is_enabled(void) 42 { 43 return static_branch_likely(&mpam_enabled); 44 } 45 46 /* 47 * Structures protected by SRCU may not be freed for a surprising amount of 48 * time (especially if perf is running). To ensure the MPAM error interrupt can 49 * tear down all the structures, build a list of objects that can be garbage 50 * collected once synchronize_srcu() has returned. 51 * If pdev is non-NULL, use devm_kfree(). 52 */ 53 struct mpam_garbage { 54 /* member of mpam_garbage */ 55 struct llist_node llist; 56 57 void *to_free; 58 struct platform_device *pdev; 59 }; 60 61 struct mpam_pcc_chan { 62 struct list_head pcc_chans; 63 struct mbox_client pcc_cl; 64 struct pcc_mbox_chan *pcc_chan; 65 struct mutex pcc_chan_lock; /* only one message at a time */ 66 struct kref refcount; 67 int subspace_id; 68 }; 69 70 struct mpam_msc { 71 /* member of mpam_all_msc */ 72 struct list_head all_msc_list; 73 74 int id; 75 struct platform_device *pdev; 76 77 /* Not modified after mpam_is_enabled() becomes true */ 78 enum mpam_msc_iface iface; 79 struct mpam_pcc_chan *pcc_chan; 80 int fb_id; 81 u32 nrdy_usec; 82 cpumask_t accessibility; 83 bool has_extd_esr; 84 85 int reenable_error_ppi; 86 struct mpam_msc * __percpu *error_dev_id; 87 88 atomic_t online_refs; 89 90 /* 91 * probe_lock is only taken during discovery. After discovery these 92 * properties become read-only and the lists are protected by SRCU. 93 */ 94 struct mutex probe_lock; 95 bool probed; 96 u16 partid_max; 97 u8 pmg_max; 98 unsigned long ris_idxs; 99 u32 ris_max; 100 u32 iidr; 101 u16 quirks; 102 103 /* 104 * error_irq_lock is taken when registering/unregistering the error 105 * interrupt and maniupulating the below flags. 106 */ 107 struct mutex error_irq_lock; 108 bool error_irq_req; 109 bool error_irq_hw_enabled; 110 111 /* mpam_msc_ris of this component */ 112 struct list_head ris; 113 114 /* 115 * part_sel_lock protects access to the MSC hardware registers that are 116 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary 117 * by RIS). 118 * If needed, take msc->probe_lock first. 119 */ 120 struct mutex part_sel_lock; 121 122 /* 123 * cfg_lock protects the msc configuration and guards against mbwu_state 124 * save and restore racing. 125 */ 126 struct mutex cfg_lock; 127 128 /* 129 * mon_sel_lock protects access to the MSC hardware registers that are 130 * affected by MPAMCFG_MON_SEL, and the mbwu_state. 131 * Access to mon_sel is needed from both process and interrupt contexts, 132 * but is complicated by firmware-backed platforms that can't make any 133 * access unless they can sleep. 134 * Always use the mpam_mon_sel_lock() helpers. 135 * Accesses to mon_sel need to be able to fail if they occur in the wrong 136 * context. 137 * If needed, take msc->probe_lock first. 138 */ 139 raw_spinlock_t _mon_sel_lock; 140 unsigned long _mon_sel_flags; 141 /* 142 * mon_sel_mutex is the mutex version of the _mon_sel_lock above. 143 * Always use the mpam_mon_sel_lock() helpers when taking the lock, 144 * as this will select the correct lock type automatically. 145 */ 146 struct mutex mon_sel_mutex; 147 148 void __iomem *mapped_hwpage; 149 size_t mapped_hwpage_sz; 150 151 /* Values only used on some platforms for quirks */ 152 u32 t241_id; 153 154 struct mpam_garbage garbage; 155 }; 156 157 /* Returning false here means accesses to mon_sel must fail and report an error. */ 158 static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) 159 { 160 if (msc->iface == MPAM_IFACE_MMIO) { 161 raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); 162 163 return true; 164 } 165 166 if (!preemptible()) 167 return false; 168 169 mutex_lock(&msc->mon_sel_mutex); 170 171 return true; 172 } 173 174 static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) 175 { 176 if (msc->iface == MPAM_IFACE_MMIO) { 177 raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, 178 msc->_mon_sel_flags); 179 180 return; 181 } 182 183 mutex_unlock(&msc->mon_sel_mutex); 184 } 185 186 static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) 187 { 188 if (msc->iface == MPAM_IFACE_MMIO) 189 lockdep_assert_held_once(&msc->_mon_sel_lock); 190 else 191 lockdep_assert_held_once(&msc->mon_sel_mutex); 192 } 193 194 static inline int mpam_mon_sel_lock_init(struct device *dev, 195 struct mpam_msc *msc) 196 { 197 if (msc->iface == MPAM_IFACE_MMIO) { 198 raw_spin_lock_init(&msc->_mon_sel_lock); 199 200 return 0; 201 } 202 203 return devm_mutex_init(dev, &msc->mon_sel_mutex); 204 } 205 206 DEFINE_CLASS(mon_sel_lock, struct mpam_msc *, 207 if (_T) mpam_mon_sel_unlock(_T), 208 mpam_mon_sel_lock(msc) ? msc : NULL, struct mpam_msc *msc); 209 DEFINE_CLASS_IS_COND_GUARD(mon_sel_lock); 210 211 /* Bits for mpam features bitmaps */ 212 enum mpam_device_features { 213 mpam_feat_cpor_part, 214 mpam_feat_cmax_softlim, 215 mpam_feat_cmax_cmax, 216 mpam_feat_cmax_cmin, 217 mpam_feat_cmax_cassoc, 218 mpam_feat_mbw_part, 219 mpam_feat_mbw_min, 220 mpam_feat_mbw_max, 221 mpam_feat_mbw_prop, 222 mpam_feat_intpri_part, 223 mpam_feat_intpri_part_0_low, 224 mpam_feat_dspri_part, 225 mpam_feat_dspri_part_0_low, 226 mpam_feat_msmon, 227 mpam_feat_msmon_csu, 228 mpam_feat_msmon_csu_capture, 229 mpam_feat_msmon_csu_xcl, 230 mpam_feat_msmon_mbwu, 231 mpam_feat_msmon_mbwu_31counter, 232 mpam_feat_msmon_mbwu_44counter, 233 mpam_feat_msmon_mbwu_63counter, 234 mpam_feat_msmon_mbwu_capture, 235 mpam_feat_msmon_mbwu_rwbw, 236 mpam_feat_partid_nrw, 237 MPAM_FEATURE_LAST 238 }; 239 240 struct mpam_props { 241 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 242 243 u16 cpbm_wd; 244 u16 mbw_pbm_bits; 245 u16 bwa_wd; 246 u16 cmax_wd; 247 u16 cassoc_wd; 248 u16 intpri_wd; 249 u16 dspri_wd; 250 u16 num_csu_mon; 251 u16 num_mbwu_mon; 252 253 /* 254 * Kunit tests use memset() to set up feature combinations that should be 255 * removed, and will false-positive if the compiler introduces padding that 256 * isn't cleared during sanitisation. 257 */ 258 } PACKED_FOR_KUNIT; 259 260 #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features) 261 /* 262 * The non-atomic get/set operations are used because if struct mpam_props is 263 * packed, the alignment requirements for atomics aren't met. 264 */ 265 #define mpam_set_feature(_feat, x) __set_bit(_feat, (x)->features) 266 #define mpam_clear_feature(_feat, x) __clear_bit(_feat, (x)->features) 267 268 /* Workaround bits for msc->quirks */ 269 enum mpam_device_quirks { 270 T241_SCRUB_SHADOW_REGS, 271 T241_FORCE_MBW_MIN_TO_ONE, 272 T241_MBW_COUNTER_SCALE_64, 273 IGNORE_CSU_NRDY, 274 MPAM_QUIRK_LAST 275 }; 276 277 #define mpam_has_quirk(_quirk, x) ((1 << (_quirk) & (x)->quirks)) 278 #define mpam_set_quirk(_quirk, x) ((x)->quirks |= (1 << (_quirk))) 279 280 struct mpam_quirk { 281 int (*init)(struct mpam_msc *msc, const struct mpam_quirk *quirk); 282 283 u32 iidr; 284 u32 iidr_mask; 285 286 enum mpam_device_quirks workaround; 287 }; 288 289 #define MPAM_IIDR_MATCH_ONE (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0xfff) | \ 290 FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0xf) | \ 291 FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0xf) | \ 292 FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0xfff)) 293 294 #define MPAM_IIDR_NVIDIA_T241 (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0x241) | \ 295 FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0) | \ 296 FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0) | \ 297 FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x36b)) 298 299 #define MPAM_IIDR_ARM_CMN_650 (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0) | \ 300 FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0) | \ 301 FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0) | \ 302 FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x43b)) 303 304 /* The values for MSMON_CFG_MBWU_FLT.RWBW */ 305 enum mon_filter_options { 306 COUNT_BOTH = 0, 307 COUNT_WRITE = 1, 308 COUNT_READ = 2, 309 }; 310 311 struct mon_cfg { 312 /* 313 * mon must be large enough to hold out of range values like 314 * USE_PRE_ALLOCATED 315 */ 316 u32 mon; 317 u8 pmg; 318 bool match_pmg; 319 bool csu_exclude_clean; 320 u32 partid; 321 enum mon_filter_options opts; 322 }; 323 324 /* Changes to msmon_mbwu_state are protected by the msc's mon_sel_lock. */ 325 struct msmon_mbwu_state { 326 bool enabled; 327 bool reset_on_next_read; 328 struct mon_cfg cfg; 329 330 /* 331 * The value to add to the new reading to account for power management, 332 * and overflow. 333 */ 334 u64 correction; 335 336 struct mpam_garbage garbage; 337 }; 338 339 struct mpam_class { 340 /* mpam_components in this class */ 341 struct list_head components; 342 343 cpumask_t affinity; 344 345 struct mpam_props props; 346 u32 nrdy_usec; 347 u16 quirks; 348 u8 level; 349 enum mpam_class_types type; 350 351 /* member of mpam_classes */ 352 struct list_head classes_list; 353 354 struct ida ida_csu_mon; 355 struct ida ida_mbwu_mon; 356 357 struct mpam_garbage garbage; 358 }; 359 360 struct mpam_config { 361 /* Which configuration values are valid. */ 362 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 363 364 u32 cpbm; 365 u32 mbw_pbm; 366 u16 mbw_max; 367 368 struct mpam_garbage garbage; 369 }; 370 371 struct mpam_component { 372 u32 comp_id; 373 374 /* mpam_vmsc in this component */ 375 struct list_head vmsc; 376 377 cpumask_t affinity; 378 379 /* 380 * Array of configuration values, indexed by partid. 381 * Read from cpuhp callbacks, hold the cpuhp lock when writing. 382 */ 383 struct mpam_config *cfg; 384 385 /* member of mpam_class:components */ 386 struct list_head class_list; 387 388 /* parent: */ 389 struct mpam_class *class; 390 391 struct mpam_garbage garbage; 392 }; 393 394 struct mpam_vmsc { 395 /* member of mpam_component:vmsc_list */ 396 struct list_head comp_list; 397 398 /* mpam_msc_ris in this vmsc */ 399 struct list_head ris; 400 401 struct mpam_props props; 402 403 /* All RIS in this vMSC are members of this MSC */ 404 struct mpam_msc *msc; 405 406 /* parent: */ 407 struct mpam_component *comp; 408 409 struct mpam_garbage garbage; 410 }; 411 412 struct mpam_msc_ris { 413 u8 ris_idx; 414 u64 idr; 415 struct mpam_props props; 416 bool in_reset_state; 417 418 cpumask_t affinity; 419 420 /* member of mpam_vmsc:ris */ 421 struct list_head vmsc_list; 422 423 /* member of mpam_msc:ris */ 424 struct list_head msc_list; 425 426 /* parent: */ 427 struct mpam_vmsc *vmsc; 428 429 /* msmon mbwu configuration is preserved over reset */ 430 struct msmon_mbwu_state *mbwu_state; 431 432 struct mpam_garbage garbage; 433 }; 434 435 struct mpam_resctrl_dom { 436 struct mpam_component *ctrl_comp; 437 438 /* 439 * There is no single mon_comp because different events may be backed 440 * by different class/components. mon_comp is indexed by the event 441 * number. 442 */ 443 struct mpam_component *mon_comp[QOS_NUM_EVENTS]; 444 445 struct rdt_ctrl_domain resctrl_ctrl_dom; 446 struct rdt_l3_mon_domain resctrl_mon_dom; 447 }; 448 449 struct mpam_resctrl_res { 450 struct mpam_class *class; 451 struct rdt_resource resctrl_res; 452 bool cdp_enabled; 453 }; 454 455 struct mpam_resctrl_mon { 456 struct mpam_class *class; 457 458 /* Array of allocated MBWU monitors, indexed by (closid, rmid). */ 459 int *mbwu_idx_to_mon; 460 461 /* Array of assigned MBWU monitors, indexed by resctrl's cntr_id. */ 462 int *assigned_counters; 463 }; 464 465 static inline int mpam_alloc_csu_mon(struct mpam_class *class) 466 { 467 struct mpam_props *cprops = &class->props; 468 469 if (!mpam_has_feature(mpam_feat_msmon_csu, cprops)) 470 return -EOPNOTSUPP; 471 472 return ida_alloc_max(&class->ida_csu_mon, cprops->num_csu_mon - 1, 473 GFP_KERNEL); 474 } 475 476 static inline void mpam_free_csu_mon(struct mpam_class *class, int csu_mon) 477 { 478 ida_free(&class->ida_csu_mon, csu_mon); 479 } 480 481 static inline int mpam_alloc_mbwu_mon(struct mpam_class *class) 482 { 483 struct mpam_props *cprops = &class->props; 484 485 if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops)) 486 return -EOPNOTSUPP; 487 488 return ida_alloc_max(&class->ida_mbwu_mon, cprops->num_mbwu_mon - 1, 489 GFP_KERNEL); 490 } 491 492 static inline void mpam_free_mbwu_mon(struct mpam_class *class, int mbwu_mon) 493 { 494 ida_free(&class->ida_mbwu_mon, mbwu_mon); 495 } 496 497 /* List of all classes - protected by srcu*/ 498 extern struct srcu_struct mpam_srcu; 499 extern struct list_head mpam_classes; 500 501 /* System wide partid/pmg values */ 502 extern u16 mpam_partid_max; 503 extern u8 mpam_pmg_max; 504 505 /* Scheduled work callback to enable mpam once all MSC have been probed */ 506 void mpam_enable(struct work_struct *work); 507 void mpam_disable(struct work_struct *work); 508 509 /* helper function to call from outside mpam_devices.c */ 510 void mpam_fb_disable_mpam(int err, int mpam_fb_err); 511 512 /* Reset all the RIS in a class under cpus_read_lock() */ 513 int mpam_reset_class_locked(struct mpam_class *class); 514 515 int mpam_apply_config(struct mpam_component *comp, u16 partid, 516 struct mpam_config *cfg); 517 518 int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx, 519 enum mpam_device_features, u64 *val); 520 void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ctx); 521 522 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, 523 cpumask_t *affinity); 524 525 #ifdef CONFIG_RESCTRL_FS 526 int mpam_resctrl_setup(void); 527 void mpam_resctrl_exit(void); 528 int mpam_resctrl_online_cpu(unsigned int cpu); 529 void mpam_resctrl_offline_cpu(unsigned int cpu); 530 void mpam_resctrl_teardown_class(struct mpam_class *class); 531 #else 532 static inline int mpam_resctrl_setup(void) { return 0; } 533 static inline void mpam_resctrl_exit(void) { } 534 static inline int mpam_resctrl_online_cpu(unsigned int cpu) { return 0; } 535 static inline void mpam_resctrl_offline_cpu(unsigned int cpu) { } 536 static inline void mpam_resctrl_teardown_class(struct mpam_class *class) { } 537 #endif /* CONFIG_RESCTRL_FS */ 538 539 /* MPAM-Fb Firmware-backed protocol wrappers */ 540 int mpam_fb_send_read_request(struct mpam_msc *msc, u16 reg, u32 *result); 541 int mpam_fb_send_write_request(struct mpam_msc *msc, u16 reg, u32 value); 542 int mpam_fb_check_protocol_version(struct mpam_msc *msc); 543 int mpam_fb_check_shared_buffer_size(struct mpam_msc *msc); 544 545 /* 546 * MPAM MSCs have the following register layout. See: 547 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System 548 * Component Specification. 549 * https://developer.arm.com/documentation/ihi0099/aa/ 550 */ 551 #define MPAM_ARCHITECTURE_V1 0x10 552 553 /* Memory mapped control pages */ 554 /* ID Register offsets in the memory mapped page */ 555 #define MPAMF_IDR 0x0000 /* features id register */ 556 #define MPAMF_IIDR 0x0018 /* implementer id register */ 557 #define MPAMF_AIDR 0x0020 /* architectural id register */ 558 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ 559 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ 560 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ 561 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ 562 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ 563 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ 564 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ 565 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ 566 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ 567 568 /* Configuration and Status Register offsets in the memory mapped page */ 569 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ 570 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */ 571 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ 572 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ 573 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ 574 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ 575 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ 576 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ 577 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ 578 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */ 579 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ 580 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ 581 582 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ 583 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ 584 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ 585 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ 586 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ 587 #define MSMON_CSU 0x0840 /* current cache-usage */ 588 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ 589 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */ 590 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ 591 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ 592 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */ 593 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ 594 #define MPAMF_ESR 0x00F8 /* error status register */ 595 #define MPAMF_ECR 0x00F0 /* error control register */ 596 597 /* MPAMF_IDR - MPAM features ID register */ 598 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) 599 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16) 600 #define MPAMF_IDR_HAS_CCAP_PART BIT(24) 601 #define MPAMF_IDR_HAS_CPOR_PART BIT(25) 602 #define MPAMF_IDR_HAS_MBW_PART BIT(26) 603 #define MPAMF_IDR_HAS_PRI_PART BIT(27) 604 #define MPAMF_IDR_EXT BIT(28) 605 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29) 606 #define MPAMF_IDR_HAS_MSMON BIT(30) 607 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31) 608 #define MPAMF_IDR_HAS_RIS BIT(32) 609 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38) 610 #define MPAMF_IDR_HAS_ESR BIT(39) 611 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56) 612 613 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ 614 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) 615 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) 616 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) 617 618 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ 619 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) 620 621 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ 622 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) 623 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) 624 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) 625 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) 626 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30) 627 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) 628 629 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ 630 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) 631 #define MPAMF_MBW_IDR_HAS_MIN BIT(10) 632 #define MPAMF_MBW_IDR_HAS_MAX BIT(11) 633 #define MPAMF_MBW_IDR_HAS_PBM BIT(12) 634 #define MPAMF_MBW_IDR_HAS_PROP BIT(13) 635 #define MPAMF_MBW_IDR_WINDWR BIT(14) 636 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) 637 638 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ 639 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) 640 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) 641 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) 642 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) 643 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) 644 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) 645 646 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ 647 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) 648 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) 649 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) 650 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) 651 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) 652 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) 653 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30) 654 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) 655 656 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ 657 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) 658 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) 659 #define MPAMF_MBWUMON_IDR_LWD BIT(29) 660 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) 661 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) 662 663 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ 664 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) 665 666 /* MPAMF_IIDR - MPAM implementation ID register */ 667 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) 668 #define MPAMF_IIDR_REVISION GENMASK(15, 12) 669 #define MPAMF_IIDR_VARIANT GENMASK(19, 16) 670 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) 671 672 /* MPAMF_AIDR - MPAM architecture ID register */ 673 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) 674 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) 675 676 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ 677 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) 678 #define MPAMCFG_PART_SEL_INTERNAL BIT(16) 679 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) 680 681 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */ 682 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) 683 684 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */ 685 #define MPAMCFG_CMAX_SOFTLIM BIT(31) 686 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0) 687 688 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */ 689 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0) 690 691 /* 692 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration 693 * register 694 */ 695 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) 696 697 /* 698 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration 699 * register 700 */ 701 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) 702 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) 703 704 /* 705 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width 706 * register 707 */ 708 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) 709 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) 710 711 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */ 712 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0) 713 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16) 714 715 /* 716 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning 717 * configuration register 718 */ 719 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) 720 #define MPAMCFG_MBW_PROP_EN BIT(31) 721 722 /* 723 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register 724 */ 725 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) 726 #define MPAMCFG_INTPARTID_INTERNAL BIT(16) 727 728 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */ 729 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) 730 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) 731 732 /* MPAMF_ESR - MPAM Error Status Register */ 733 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0) 734 #define MPAMF_ESR_PMG GENMASK(23, 16) 735 #define MPAMF_ESR_ERRCODE GENMASK(27, 24) 736 #define MPAMF_ESR_OVRWR BIT(31) 737 #define MPAMF_ESR_RIS GENMASK(35, 32) 738 739 /* MPAMF_ECR - MPAM Error Control Register */ 740 #define MPAMF_ECR_INTEN BIT(0) 741 742 /* Error conditions in accessing memory mapped registers */ 743 #define MPAM_ERRCODE_NONE 0 744 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1 745 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2 746 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 747 #define MPAM_ERRCODE_REQ_PMG_RANGE 4 748 #define MPAM_ERRCODE_MONITOR_RANGE 5 749 #define MPAM_ERRCODE_INTPARTID_RANGE 6 750 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 751 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8 752 #define MPAM_ERRCODE_RIS_NO_CONTROL 9 753 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10 754 #define MPAM_ERRCODE_RIS_NO_MONITOR 11 755 756 /* 757 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage 758 * usage monitor control register 759 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory 760 * bandwidth usage monitor control register 761 */ 762 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) 763 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) 764 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) 765 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) 766 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19) 767 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) 768 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) 769 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) 770 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) 771 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) 772 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) 773 #define MSMON_CFG_x_CTL_EN BIT(31) 774 775 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 776 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 777 778 /* 779 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage 780 * usage monitor filter register 781 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory 782 * bandwidth usage monitor filter register 783 */ 784 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) 785 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) 786 787 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) 788 #define MSMON_CFG_CSU_FLT_XCL BIT(31) 789 790 /* 791 * MSMON_CSU - Memory system performance monitor cache storage usage monitor 792 * register 793 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage 794 * capture register 795 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage 796 * monitor register 797 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage 798 * capture register 799 */ 800 #define MSMON___VALUE GENMASK(30, 0) 801 #define MSMON___NRDY BIT(31) 802 #define MSMON___L_NRDY BIT(63) 803 #define MSMON___L_VALUE GENMASK(43, 0) 804 #define MSMON___LWD_VALUE GENMASK(62, 0) 805 806 /* 807 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event 808 * generation register 809 */ 810 #define MSMON_CAPT_EVNT_NOW BIT(0) 811 812 #endif /* MPAM_INTERNAL_H */ 813