1 /* 2 * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader 3 * 4 * Copyright (C) 2016 Linaro Ltd 5 * Copyright (C) 2014 Sony Mobile Communications AB 6 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/firmware.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/io.h> 25 #include <linux/of_address.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/qcom_scm.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/remoteproc.h> 31 #include <linux/soc/qcom/smem.h> 32 #include <linux/soc/qcom/smem_state.h> 33 #include <linux/rpmsg/qcom_smd.h> 34 35 #include "qcom_mdt_loader.h" 36 #include "remoteproc_internal.h" 37 #include "qcom_wcnss.h" 38 39 #define WCNSS_CRASH_REASON_SMEM 422 40 #define WCNSS_FIRMWARE_NAME "wcnss.mdt" 41 #define WCNSS_PAS_ID 6 42 43 #define WCNSS_SPARE_NVBIN_DLND BIT(25) 44 45 #define WCNSS_PMU_IRIS_XO_CFG BIT(3) 46 #define WCNSS_PMU_IRIS_XO_EN BIT(4) 47 #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5) 48 #define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */ 49 50 #define WCNSS_PMU_IRIS_RESET BIT(7) 51 #define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */ 52 #define WCNSS_PMU_IRIS_XO_READ BIT(9) 53 #define WCNSS_PMU_IRIS_XO_READ_STS BIT(10) 54 55 #define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1) 56 #define WCNSS_PMU_XO_MODE_19p2 0 57 #define WCNSS_PMU_XO_MODE_48 3 58 59 struct wcnss_data { 60 size_t pmu_offset; 61 size_t spare_offset; 62 63 const struct wcnss_vreg_info *vregs; 64 size_t num_vregs; 65 }; 66 67 struct qcom_wcnss { 68 struct device *dev; 69 struct rproc *rproc; 70 71 void __iomem *pmu_cfg; 72 void __iomem *spare_out; 73 74 bool use_48mhz_xo; 75 76 int wdog_irq; 77 int fatal_irq; 78 int ready_irq; 79 int handover_irq; 80 int stop_ack_irq; 81 82 struct qcom_smem_state *state; 83 unsigned stop_bit; 84 85 struct mutex iris_lock; 86 struct qcom_iris *iris; 87 88 struct regulator_bulk_data *vregs; 89 size_t num_vregs; 90 91 struct completion start_done; 92 struct completion stop_done; 93 94 phys_addr_t mem_phys; 95 phys_addr_t mem_reloc; 96 void *mem_region; 97 size_t mem_size; 98 99 struct device_node *smd_node; 100 struct qcom_smd_edge *smd_edge; 101 struct rproc_subdev smd_subdev; 102 }; 103 104 static const struct wcnss_data riva_data = { 105 .pmu_offset = 0x28, 106 .spare_offset = 0xb4, 107 108 .vregs = (struct wcnss_vreg_info[]) { 109 { "vddmx", 1050000, 1150000, 0 }, 110 { "vddcx", 1050000, 1150000, 0 }, 111 { "vddpx", 1800000, 1800000, 0 }, 112 }, 113 .num_vregs = 3, 114 }; 115 116 static const struct wcnss_data pronto_v1_data = { 117 .pmu_offset = 0x1004, 118 .spare_offset = 0x1088, 119 120 .vregs = (struct wcnss_vreg_info[]) { 121 { "vddmx", 950000, 1150000, 0 }, 122 { "vddcx", .super_turbo = true}, 123 { "vddpx", 1800000, 1800000, 0 }, 124 }, 125 .num_vregs = 3, 126 }; 127 128 static const struct wcnss_data pronto_v2_data = { 129 .pmu_offset = 0x1004, 130 .spare_offset = 0x1088, 131 132 .vregs = (struct wcnss_vreg_info[]) { 133 { "vddmx", 1287500, 1287500, 0 }, 134 { "vddcx", .super_turbo = true }, 135 { "vddpx", 1800000, 1800000, 0 }, 136 }, 137 .num_vregs = 3, 138 }; 139 140 void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss, 141 struct qcom_iris *iris, 142 bool use_48mhz_xo) 143 { 144 mutex_lock(&wcnss->iris_lock); 145 146 wcnss->iris = iris; 147 wcnss->use_48mhz_xo = use_48mhz_xo; 148 149 mutex_unlock(&wcnss->iris_lock); 150 } 151 152 static int wcnss_load(struct rproc *rproc, const struct firmware *fw) 153 { 154 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; 155 phys_addr_t fw_addr; 156 size_t fw_size; 157 bool relocate; 158 int ret; 159 160 ret = qcom_scm_pas_init_image(WCNSS_PAS_ID, fw->data, fw->size); 161 if (ret) { 162 dev_err(&rproc->dev, "invalid firmware metadata\n"); 163 return ret; 164 } 165 166 ret = qcom_mdt_parse(fw, &fw_addr, &fw_size, &relocate); 167 if (ret) { 168 dev_err(&rproc->dev, "failed to parse mdt header\n"); 169 return ret; 170 } 171 172 if (relocate) { 173 wcnss->mem_reloc = fw_addr; 174 175 ret = qcom_scm_pas_mem_setup(WCNSS_PAS_ID, wcnss->mem_phys, fw_size); 176 if (ret) { 177 dev_err(&rproc->dev, "unable to setup memory for image\n"); 178 return ret; 179 } 180 } 181 182 return qcom_mdt_load(rproc, fw, rproc->firmware); 183 } 184 185 static const struct rproc_fw_ops wcnss_fw_ops = { 186 .find_rsc_table = qcom_mdt_find_rsc_table, 187 .load = wcnss_load, 188 }; 189 190 static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss) 191 { 192 u32 val; 193 194 /* Indicate NV download capability */ 195 val = readl(wcnss->spare_out); 196 val |= WCNSS_SPARE_NVBIN_DLND; 197 writel(val, wcnss->spare_out); 198 } 199 200 static void wcnss_configure_iris(struct qcom_wcnss *wcnss) 201 { 202 u32 val; 203 204 /* Clear PMU cfg register */ 205 writel(0, wcnss->pmu_cfg); 206 207 val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN; 208 writel(val, wcnss->pmu_cfg); 209 210 /* Clear XO_MODE */ 211 val &= ~WCNSS_PMU_XO_MODE_MASK; 212 if (wcnss->use_48mhz_xo) 213 val |= WCNSS_PMU_XO_MODE_48 << 1; 214 else 215 val |= WCNSS_PMU_XO_MODE_19p2 << 1; 216 writel(val, wcnss->pmu_cfg); 217 218 /* Reset IRIS */ 219 val |= WCNSS_PMU_IRIS_RESET; 220 writel(val, wcnss->pmu_cfg); 221 222 /* Wait for PMU.iris_reg_reset_sts */ 223 while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS) 224 cpu_relax(); 225 226 /* Clear IRIS reset */ 227 val &= ~WCNSS_PMU_IRIS_RESET; 228 writel(val, wcnss->pmu_cfg); 229 230 /* Start IRIS XO configuration */ 231 val |= WCNSS_PMU_IRIS_XO_CFG; 232 writel(val, wcnss->pmu_cfg); 233 234 /* Wait for XO configuration to finish */ 235 while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS) 236 cpu_relax(); 237 238 /* Stop IRIS XO configuration */ 239 val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP; 240 val &= ~WCNSS_PMU_IRIS_XO_CFG; 241 writel(val, wcnss->pmu_cfg); 242 243 /* Add some delay for XO to settle */ 244 msleep(20); 245 } 246 247 static int wcnss_start(struct rproc *rproc) 248 { 249 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; 250 int ret; 251 252 mutex_lock(&wcnss->iris_lock); 253 if (!wcnss->iris) { 254 dev_err(wcnss->dev, "no iris registered\n"); 255 ret = -EINVAL; 256 goto release_iris_lock; 257 } 258 259 ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs); 260 if (ret) 261 goto release_iris_lock; 262 263 ret = qcom_iris_enable(wcnss->iris); 264 if (ret) 265 goto disable_regulators; 266 267 wcnss_indicate_nv_download(wcnss); 268 wcnss_configure_iris(wcnss); 269 270 ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID); 271 if (ret) { 272 dev_err(wcnss->dev, 273 "failed to authenticate image and release reset\n"); 274 goto disable_iris; 275 } 276 277 ret = wait_for_completion_timeout(&wcnss->start_done, 278 msecs_to_jiffies(5000)); 279 if (wcnss->ready_irq > 0 && ret == 0) { 280 /* We have a ready_irq, but it didn't fire in time. */ 281 dev_err(wcnss->dev, "start timed out\n"); 282 qcom_scm_pas_shutdown(WCNSS_PAS_ID); 283 ret = -ETIMEDOUT; 284 goto disable_iris; 285 } 286 287 ret = 0; 288 289 disable_iris: 290 qcom_iris_disable(wcnss->iris); 291 disable_regulators: 292 regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs); 293 release_iris_lock: 294 mutex_unlock(&wcnss->iris_lock); 295 296 return ret; 297 } 298 299 static int wcnss_stop(struct rproc *rproc) 300 { 301 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; 302 int ret; 303 304 if (wcnss->state) { 305 qcom_smem_state_update_bits(wcnss->state, 306 BIT(wcnss->stop_bit), 307 BIT(wcnss->stop_bit)); 308 309 ret = wait_for_completion_timeout(&wcnss->stop_done, 310 msecs_to_jiffies(5000)); 311 if (ret == 0) 312 dev_err(wcnss->dev, "timed out on wait\n"); 313 314 qcom_smem_state_update_bits(wcnss->state, 315 BIT(wcnss->stop_bit), 316 0); 317 } 318 319 ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID); 320 if (ret) 321 dev_err(wcnss->dev, "failed to shutdown: %d\n", ret); 322 323 return ret; 324 } 325 326 static void *wcnss_da_to_va(struct rproc *rproc, u64 da, int len) 327 { 328 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; 329 int offset; 330 331 offset = da - wcnss->mem_reloc; 332 if (offset < 0 || offset + len > wcnss->mem_size) 333 return NULL; 334 335 return wcnss->mem_region + offset; 336 } 337 338 static const struct rproc_ops wcnss_ops = { 339 .start = wcnss_start, 340 .stop = wcnss_stop, 341 .da_to_va = wcnss_da_to_va, 342 }; 343 344 static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev) 345 { 346 struct qcom_wcnss *wcnss = dev; 347 348 rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG); 349 350 return IRQ_HANDLED; 351 } 352 353 static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev) 354 { 355 struct qcom_wcnss *wcnss = dev; 356 size_t len; 357 char *msg; 358 359 msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len); 360 if (!IS_ERR(msg) && len > 0 && msg[0]) 361 dev_err(wcnss->dev, "fatal error received: %s\n", msg); 362 363 rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR); 364 365 if (!IS_ERR(msg)) 366 msg[0] = '\0'; 367 368 return IRQ_HANDLED; 369 } 370 371 static irqreturn_t wcnss_ready_interrupt(int irq, void *dev) 372 { 373 struct qcom_wcnss *wcnss = dev; 374 375 complete(&wcnss->start_done); 376 377 return IRQ_HANDLED; 378 } 379 380 static irqreturn_t wcnss_handover_interrupt(int irq, void *dev) 381 { 382 /* 383 * XXX: At this point we're supposed to release the resources that we 384 * have been holding on behalf of the WCNSS. Unfortunately this 385 * interrupt comes way before the other side seems to be done. 386 * 387 * So we're currently relying on the ready interrupt firing later then 388 * this and we just disable the resources at the end of wcnss_start(). 389 */ 390 391 return IRQ_HANDLED; 392 } 393 394 static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev) 395 { 396 struct qcom_wcnss *wcnss = dev; 397 398 complete(&wcnss->stop_done); 399 400 return IRQ_HANDLED; 401 } 402 403 static int wcnss_smd_probe(struct rproc_subdev *subdev) 404 { 405 struct qcom_wcnss *wcnss = container_of(subdev, struct qcom_wcnss, smd_subdev); 406 407 wcnss->smd_edge = qcom_smd_register_edge(wcnss->dev, wcnss->smd_node); 408 409 return IS_ERR(wcnss->smd_edge) ? PTR_ERR(wcnss->smd_edge) : 0; 410 } 411 412 static void wcnss_smd_remove(struct rproc_subdev *subdev) 413 { 414 struct qcom_wcnss *wcnss = container_of(subdev, struct qcom_wcnss, smd_subdev); 415 416 qcom_smd_unregister_edge(wcnss->smd_edge); 417 wcnss->smd_edge = NULL; 418 } 419 420 static int wcnss_init_regulators(struct qcom_wcnss *wcnss, 421 const struct wcnss_vreg_info *info, 422 int num_vregs) 423 { 424 struct regulator_bulk_data *bulk; 425 int ret; 426 int i; 427 428 bulk = devm_kcalloc(wcnss->dev, 429 num_vregs, sizeof(struct regulator_bulk_data), 430 GFP_KERNEL); 431 if (!bulk) 432 return -ENOMEM; 433 434 for (i = 0; i < num_vregs; i++) 435 bulk[i].supply = info[i].name; 436 437 ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk); 438 if (ret) 439 return ret; 440 441 for (i = 0; i < num_vregs; i++) { 442 if (info[i].max_voltage) 443 regulator_set_voltage(bulk[i].consumer, 444 info[i].min_voltage, 445 info[i].max_voltage); 446 447 if (info[i].load_uA) 448 regulator_set_load(bulk[i].consumer, info[i].load_uA); 449 } 450 451 wcnss->vregs = bulk; 452 wcnss->num_vregs = num_vregs; 453 454 return 0; 455 } 456 457 static int wcnss_request_irq(struct qcom_wcnss *wcnss, 458 struct platform_device *pdev, 459 const char *name, 460 bool optional, 461 irq_handler_t thread_fn) 462 { 463 int ret; 464 465 ret = platform_get_irq_byname(pdev, name); 466 if (ret < 0 && optional) { 467 dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name); 468 return 0; 469 } else if (ret < 0) { 470 dev_err(&pdev->dev, "no %s IRQ defined\n", name); 471 return ret; 472 } 473 474 ret = devm_request_threaded_irq(&pdev->dev, ret, 475 NULL, thread_fn, 476 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 477 "wcnss", wcnss); 478 if (ret) 479 dev_err(&pdev->dev, "request %s IRQ failed\n", name); 480 481 return ret; 482 } 483 484 static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss) 485 { 486 struct device_node *node; 487 struct resource r; 488 int ret; 489 490 node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0); 491 if (!node) { 492 dev_err(wcnss->dev, "no memory-region specified\n"); 493 return -EINVAL; 494 } 495 496 ret = of_address_to_resource(node, 0, &r); 497 if (ret) 498 return ret; 499 500 wcnss->mem_phys = wcnss->mem_reloc = r.start; 501 wcnss->mem_size = resource_size(&r); 502 wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size); 503 if (!wcnss->mem_region) { 504 dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n", 505 &r.start, wcnss->mem_size); 506 return -EBUSY; 507 } 508 509 return 0; 510 } 511 512 static int wcnss_probe(struct platform_device *pdev) 513 { 514 const struct wcnss_data *data; 515 struct qcom_wcnss *wcnss; 516 struct resource *res; 517 struct rproc *rproc; 518 void __iomem *mmio; 519 int ret; 520 521 data = of_device_get_match_data(&pdev->dev); 522 523 if (!qcom_scm_is_available()) 524 return -EPROBE_DEFER; 525 526 if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) { 527 dev_err(&pdev->dev, "PAS is not available for WCNSS\n"); 528 return -ENXIO; 529 } 530 531 rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops, 532 WCNSS_FIRMWARE_NAME, sizeof(*wcnss)); 533 if (!rproc) { 534 dev_err(&pdev->dev, "unable to allocate remoteproc\n"); 535 return -ENOMEM; 536 } 537 538 rproc->fw_ops = &wcnss_fw_ops; 539 540 wcnss = (struct qcom_wcnss *)rproc->priv; 541 wcnss->dev = &pdev->dev; 542 wcnss->rproc = rproc; 543 platform_set_drvdata(pdev, wcnss); 544 545 init_completion(&wcnss->start_done); 546 init_completion(&wcnss->stop_done); 547 548 mutex_init(&wcnss->iris_lock); 549 550 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu"); 551 mmio = devm_ioremap_resource(&pdev->dev, res); 552 if (IS_ERR(mmio)) { 553 ret = PTR_ERR(mmio); 554 goto free_rproc; 555 }; 556 557 ret = wcnss_alloc_memory_region(wcnss); 558 if (ret) 559 goto free_rproc; 560 561 wcnss->pmu_cfg = mmio + data->pmu_offset; 562 wcnss->spare_out = mmio + data->spare_offset; 563 564 ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs); 565 if (ret) 566 goto free_rproc; 567 568 ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt); 569 if (ret < 0) 570 goto free_rproc; 571 wcnss->wdog_irq = ret; 572 573 ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt); 574 if (ret < 0) 575 goto free_rproc; 576 wcnss->fatal_irq = ret; 577 578 ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt); 579 if (ret < 0) 580 goto free_rproc; 581 wcnss->ready_irq = ret; 582 583 ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt); 584 if (ret < 0) 585 goto free_rproc; 586 wcnss->handover_irq = ret; 587 588 ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt); 589 if (ret < 0) 590 goto free_rproc; 591 wcnss->stop_ack_irq = ret; 592 593 if (wcnss->stop_ack_irq) { 594 wcnss->state = qcom_smem_state_get(&pdev->dev, "stop", 595 &wcnss->stop_bit); 596 if (IS_ERR(wcnss->state)) { 597 ret = PTR_ERR(wcnss->state); 598 goto free_rproc; 599 } 600 } 601 602 wcnss->smd_node = of_get_child_by_name(pdev->dev.of_node, "smd-edge"); 603 if (wcnss->smd_node) 604 rproc_add_subdev(rproc, &wcnss->smd_subdev, wcnss_smd_probe, wcnss_smd_remove); 605 606 ret = rproc_add(rproc); 607 if (ret) 608 goto free_rproc; 609 610 return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 611 612 free_rproc: 613 rproc_free(rproc); 614 615 return ret; 616 } 617 618 static int wcnss_remove(struct platform_device *pdev) 619 { 620 struct qcom_wcnss *wcnss = platform_get_drvdata(pdev); 621 622 of_platform_depopulate(&pdev->dev); 623 624 of_node_put(wcnss->smd_node); 625 qcom_smem_state_put(wcnss->state); 626 rproc_del(wcnss->rproc); 627 rproc_free(wcnss->rproc); 628 629 return 0; 630 } 631 632 static const struct of_device_id wcnss_of_match[] = { 633 { .compatible = "qcom,riva-pil", &riva_data }, 634 { .compatible = "qcom,pronto-v1-pil", &pronto_v1_data }, 635 { .compatible = "qcom,pronto-v2-pil", &pronto_v2_data }, 636 { }, 637 }; 638 MODULE_DEVICE_TABLE(of, wcnss_of_match); 639 640 static struct platform_driver wcnss_driver = { 641 .probe = wcnss_probe, 642 .remove = wcnss_remove, 643 .driver = { 644 .name = "qcom-wcnss-pil", 645 .of_match_table = wcnss_of_match, 646 }, 647 }; 648 649 static int __init wcnss_init(void) 650 { 651 int ret; 652 653 ret = platform_driver_register(&wcnss_driver); 654 if (ret) 655 return ret; 656 657 ret = platform_driver_register(&qcom_iris_driver); 658 if (ret) 659 platform_driver_unregister(&wcnss_driver); 660 661 return ret; 662 } 663 module_init(wcnss_init); 664 665 static void __exit wcnss_exit(void) 666 { 667 platform_driver_unregister(&qcom_iris_driver); 668 platform_driver_unregister(&wcnss_driver); 669 } 670 module_exit(wcnss_exit); 671 672 MODULE_DESCRIPTION("Qualcomm Peripherial Image Loader for Wireless Subsystem"); 673 MODULE_LICENSE("GPL v2"); 674