1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Qualcomm self-authenticating modem subsystem remoteproc driver 4 * 5 * Copyright (C) 2016 Linaro Ltd. 6 * Copyright (C) 2014 Sony Mobile Communications AB 7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/devcoredump.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_reserved_mem.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_domain.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/remoteproc.h> 27 #include <linux/reset.h> 28 #include <linux/soc/qcom/mdt_loader.h> 29 #include <linux/iopoll.h> 30 #include <linux/slab.h> 31 32 #include "remoteproc_internal.h" 33 #include "qcom_common.h" 34 #include "qcom_pil_info.h" 35 #include "qcom_q6v5.h" 36 37 #include <linux/firmware/qcom/qcom_scm.h> 38 39 #define MPSS_CRASH_REASON_SMEM 421 40 41 #define MBA_LOG_SIZE SZ_4K 42 43 #define MPSS_PAS_ID 5 44 45 /* RMB Status Register Values */ 46 #define RMB_PBL_SUCCESS 0x1 47 48 #define RMB_MBA_XPU_UNLOCKED 0x1 49 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2 50 #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3 51 #define RMB_MBA_AUTH_COMPLETE 0x4 52 53 /* PBL/MBA interface registers */ 54 #define RMB_MBA_IMAGE_REG 0x00 55 #define RMB_PBL_STATUS_REG 0x04 56 #define RMB_MBA_COMMAND_REG 0x08 57 #define RMB_MBA_STATUS_REG 0x0C 58 #define RMB_PMI_META_DATA_REG 0x10 59 #define RMB_PMI_CODE_START_REG 0x14 60 #define RMB_PMI_CODE_LENGTH_REG 0x18 61 #define RMB_MBA_MSS_STATUS 0x40 62 #define RMB_MBA_ALT_RESET 0x44 63 64 #define RMB_CMD_META_DATA_READY 0x1 65 #define RMB_CMD_LOAD_READY 0x2 66 67 /* QDSP6SS Register Offsets */ 68 #define QDSP6SS_RESET_REG 0x014 69 #define QDSP6SS_GFMUX_CTL_REG 0x020 70 #define QDSP6SS_PWR_CTL_REG 0x030 71 #define QDSP6SS_MEM_PWR_CTL 0x0B0 72 #define QDSP6V6SS_MEM_PWR_CTL 0x034 73 #define QDSP6SS_STRAP_ACC 0x110 74 #define QDSP6V62SS_BHS_STATUS 0x0C4 75 76 /* AXI Halt Register Offsets */ 77 #define AXI_HALTREQ_REG 0x0 78 #define AXI_HALTACK_REG 0x4 79 #define AXI_IDLE_REG 0x8 80 #define AXI_GATING_VALID_OVERRIDE BIT(0) 81 82 #define HALT_ACK_TIMEOUT_US 100000 83 84 /* QACCEPT Register Offsets */ 85 #define QACCEPT_ACCEPT_REG 0x0 86 #define QACCEPT_ACTIVE_REG 0x4 87 #define QACCEPT_DENY_REG 0x8 88 #define QACCEPT_REQ_REG 0xC 89 90 #define QACCEPT_TIMEOUT_US 50 91 92 /* QDSP6SS_RESET */ 93 #define Q6SS_STOP_CORE BIT(0) 94 #define Q6SS_CORE_ARES BIT(1) 95 #define Q6SS_BUS_ARES_ENABLE BIT(2) 96 97 /* QDSP6SS CBCR */ 98 #define Q6SS_CBCR_CLKEN BIT(0) 99 #define Q6SS_CBCR_CLKOFF BIT(31) 100 #define Q6SS_CBCR_TIMEOUT_US 200 101 102 /* QDSP6SS_GFMUX_CTL */ 103 #define Q6SS_CLK_ENABLE BIT(1) 104 105 /* QDSP6SS_PWR_CTL */ 106 #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0) 107 #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1) 108 #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2) 109 #define Q6SS_L2TAG_SLP_NRET_N BIT(16) 110 #define Q6SS_ETB_SLP_NRET_N BIT(17) 111 #define Q6SS_L2DATA_STBY_N BIT(18) 112 #define Q6SS_SLP_RET_N BIT(19) 113 #define Q6SS_CLAMP_IO BIT(20) 114 #define QDSS_BHS_ON BIT(21) 115 #define QDSS_LDO_BYP BIT(22) 116 117 /* QDSP6v55 parameters */ 118 #define QDSP6V55_MEM_BITS GENMASK(16, 8) 119 120 /* QDSP6v56 parameters */ 121 #define QDSP6v56_LDO_BYP BIT(25) 122 #define QDSP6v56_BHS_ON BIT(24) 123 #define QDSP6v56_CLAMP_WL BIT(21) 124 #define QDSP6v56_CLAMP_QMC_MEM BIT(22) 125 #define QDSP6SS_XO_CBCR 0x0038 126 #define QDSP6SS_ACC_OVERRIDE_VAL 0x20 127 #define QDSP6v55_BHS_EN_REST_ACK BIT(0) 128 129 /* QDSP6v65 parameters */ 130 #define QDSP6SS_CORE_CBCR 0x20 131 #define QDSP6SS_SLEEP 0x3C 132 #define QDSP6SS_BOOT_CORE_START 0x400 133 #define QDSP6SS_BOOT_CMD 0x404 134 #define BOOT_FSM_TIMEOUT 10000 135 #define BHS_CHECK_MAX_LOOPS 200 136 137 struct reg_info { 138 struct regulator *reg; 139 int uV; 140 int uA; 141 }; 142 143 struct qcom_mss_reg_res { 144 const char *supply; 145 int uV; 146 int uA; 147 }; 148 149 struct rproc_hexagon_res { 150 const char *hexagon_mba_image; 151 struct qcom_mss_reg_res *proxy_supply; 152 struct qcom_mss_reg_res *fallback_proxy_supply; 153 struct qcom_mss_reg_res *active_supply; 154 char **proxy_clk_names; 155 char **reset_clk_names; 156 char **active_clk_names; 157 char **proxy_pd_names; 158 int version; 159 bool need_mem_protection; 160 bool has_alt_reset; 161 bool has_mba_logs; 162 bool has_spare_reg; 163 bool has_qaccept_regs; 164 bool has_ext_cntl_regs; 165 bool has_vq6; 166 }; 167 168 struct q6v5 { 169 struct device *dev; 170 struct rproc *rproc; 171 172 void __iomem *reg_base; 173 void __iomem *rmb_base; 174 175 struct regmap *halt_map; 176 struct regmap *conn_map; 177 178 u32 halt_q6; 179 u32 halt_modem; 180 u32 halt_nc; 181 u32 halt_vq6; 182 u32 conn_box; 183 184 u32 qaccept_mdm; 185 u32 qaccept_cx; 186 u32 qaccept_axi; 187 188 u32 axim1_clk_off; 189 u32 crypto_clk_off; 190 u32 force_clk_on; 191 u32 rscc_disable; 192 193 struct reset_control *mss_restart; 194 struct reset_control *pdc_reset; 195 196 struct qcom_q6v5 q6v5; 197 198 struct clk *active_clks[8]; 199 struct clk *reset_clks[4]; 200 struct clk *proxy_clks[4]; 201 struct device *proxy_pds[3]; 202 int active_clk_count; 203 int reset_clk_count; 204 int proxy_clk_count; 205 int proxy_pd_count; 206 207 struct reg_info active_regs[1]; 208 struct reg_info proxy_regs[1]; 209 struct reg_info fallback_proxy_regs[2]; 210 int active_reg_count; 211 int proxy_reg_count; 212 int fallback_proxy_reg_count; 213 214 bool dump_mba_loaded; 215 size_t current_dump_size; 216 size_t total_dump_size; 217 218 phys_addr_t mba_phys; 219 size_t mba_size; 220 size_t dp_size; 221 222 phys_addr_t mdata_phys; 223 size_t mdata_size; 224 225 phys_addr_t mpss_phys; 226 phys_addr_t mpss_reloc; 227 size_t mpss_size; 228 229 struct qcom_rproc_glink glink_subdev; 230 struct qcom_rproc_subdev smd_subdev; 231 struct qcom_rproc_pdm pdm_subdev; 232 struct qcom_rproc_ssr ssr_subdev; 233 struct qcom_sysmon *sysmon; 234 struct platform_device *bam_dmux; 235 bool need_mem_protection; 236 bool has_alt_reset; 237 bool has_mba_logs; 238 bool has_spare_reg; 239 bool has_qaccept_regs; 240 bool has_ext_cntl_regs; 241 bool has_vq6; 242 u64 mpss_perm; 243 u64 mba_perm; 244 const char *hexagon_mdt_image; 245 int version; 246 }; 247 248 enum { 249 MSS_MSM8909, 250 MSS_MSM8916, 251 MSS_MSM8953, 252 MSS_MSM8974, 253 MSS_MSM8996, 254 MSS_MSM8998, 255 MSS_SC7180, 256 MSS_SC7280, 257 MSS_SDM660, 258 MSS_SDM845, 259 }; 260 261 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs, 262 const struct qcom_mss_reg_res *reg_res) 263 { 264 int i; 265 266 if (!reg_res) 267 return 0; 268 269 for (i = 0; reg_res[i].supply; i++) { 270 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply); 271 if (IS_ERR(regs[i].reg)) 272 return dev_err_probe(dev, PTR_ERR(regs[i].reg), 273 "Failed to get %s\n regulator", 274 reg_res[i].supply); 275 276 regs[i].uV = reg_res[i].uV; 277 regs[i].uA = reg_res[i].uA; 278 } 279 280 return i; 281 } 282 283 static int q6v5_regulator_enable(struct q6v5 *qproc, 284 struct reg_info *regs, int count) 285 { 286 int ret; 287 int i; 288 289 for (i = 0; i < count; i++) { 290 if (regs[i].uV > 0) { 291 ret = regulator_set_voltage(regs[i].reg, 292 regs[i].uV, INT_MAX); 293 if (ret) { 294 dev_err(qproc->dev, 295 "Failed to request voltage for %d.\n", 296 i); 297 goto err; 298 } 299 } 300 301 if (regs[i].uA > 0) { 302 ret = regulator_set_load(regs[i].reg, 303 regs[i].uA); 304 if (ret < 0) { 305 dev_err(qproc->dev, 306 "Failed to set regulator mode\n"); 307 goto err; 308 } 309 } 310 311 ret = regulator_enable(regs[i].reg); 312 if (ret) { 313 dev_err(qproc->dev, "Regulator enable failed\n"); 314 goto err; 315 } 316 } 317 318 return 0; 319 err: 320 for (; i >= 0; i--) { 321 if (regs[i].uV > 0) 322 regulator_set_voltage(regs[i].reg, 0, INT_MAX); 323 324 if (regs[i].uA > 0) 325 regulator_set_load(regs[i].reg, 0); 326 327 regulator_disable(regs[i].reg); 328 } 329 330 return ret; 331 } 332 333 static void q6v5_regulator_disable(struct q6v5 *qproc, 334 struct reg_info *regs, int count) 335 { 336 int i; 337 338 for (i = 0; i < count; i++) { 339 if (regs[i].uV > 0) 340 regulator_set_voltage(regs[i].reg, 0, INT_MAX); 341 342 if (regs[i].uA > 0) 343 regulator_set_load(regs[i].reg, 0); 344 345 regulator_disable(regs[i].reg); 346 } 347 } 348 349 static int q6v5_clk_enable(struct device *dev, 350 struct clk **clks, int count) 351 { 352 int rc; 353 int i; 354 355 for (i = 0; i < count; i++) { 356 rc = clk_prepare_enable(clks[i]); 357 if (rc) { 358 dev_err(dev, "Clock enable failed\n"); 359 goto err; 360 } 361 } 362 363 return 0; 364 err: 365 for (i--; i >= 0; i--) 366 clk_disable_unprepare(clks[i]); 367 368 return rc; 369 } 370 371 static void q6v5_clk_disable(struct device *dev, 372 struct clk **clks, int count) 373 { 374 int i; 375 376 for (i = 0; i < count; i++) 377 clk_disable_unprepare(clks[i]); 378 } 379 380 static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds, 381 size_t pd_count) 382 { 383 int ret; 384 int i; 385 386 for (i = 0; i < pd_count; i++) { 387 dev_pm_genpd_set_performance_state(pds[i], INT_MAX); 388 ret = pm_runtime_get_sync(pds[i]); 389 if (ret < 0) { 390 pm_runtime_put_noidle(pds[i]); 391 dev_pm_genpd_set_performance_state(pds[i], 0); 392 goto unroll_pd_votes; 393 } 394 } 395 396 return 0; 397 398 unroll_pd_votes: 399 for (i--; i >= 0; i--) { 400 dev_pm_genpd_set_performance_state(pds[i], 0); 401 pm_runtime_put(pds[i]); 402 } 403 404 return ret; 405 } 406 407 static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds, 408 size_t pd_count) 409 { 410 int i; 411 412 for (i = 0; i < pd_count; i++) { 413 dev_pm_genpd_set_performance_state(pds[i], 0); 414 pm_runtime_put(pds[i]); 415 } 416 } 417 418 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, u64 *current_perm, 419 bool local, bool remote, phys_addr_t addr, 420 size_t size) 421 { 422 struct qcom_scm_vmperm next[2]; 423 int perms = 0; 424 425 if (!qproc->need_mem_protection) 426 return 0; 427 428 if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) && 429 remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA))) 430 return 0; 431 432 if (local) { 433 next[perms].vmid = QCOM_SCM_VMID_HLOS; 434 next[perms].perm = QCOM_SCM_PERM_RWX; 435 perms++; 436 } 437 438 if (remote) { 439 next[perms].vmid = QCOM_SCM_VMID_MSS_MSA; 440 next[perms].perm = QCOM_SCM_PERM_RW; 441 perms++; 442 } 443 444 return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K), 445 current_perm, next, perms); 446 } 447 448 static void q6v5_debug_policy_load(struct q6v5 *qproc, void *mba_region) 449 { 450 const struct firmware *dp_fw; 451 452 if (request_firmware_direct(&dp_fw, "msadp", qproc->dev)) 453 return; 454 455 if (SZ_1M + dp_fw->size <= qproc->mba_size) { 456 memcpy(mba_region + SZ_1M, dp_fw->data, dp_fw->size); 457 qproc->dp_size = dp_fw->size; 458 } 459 460 release_firmware(dp_fw); 461 } 462 463 static int q6v5_load(struct rproc *rproc, const struct firmware *fw) 464 { 465 struct q6v5 *qproc = rproc->priv; 466 void *mba_region; 467 468 /* MBA is restricted to a maximum size of 1M */ 469 if (fw->size > qproc->mba_size || fw->size > SZ_1M) { 470 dev_err(qproc->dev, "MBA firmware load failed\n"); 471 return -EINVAL; 472 } 473 474 mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC); 475 if (!mba_region) { 476 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n", 477 &qproc->mba_phys, qproc->mba_size); 478 return -EBUSY; 479 } 480 481 memcpy(mba_region, fw->data, fw->size); 482 q6v5_debug_policy_load(qproc, mba_region); 483 memunmap(mba_region); 484 485 return 0; 486 } 487 488 static int q6v5_reset_assert(struct q6v5 *qproc) 489 { 490 int ret; 491 492 if (qproc->has_alt_reset) { 493 reset_control_assert(qproc->pdc_reset); 494 ret = reset_control_reset(qproc->mss_restart); 495 reset_control_deassert(qproc->pdc_reset); 496 } else if (qproc->has_spare_reg) { 497 /* 498 * When the AXI pipeline is being reset with the Q6 modem partly 499 * operational there is possibility of AXI valid signal to 500 * glitch, leading to spurious transactions and Q6 hangs. A work 501 * around is employed by asserting the AXI_GATING_VALID_OVERRIDE 502 * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE 503 * is withdrawn post MSS assert followed by a MSS deassert, 504 * while holding the PDC reset. 505 */ 506 reset_control_assert(qproc->pdc_reset); 507 regmap_update_bits(qproc->conn_map, qproc->conn_box, 508 AXI_GATING_VALID_OVERRIDE, 1); 509 reset_control_assert(qproc->mss_restart); 510 reset_control_deassert(qproc->pdc_reset); 511 regmap_update_bits(qproc->conn_map, qproc->conn_box, 512 AXI_GATING_VALID_OVERRIDE, 0); 513 ret = reset_control_deassert(qproc->mss_restart); 514 } else if (qproc->has_ext_cntl_regs) { 515 regmap_write(qproc->conn_map, qproc->rscc_disable, 0); 516 reset_control_assert(qproc->pdc_reset); 517 reset_control_assert(qproc->mss_restart); 518 reset_control_deassert(qproc->pdc_reset); 519 ret = reset_control_deassert(qproc->mss_restart); 520 } else { 521 ret = reset_control_assert(qproc->mss_restart); 522 } 523 524 return ret; 525 } 526 527 static int q6v5_reset_deassert(struct q6v5 *qproc) 528 { 529 int ret; 530 531 if (qproc->has_alt_reset) { 532 reset_control_assert(qproc->pdc_reset); 533 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET); 534 ret = reset_control_reset(qproc->mss_restart); 535 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET); 536 reset_control_deassert(qproc->pdc_reset); 537 } else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) { 538 ret = reset_control_reset(qproc->mss_restart); 539 } else { 540 ret = reset_control_deassert(qproc->mss_restart); 541 } 542 543 return ret; 544 } 545 546 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms) 547 { 548 unsigned long timeout; 549 s32 val; 550 551 timeout = jiffies + msecs_to_jiffies(ms); 552 for (;;) { 553 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG); 554 if (val) 555 break; 556 557 if (time_after(jiffies, timeout)) 558 return -ETIMEDOUT; 559 560 msleep(1); 561 } 562 563 return val; 564 } 565 566 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms) 567 { 568 569 unsigned long timeout; 570 s32 val; 571 572 timeout = jiffies + msecs_to_jiffies(ms); 573 for (;;) { 574 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG); 575 if (val < 0) 576 break; 577 578 if (!status && val) 579 break; 580 else if (status && val == status) 581 break; 582 583 if (time_after(jiffies, timeout)) 584 return -ETIMEDOUT; 585 586 msleep(1); 587 } 588 589 return val; 590 } 591 592 static void q6v5_dump_mba_logs(struct q6v5 *qproc) 593 { 594 struct rproc *rproc = qproc->rproc; 595 void *data; 596 void *mba_region; 597 598 if (!qproc->has_mba_logs) 599 return; 600 601 if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys, 602 qproc->mba_size)) 603 return; 604 605 mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC); 606 if (!mba_region) 607 return; 608 609 data = vmalloc(MBA_LOG_SIZE); 610 if (data) { 611 memcpy(data, mba_region, MBA_LOG_SIZE); 612 dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL); 613 } 614 memunmap(mba_region); 615 } 616 617 static int q6v5proc_reset(struct q6v5 *qproc) 618 { 619 u32 val; 620 int ret; 621 int i; 622 623 if (qproc->version == MSS_SDM845) { 624 val = readl(qproc->reg_base + QDSP6SS_SLEEP); 625 val |= Q6SS_CBCR_CLKEN; 626 writel(val, qproc->reg_base + QDSP6SS_SLEEP); 627 628 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP, 629 val, !(val & Q6SS_CBCR_CLKOFF), 1, 630 Q6SS_CBCR_TIMEOUT_US); 631 if (ret) { 632 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n"); 633 return -ETIMEDOUT; 634 } 635 636 /* De-assert QDSP6 stop core */ 637 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START); 638 /* Trigger boot FSM */ 639 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD); 640 641 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS, 642 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); 643 if (ret) { 644 dev_err(qproc->dev, "Boot FSM failed to complete.\n"); 645 /* Reset the modem so that boot FSM is in reset state */ 646 q6v5_reset_deassert(qproc); 647 return ret; 648 } 649 650 goto pbl_wait; 651 } else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) { 652 val = readl(qproc->reg_base + QDSP6SS_SLEEP); 653 val |= Q6SS_CBCR_CLKEN; 654 writel(val, qproc->reg_base + QDSP6SS_SLEEP); 655 656 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP, 657 val, !(val & Q6SS_CBCR_CLKOFF), 1, 658 Q6SS_CBCR_TIMEOUT_US); 659 if (ret) { 660 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n"); 661 return -ETIMEDOUT; 662 } 663 664 /* Turn on the XO clock needed for PLL setup */ 665 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); 666 val |= Q6SS_CBCR_CLKEN; 667 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); 668 669 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, 670 val, !(val & Q6SS_CBCR_CLKOFF), 1, 671 Q6SS_CBCR_TIMEOUT_US); 672 if (ret) { 673 dev_err(qproc->dev, "QDSP6SS XO clock timed out\n"); 674 return -ETIMEDOUT; 675 } 676 677 /* Configure Q6 core CBCR to auto-enable after reset sequence */ 678 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR); 679 val |= Q6SS_CBCR_CLKEN; 680 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR); 681 682 /* De-assert the Q6 stop core signal */ 683 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START); 684 685 /* Wait for 10 us for any staggering logic to settle */ 686 usleep_range(10, 20); 687 688 /* Trigger the boot FSM to start the Q6 out-of-reset sequence */ 689 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD); 690 691 /* Poll the MSS_STATUS for FSM completion */ 692 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS, 693 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); 694 if (ret) { 695 dev_err(qproc->dev, "Boot FSM failed to complete.\n"); 696 /* Reset the modem so that boot FSM is in reset state */ 697 q6v5_reset_deassert(qproc); 698 return ret; 699 } 700 goto pbl_wait; 701 } else if (qproc->version == MSS_MSM8909 || 702 qproc->version == MSS_MSM8953 || 703 qproc->version == MSS_MSM8996 || 704 qproc->version == MSS_MSM8998 || 705 qproc->version == MSS_SDM660) { 706 707 if (qproc->version != MSS_MSM8909 && 708 qproc->version != MSS_MSM8953) 709 /* Override the ACC value if required */ 710 writel(QDSP6SS_ACC_OVERRIDE_VAL, 711 qproc->reg_base + QDSP6SS_STRAP_ACC); 712 713 /* Assert resets, stop core */ 714 val = readl(qproc->reg_base + QDSP6SS_RESET_REG); 715 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; 716 writel(val, qproc->reg_base + QDSP6SS_RESET_REG); 717 718 /* BHS require xo cbcr to be enabled */ 719 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); 720 val |= Q6SS_CBCR_CLKEN; 721 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); 722 723 /* Read CLKOFF bit to go low indicating CLK is enabled */ 724 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, 725 val, !(val & Q6SS_CBCR_CLKOFF), 1, 726 Q6SS_CBCR_TIMEOUT_US); 727 if (ret) { 728 dev_err(qproc->dev, 729 "xo cbcr enabling timed out (rc:%d)\n", ret); 730 return ret; 731 } 732 /* Enable power block headswitch and wait for it to stabilize */ 733 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 734 val |= QDSP6v56_BHS_ON; 735 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 736 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 737 udelay(1); 738 739 if (qproc->version == MSS_SDM660) { 740 ret = readl_relaxed_poll_timeout(qproc->reg_base + QDSP6V62SS_BHS_STATUS, 741 i, (i & QDSP6v55_BHS_EN_REST_ACK), 742 1, BHS_CHECK_MAX_LOOPS); 743 if (ret == -ETIMEDOUT) { 744 dev_err(qproc->dev, "BHS_EN_REST_ACK not set!\n"); 745 return -ETIMEDOUT; 746 } 747 } 748 749 /* Put LDO in bypass mode */ 750 val |= QDSP6v56_LDO_BYP; 751 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 752 753 if (qproc->version != MSS_MSM8909) { 754 int mem_pwr_ctl; 755 756 /* Deassert QDSP6 compiler memory clamp */ 757 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 758 val &= ~QDSP6v56_CLAMP_QMC_MEM; 759 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 760 761 /* Deassert memory peripheral sleep and L2 memory standby */ 762 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; 763 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 764 765 /* Turn on L1, L2, ETB and JU memories 1 at a time */ 766 if (qproc->version == MSS_MSM8953 || 767 qproc->version == MSS_MSM8996) { 768 mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL; 769 i = 19; 770 } else { 771 /* MSS_MSM8998, MSS_SDM660 */ 772 mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL; 773 i = 28; 774 } 775 val = readl(qproc->reg_base + mem_pwr_ctl); 776 for (; i >= 0; i--) { 777 val |= BIT(i); 778 writel(val, qproc->reg_base + mem_pwr_ctl); 779 /* 780 * Read back value to ensure the write is done then 781 * wait for 1us for both memory peripheral and data 782 * array to turn on. 783 */ 784 val |= readl(qproc->reg_base + mem_pwr_ctl); 785 udelay(1); 786 } 787 } else { 788 /* Turn on memories */ 789 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 790 val |= Q6SS_SLP_RET_N | Q6SS_L2DATA_STBY_N | 791 Q6SS_ETB_SLP_NRET_N | QDSP6V55_MEM_BITS; 792 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 793 794 /* Turn on L2 banks 1 at a time */ 795 for (i = 0; i <= 7; i++) { 796 val |= BIT(i); 797 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 798 } 799 } 800 801 /* Remove word line clamp */ 802 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 803 val &= ~QDSP6v56_CLAMP_WL; 804 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 805 } else { 806 /* Assert resets, stop core */ 807 val = readl(qproc->reg_base + QDSP6SS_RESET_REG); 808 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; 809 writel(val, qproc->reg_base + QDSP6SS_RESET_REG); 810 811 /* Enable power block headswitch and wait for it to stabilize */ 812 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 813 val |= QDSS_BHS_ON | QDSS_LDO_BYP; 814 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 815 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 816 udelay(1); 817 /* 818 * Turn on memories. L2 banks should be done individually 819 * to minimize inrush current. 820 */ 821 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 822 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N | 823 Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N; 824 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 825 val |= Q6SS_L2DATA_SLP_NRET_N_2; 826 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 827 val |= Q6SS_L2DATA_SLP_NRET_N_1; 828 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 829 val |= Q6SS_L2DATA_SLP_NRET_N_0; 830 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 831 } 832 /* Remove IO clamp */ 833 val &= ~Q6SS_CLAMP_IO; 834 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 835 836 /* Bring core out of reset */ 837 val = readl(qproc->reg_base + QDSP6SS_RESET_REG); 838 val &= ~Q6SS_CORE_ARES; 839 writel(val, qproc->reg_base + QDSP6SS_RESET_REG); 840 841 /* Turn on core clock */ 842 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); 843 val |= Q6SS_CLK_ENABLE; 844 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); 845 846 /* Start core execution */ 847 val = readl(qproc->reg_base + QDSP6SS_RESET_REG); 848 val &= ~Q6SS_STOP_CORE; 849 writel(val, qproc->reg_base + QDSP6SS_RESET_REG); 850 851 pbl_wait: 852 /* Wait for PBL status */ 853 ret = q6v5_rmb_pbl_wait(qproc, 1000); 854 if (ret == -ETIMEDOUT) { 855 dev_err(qproc->dev, "PBL boot timed out\n"); 856 } else if (ret != RMB_PBL_SUCCESS) { 857 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret); 858 ret = -EINVAL; 859 } else { 860 ret = 0; 861 } 862 863 return ret; 864 } 865 866 static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset) 867 { 868 unsigned int val; 869 int ret; 870 871 if (!qproc->has_qaccept_regs) 872 return 0; 873 874 if (qproc->has_ext_cntl_regs) { 875 regmap_write(qproc->conn_map, qproc->rscc_disable, 0); 876 regmap_write(qproc->conn_map, qproc->force_clk_on, 1); 877 878 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val, 879 !val, 1, Q6SS_CBCR_TIMEOUT_US); 880 if (ret) { 881 dev_err(qproc->dev, "failed to enable axim1 clock\n"); 882 return -ETIMEDOUT; 883 } 884 } 885 886 regmap_write(map, offset + QACCEPT_REQ_REG, 1); 887 888 /* Wait for accept */ 889 ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5, 890 QACCEPT_TIMEOUT_US); 891 if (ret) { 892 dev_err(qproc->dev, "qchannel enable failed\n"); 893 return -ETIMEDOUT; 894 } 895 896 return 0; 897 } 898 899 static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset) 900 { 901 int ret; 902 unsigned int val, retry; 903 unsigned int nretry = 10; 904 bool takedown_complete = false; 905 906 if (!qproc->has_qaccept_regs) 907 return; 908 909 while (!takedown_complete && nretry) { 910 nretry--; 911 912 /* Wait for active transactions to complete */ 913 regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5, 914 QACCEPT_TIMEOUT_US); 915 916 /* Request Q-channel transaction takedown */ 917 regmap_write(map, offset + QACCEPT_REQ_REG, 0); 918 919 /* 920 * If the request is denied, reset the Q-channel takedown request, 921 * wait for active transactions to complete and retry takedown. 922 */ 923 retry = 10; 924 while (retry) { 925 usleep_range(5, 10); 926 retry--; 927 ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val); 928 if (!ret && val) { 929 regmap_write(map, offset + QACCEPT_REQ_REG, 1); 930 break; 931 } 932 933 ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val); 934 if (!ret && !val) { 935 takedown_complete = true; 936 break; 937 } 938 } 939 940 if (!retry) 941 break; 942 } 943 944 /* Rely on mss_restart to clear out pending transactions on takedown failure */ 945 if (!takedown_complete) 946 dev_err(qproc->dev, "qchannel takedown failed\n"); 947 } 948 949 static void q6v5proc_halt_axi_port(struct q6v5 *qproc, 950 struct regmap *halt_map, 951 u32 offset) 952 { 953 unsigned int val; 954 int ret; 955 956 /* Check if we're already idle */ 957 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); 958 if (!ret && val) 959 return; 960 961 /* Assert halt request */ 962 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1); 963 964 /* Wait for halt */ 965 regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val, 966 val, 1000, HALT_ACK_TIMEOUT_US); 967 968 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); 969 if (ret || !val) 970 dev_err(qproc->dev, "port failed halt\n"); 971 972 /* Clear halt request (port will remain halted until reset) */ 973 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0); 974 } 975 976 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw, 977 const char *fw_name) 978 { 979 unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; 980 dma_addr_t phys; 981 void *metadata; 982 u64 mdata_perm; 983 int xferop_ret; 984 size_t size; 985 void *ptr; 986 int ret; 987 988 metadata = qcom_mdt_read_metadata(fw, &size, fw_name, qproc->dev); 989 if (IS_ERR(metadata)) 990 return PTR_ERR(metadata); 991 992 if (qproc->mdata_phys) { 993 if (size > qproc->mdata_size) { 994 ret = -EINVAL; 995 dev_err(qproc->dev, "metadata size outside memory range\n"); 996 goto free_metadata; 997 } 998 999 phys = qproc->mdata_phys; 1000 ptr = memremap(qproc->mdata_phys, size, MEMREMAP_WC); 1001 if (!ptr) { 1002 ret = -EBUSY; 1003 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n", 1004 &qproc->mdata_phys, size); 1005 goto free_metadata; 1006 } 1007 } else { 1008 ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs); 1009 if (!ptr) { 1010 ret = -ENOMEM; 1011 dev_err(qproc->dev, "failed to allocate mdt buffer\n"); 1012 goto free_metadata; 1013 } 1014 } 1015 1016 memcpy(ptr, metadata, size); 1017 1018 if (qproc->mdata_phys) 1019 memunmap(ptr); 1020 1021 /* Hypervisor mapping to access metadata by modem */ 1022 mdata_perm = BIT(QCOM_SCM_VMID_HLOS); 1023 ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true, 1024 phys, size); 1025 if (ret) { 1026 dev_err(qproc->dev, 1027 "assigning Q6 access to metadata failed: %d\n", ret); 1028 ret = -EAGAIN; 1029 goto free_dma_attrs; 1030 } 1031 1032 writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG); 1033 writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG); 1034 1035 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000); 1036 if (ret == -ETIMEDOUT) 1037 dev_err(qproc->dev, "MPSS header authentication timed out\n"); 1038 else if (ret < 0) 1039 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret); 1040 1041 /* Metadata authentication done, remove modem access */ 1042 xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false, 1043 phys, size); 1044 if (xferop_ret) 1045 dev_warn(qproc->dev, 1046 "mdt buffer not reclaimed system may become unstable\n"); 1047 1048 free_dma_attrs: 1049 if (!qproc->mdata_phys) 1050 dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs); 1051 free_metadata: 1052 kfree(metadata); 1053 1054 return ret < 0 ? ret : 0; 1055 } 1056 1057 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr) 1058 { 1059 if (phdr->p_type != PT_LOAD) 1060 return false; 1061 1062 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH) 1063 return false; 1064 1065 if (!phdr->p_memsz) 1066 return false; 1067 1068 return true; 1069 } 1070 1071 static int q6v5_mba_load(struct q6v5 *qproc) 1072 { 1073 int ret; 1074 int xfermemop_ret; 1075 bool mba_load_err = false; 1076 1077 ret = qcom_q6v5_prepare(&qproc->q6v5); 1078 if (ret) 1079 return ret; 1080 1081 ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); 1082 if (ret < 0) { 1083 dev_err(qproc->dev, "failed to enable proxy power domains\n"); 1084 goto disable_irqs; 1085 } 1086 1087 ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs, 1088 qproc->fallback_proxy_reg_count); 1089 if (ret) { 1090 dev_err(qproc->dev, "failed to enable fallback proxy supplies\n"); 1091 goto disable_proxy_pds; 1092 } 1093 1094 ret = q6v5_regulator_enable(qproc, qproc->proxy_regs, 1095 qproc->proxy_reg_count); 1096 if (ret) { 1097 dev_err(qproc->dev, "failed to enable proxy supplies\n"); 1098 goto disable_fallback_proxy_reg; 1099 } 1100 1101 ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks, 1102 qproc->proxy_clk_count); 1103 if (ret) { 1104 dev_err(qproc->dev, "failed to enable proxy clocks\n"); 1105 goto disable_proxy_reg; 1106 } 1107 1108 ret = q6v5_regulator_enable(qproc, qproc->active_regs, 1109 qproc->active_reg_count); 1110 if (ret) { 1111 dev_err(qproc->dev, "failed to enable supplies\n"); 1112 goto disable_proxy_clk; 1113 } 1114 1115 ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks, 1116 qproc->reset_clk_count); 1117 if (ret) { 1118 dev_err(qproc->dev, "failed to enable reset clocks\n"); 1119 goto disable_vdd; 1120 } 1121 1122 ret = q6v5_reset_deassert(qproc); 1123 if (ret) { 1124 dev_err(qproc->dev, "failed to deassert mss restart\n"); 1125 goto disable_reset_clks; 1126 } 1127 1128 ret = q6v5_clk_enable(qproc->dev, qproc->active_clks, 1129 qproc->active_clk_count); 1130 if (ret) { 1131 dev_err(qproc->dev, "failed to enable clocks\n"); 1132 goto assert_reset; 1133 } 1134 1135 ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi); 1136 if (ret) { 1137 dev_err(qproc->dev, "failed to enable axi bridge\n"); 1138 goto disable_active_clks; 1139 } 1140 1141 /* 1142 * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide 1143 * the Q6 access to this region. 1144 */ 1145 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true, 1146 qproc->mpss_phys, qproc->mpss_size); 1147 if (ret) { 1148 dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret); 1149 goto disable_active_clks; 1150 } 1151 1152 /* Assign MBA image access in DDR to q6 */ 1153 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true, 1154 qproc->mba_phys, qproc->mba_size); 1155 if (ret) { 1156 dev_err(qproc->dev, 1157 "assigning Q6 access to mba memory failed: %d\n", ret); 1158 goto disable_active_clks; 1159 } 1160 1161 if (qproc->has_mba_logs) 1162 qcom_pil_info_store("mba", qproc->mba_phys, MBA_LOG_SIZE); 1163 1164 writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG); 1165 if (qproc->dp_size) { 1166 writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG); 1167 writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); 1168 } 1169 1170 ret = q6v5proc_reset(qproc); 1171 if (ret) 1172 goto reclaim_mba; 1173 1174 ret = q6v5_rmb_mba_wait(qproc, 0, 5000); 1175 if (ret == -ETIMEDOUT) { 1176 dev_err(qproc->dev, "MBA boot timed out\n"); 1177 goto halt_axi_ports; 1178 } else if (ret != RMB_MBA_XPU_UNLOCKED && 1179 ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) { 1180 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret); 1181 ret = -EINVAL; 1182 goto halt_axi_ports; 1183 } 1184 1185 qproc->dump_mba_loaded = true; 1186 return 0; 1187 1188 halt_axi_ports: 1189 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); 1190 if (qproc->has_vq6) 1191 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6); 1192 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); 1193 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); 1194 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm); 1195 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx); 1196 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi); 1197 mba_load_err = true; 1198 reclaim_mba: 1199 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, 1200 false, qproc->mba_phys, 1201 qproc->mba_size); 1202 if (xfermemop_ret) { 1203 dev_err(qproc->dev, 1204 "Failed to reclaim mba buffer, system may become unstable\n"); 1205 } else if (mba_load_err) { 1206 q6v5_dump_mba_logs(qproc); 1207 } 1208 1209 disable_active_clks: 1210 q6v5_clk_disable(qproc->dev, qproc->active_clks, 1211 qproc->active_clk_count); 1212 assert_reset: 1213 q6v5_reset_assert(qproc); 1214 disable_reset_clks: 1215 q6v5_clk_disable(qproc->dev, qproc->reset_clks, 1216 qproc->reset_clk_count); 1217 disable_vdd: 1218 q6v5_regulator_disable(qproc, qproc->active_regs, 1219 qproc->active_reg_count); 1220 disable_proxy_clk: 1221 q6v5_clk_disable(qproc->dev, qproc->proxy_clks, 1222 qproc->proxy_clk_count); 1223 disable_proxy_reg: 1224 q6v5_regulator_disable(qproc, qproc->proxy_regs, 1225 qproc->proxy_reg_count); 1226 disable_fallback_proxy_reg: 1227 q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs, 1228 qproc->fallback_proxy_reg_count); 1229 disable_proxy_pds: 1230 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); 1231 disable_irqs: 1232 qcom_q6v5_unprepare(&qproc->q6v5); 1233 1234 return ret; 1235 } 1236 1237 static void q6v5_mba_reclaim(struct q6v5 *qproc) 1238 { 1239 int ret; 1240 u32 val; 1241 1242 qproc->dump_mba_loaded = false; 1243 qproc->dp_size = 0; 1244 1245 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); 1246 if (qproc->has_vq6) 1247 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6); 1248 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); 1249 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); 1250 if (qproc->version == MSS_MSM8996) { 1251 /* 1252 * To avoid high MX current during LPASS/MSS restart. 1253 */ 1254 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 1255 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL | 1256 QDSP6v56_CLAMP_QMC_MEM; 1257 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 1258 } 1259 1260 if (qproc->has_ext_cntl_regs) { 1261 regmap_write(qproc->conn_map, qproc->rscc_disable, 1); 1262 1263 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val, 1264 !val, 1, Q6SS_CBCR_TIMEOUT_US); 1265 if (ret) 1266 dev_err(qproc->dev, "failed to enable axim1 clock\n"); 1267 1268 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val, 1269 !val, 1, Q6SS_CBCR_TIMEOUT_US); 1270 if (ret) 1271 dev_err(qproc->dev, "failed to enable crypto clock\n"); 1272 } 1273 1274 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm); 1275 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx); 1276 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi); 1277 1278 q6v5_reset_assert(qproc); 1279 1280 q6v5_clk_disable(qproc->dev, qproc->reset_clks, 1281 qproc->reset_clk_count); 1282 q6v5_clk_disable(qproc->dev, qproc->active_clks, 1283 qproc->active_clk_count); 1284 q6v5_regulator_disable(qproc, qproc->active_regs, 1285 qproc->active_reg_count); 1286 1287 /* In case of failure or coredump scenario where reclaiming MBA memory 1288 * could not happen reclaim it here. 1289 */ 1290 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, 1291 qproc->mba_phys, 1292 qproc->mba_size); 1293 WARN_ON(ret); 1294 1295 ret = qcom_q6v5_unprepare(&qproc->q6v5); 1296 if (ret) { 1297 q6v5_pds_disable(qproc, qproc->proxy_pds, 1298 qproc->proxy_pd_count); 1299 q6v5_clk_disable(qproc->dev, qproc->proxy_clks, 1300 qproc->proxy_clk_count); 1301 q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs, 1302 qproc->fallback_proxy_reg_count); 1303 q6v5_regulator_disable(qproc, qproc->proxy_regs, 1304 qproc->proxy_reg_count); 1305 } 1306 } 1307 1308 static int q6v5_reload_mba(struct rproc *rproc) 1309 { 1310 struct q6v5 *qproc = rproc->priv; 1311 const struct firmware *fw; 1312 int ret; 1313 1314 ret = request_firmware(&fw, rproc->firmware, qproc->dev); 1315 if (ret < 0) 1316 return ret; 1317 1318 q6v5_load(rproc, fw); 1319 ret = q6v5_mba_load(qproc); 1320 release_firmware(fw); 1321 1322 return ret; 1323 } 1324 1325 static int q6v5_mpss_load(struct q6v5 *qproc) 1326 { 1327 const struct elf32_phdr *phdrs; 1328 const struct elf32_phdr *phdr; 1329 const struct firmware *seg_fw; 1330 const struct firmware *fw; 1331 struct elf32_hdr *ehdr; 1332 phys_addr_t mpss_reloc; 1333 phys_addr_t boot_addr; 1334 phys_addr_t min_addr = PHYS_ADDR_MAX; 1335 phys_addr_t max_addr = 0; 1336 u32 code_length; 1337 bool relocate = false; 1338 char *fw_name; 1339 size_t fw_name_len; 1340 ssize_t offset; 1341 size_t size = 0; 1342 void *ptr; 1343 int ret; 1344 int i; 1345 1346 fw_name_len = strlen(qproc->hexagon_mdt_image); 1347 if (fw_name_len <= 4) 1348 return -EINVAL; 1349 1350 fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL); 1351 if (!fw_name) 1352 return -ENOMEM; 1353 1354 ret = request_firmware(&fw, fw_name, qproc->dev); 1355 if (ret < 0) { 1356 dev_err(qproc->dev, "unable to load %s\n", fw_name); 1357 goto out; 1358 } 1359 1360 /* Initialize the RMB validator */ 1361 writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); 1362 1363 ret = q6v5_mpss_init_image(qproc, fw, qproc->hexagon_mdt_image); 1364 if (ret) 1365 goto release_firmware; 1366 1367 ehdr = (struct elf32_hdr *)fw->data; 1368 phdrs = (struct elf32_phdr *)(ehdr + 1); 1369 1370 for (i = 0; i < ehdr->e_phnum; i++) { 1371 phdr = &phdrs[i]; 1372 1373 if (!q6v5_phdr_valid(phdr)) 1374 continue; 1375 1376 if (phdr->p_flags & QCOM_MDT_RELOCATABLE) 1377 relocate = true; 1378 1379 if (phdr->p_paddr < min_addr) 1380 min_addr = phdr->p_paddr; 1381 1382 if (phdr->p_paddr + phdr->p_memsz > max_addr) 1383 max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K); 1384 } 1385 1386 if (qproc->version == MSS_MSM8953) { 1387 ret = qcom_scm_pas_mem_setup(MPSS_PAS_ID, qproc->mpss_phys, qproc->mpss_size); 1388 if (ret) { 1389 dev_err(qproc->dev, 1390 "setting up mpss memory failed: %d\n", ret); 1391 goto release_firmware; 1392 } 1393 } 1394 1395 /* 1396 * In case of a modem subsystem restart on secure devices, the modem 1397 * memory can be reclaimed only after MBA is loaded. 1398 */ 1399 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false, 1400 qproc->mpss_phys, qproc->mpss_size); 1401 1402 /* Share ownership between Linux and MSS, during segment loading */ 1403 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true, 1404 qproc->mpss_phys, qproc->mpss_size); 1405 if (ret) { 1406 dev_err(qproc->dev, 1407 "assigning Q6 access to mpss memory failed: %d\n", ret); 1408 ret = -EAGAIN; 1409 goto release_firmware; 1410 } 1411 1412 mpss_reloc = relocate ? min_addr : qproc->mpss_phys; 1413 qproc->mpss_reloc = mpss_reloc; 1414 /* Load firmware segments */ 1415 for (i = 0; i < ehdr->e_phnum; i++) { 1416 phdr = &phdrs[i]; 1417 1418 if (!q6v5_phdr_valid(phdr)) 1419 continue; 1420 1421 offset = phdr->p_paddr - mpss_reloc; 1422 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) { 1423 dev_err(qproc->dev, "segment outside memory range\n"); 1424 ret = -EINVAL; 1425 goto release_firmware; 1426 } 1427 1428 if (phdr->p_filesz > phdr->p_memsz) { 1429 dev_err(qproc->dev, 1430 "refusing to load segment %d with p_filesz > p_memsz\n", 1431 i); 1432 ret = -EINVAL; 1433 goto release_firmware; 1434 } 1435 1436 ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC); 1437 if (!ptr) { 1438 dev_err(qproc->dev, 1439 "unable to map memory region: %pa+%zx-%x\n", 1440 &qproc->mpss_phys, offset, phdr->p_memsz); 1441 goto release_firmware; 1442 } 1443 1444 if (phdr->p_filesz && phdr->p_offset < fw->size) { 1445 /* Firmware is large enough to be non-split */ 1446 if (phdr->p_offset + phdr->p_filesz > fw->size) { 1447 dev_err(qproc->dev, 1448 "failed to load segment %d from truncated file %s\n", 1449 i, fw_name); 1450 ret = -EINVAL; 1451 memunmap(ptr); 1452 goto release_firmware; 1453 } 1454 1455 memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz); 1456 } else if (phdr->p_filesz) { 1457 /* Replace "xxx.xxx" with "xxx.bxx" */ 1458 sprintf(fw_name + fw_name_len - 3, "b%02d", i); 1459 ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev, 1460 ptr, phdr->p_filesz); 1461 if (ret) { 1462 dev_err(qproc->dev, "failed to load %s\n", fw_name); 1463 memunmap(ptr); 1464 goto release_firmware; 1465 } 1466 1467 if (seg_fw->size != phdr->p_filesz) { 1468 dev_err(qproc->dev, 1469 "failed to load segment %d from truncated file %s\n", 1470 i, fw_name); 1471 ret = -EINVAL; 1472 release_firmware(seg_fw); 1473 memunmap(ptr); 1474 goto release_firmware; 1475 } 1476 1477 release_firmware(seg_fw); 1478 } 1479 1480 if (phdr->p_memsz > phdr->p_filesz) { 1481 memset(ptr + phdr->p_filesz, 0, 1482 phdr->p_memsz - phdr->p_filesz); 1483 } 1484 memunmap(ptr); 1485 size += phdr->p_memsz; 1486 1487 code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); 1488 if (!code_length) { 1489 boot_addr = relocate ? qproc->mpss_phys : min_addr; 1490 writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG); 1491 writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG); 1492 } 1493 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); 1494 1495 ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG); 1496 if (ret < 0) { 1497 dev_err(qproc->dev, "MPSS authentication failed: %d\n", 1498 ret); 1499 goto release_firmware; 1500 } 1501 } 1502 1503 /* Transfer ownership of modem ddr region to q6 */ 1504 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true, 1505 qproc->mpss_phys, qproc->mpss_size); 1506 if (ret) { 1507 dev_err(qproc->dev, 1508 "assigning Q6 access to mpss memory failed: %d\n", ret); 1509 ret = -EAGAIN; 1510 goto release_firmware; 1511 } 1512 1513 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000); 1514 if (ret == -ETIMEDOUT) 1515 dev_err(qproc->dev, "MPSS authentication timed out\n"); 1516 else if (ret < 0) 1517 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret); 1518 1519 qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size); 1520 1521 release_firmware: 1522 release_firmware(fw); 1523 out: 1524 kfree(fw_name); 1525 1526 return ret < 0 ? ret : 0; 1527 } 1528 1529 static void qcom_q6v5_dump_segment(struct rproc *rproc, 1530 struct rproc_dump_segment *segment, 1531 void *dest, size_t cp_offset, size_t size) 1532 { 1533 int ret = 0; 1534 struct q6v5 *qproc = rproc->priv; 1535 int offset = segment->da - qproc->mpss_reloc; 1536 void *ptr = NULL; 1537 1538 /* Unlock mba before copying segments */ 1539 if (!qproc->dump_mba_loaded) { 1540 ret = q6v5_reload_mba(rproc); 1541 if (!ret) { 1542 /* Reset ownership back to Linux to copy segments */ 1543 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, 1544 true, false, 1545 qproc->mpss_phys, 1546 qproc->mpss_size); 1547 } 1548 } 1549 1550 if (!ret) 1551 ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC); 1552 1553 if (ptr) { 1554 memcpy(dest, ptr, size); 1555 memunmap(ptr); 1556 } else { 1557 memset(dest, 0xff, size); 1558 } 1559 1560 qproc->current_dump_size += size; 1561 1562 /* Reclaim mba after copying segments */ 1563 if (qproc->current_dump_size == qproc->total_dump_size) { 1564 if (qproc->dump_mba_loaded) { 1565 /* Try to reset ownership back to Q6 */ 1566 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, 1567 false, true, 1568 qproc->mpss_phys, 1569 qproc->mpss_size); 1570 q6v5_mba_reclaim(qproc); 1571 } 1572 } 1573 } 1574 1575 static int q6v5_start(struct rproc *rproc) 1576 { 1577 struct q6v5 *qproc = rproc->priv; 1578 int xfermemop_ret; 1579 int ret; 1580 1581 ret = q6v5_mba_load(qproc); 1582 if (ret) 1583 return ret; 1584 1585 dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n", 1586 qproc->dp_size ? "" : "out"); 1587 1588 ret = q6v5_mpss_load(qproc); 1589 if (ret) 1590 goto reclaim_mpss; 1591 1592 ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000)); 1593 if (ret == -ETIMEDOUT) { 1594 dev_err(qproc->dev, "start timed out\n"); 1595 goto reclaim_mpss; 1596 } 1597 1598 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, 1599 false, qproc->mba_phys, 1600 qproc->mba_size); 1601 if (xfermemop_ret) 1602 dev_err(qproc->dev, 1603 "Failed to reclaim mba buffer system may become unstable\n"); 1604 1605 /* Reset Dump Segment Mask */ 1606 qproc->current_dump_size = 0; 1607 1608 return 0; 1609 1610 reclaim_mpss: 1611 q6v5_mba_reclaim(qproc); 1612 q6v5_dump_mba_logs(qproc); 1613 1614 return ret; 1615 } 1616 1617 static int q6v5_stop(struct rproc *rproc) 1618 { 1619 struct q6v5 *qproc = rproc->priv; 1620 int ret; 1621 1622 ret = qcom_q6v5_request_stop(&qproc->q6v5, qproc->sysmon); 1623 if (ret == -ETIMEDOUT) 1624 dev_err(qproc->dev, "timed out on wait\n"); 1625 1626 q6v5_mba_reclaim(qproc); 1627 1628 return 0; 1629 } 1630 1631 static int qcom_q6v5_register_dump_segments(struct rproc *rproc, 1632 const struct firmware *mba_fw) 1633 { 1634 const struct firmware *fw; 1635 const struct elf32_phdr *phdrs; 1636 const struct elf32_phdr *phdr; 1637 const struct elf32_hdr *ehdr; 1638 struct q6v5 *qproc = rproc->priv; 1639 unsigned long i; 1640 int ret; 1641 1642 ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev); 1643 if (ret < 0) { 1644 dev_err(qproc->dev, "unable to load %s\n", 1645 qproc->hexagon_mdt_image); 1646 return ret; 1647 } 1648 1649 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); 1650 1651 ehdr = (struct elf32_hdr *)fw->data; 1652 phdrs = (struct elf32_phdr *)(ehdr + 1); 1653 qproc->total_dump_size = 0; 1654 1655 for (i = 0; i < ehdr->e_phnum; i++) { 1656 phdr = &phdrs[i]; 1657 1658 if (!q6v5_phdr_valid(phdr)) 1659 continue; 1660 1661 ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr, 1662 phdr->p_memsz, 1663 qcom_q6v5_dump_segment, 1664 NULL); 1665 if (ret) 1666 break; 1667 1668 qproc->total_dump_size += phdr->p_memsz; 1669 } 1670 1671 release_firmware(fw); 1672 return ret; 1673 } 1674 1675 static unsigned long q6v5_panic(struct rproc *rproc) 1676 { 1677 struct q6v5 *qproc = rproc->priv; 1678 1679 return qcom_q6v5_panic(&qproc->q6v5); 1680 } 1681 1682 static const struct rproc_ops q6v5_ops = { 1683 .start = q6v5_start, 1684 .stop = q6v5_stop, 1685 .parse_fw = qcom_q6v5_register_dump_segments, 1686 .load = q6v5_load, 1687 .panic = q6v5_panic, 1688 }; 1689 1690 static void qcom_msa_handover(struct qcom_q6v5 *q6v5) 1691 { 1692 struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5); 1693 1694 q6v5_clk_disable(qproc->dev, qproc->proxy_clks, 1695 qproc->proxy_clk_count); 1696 q6v5_regulator_disable(qproc, qproc->proxy_regs, 1697 qproc->proxy_reg_count); 1698 q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs, 1699 qproc->fallback_proxy_reg_count); 1700 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); 1701 } 1702 1703 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev) 1704 { 1705 struct of_phandle_args args; 1706 int halt_cell_cnt = 3; 1707 int ret; 1708 1709 qproc->reg_base = devm_platform_ioremap_resource_byname(pdev, "qdsp6"); 1710 if (IS_ERR(qproc->reg_base)) 1711 return PTR_ERR(qproc->reg_base); 1712 1713 qproc->rmb_base = devm_platform_ioremap_resource_byname(pdev, "rmb"); 1714 if (IS_ERR(qproc->rmb_base)) 1715 return PTR_ERR(qproc->rmb_base); 1716 1717 if (qproc->has_vq6) 1718 halt_cell_cnt++; 1719 1720 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, 1721 "qcom,halt-regs", halt_cell_cnt, 0, &args); 1722 if (ret < 0) { 1723 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); 1724 return -EINVAL; 1725 } 1726 1727 qproc->halt_map = syscon_node_to_regmap(args.np); 1728 of_node_put(args.np); 1729 if (IS_ERR(qproc->halt_map)) 1730 return PTR_ERR(qproc->halt_map); 1731 1732 qproc->halt_q6 = args.args[0]; 1733 qproc->halt_modem = args.args[1]; 1734 qproc->halt_nc = args.args[2]; 1735 1736 if (qproc->has_vq6) 1737 qproc->halt_vq6 = args.args[3]; 1738 1739 if (qproc->has_qaccept_regs) { 1740 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, 1741 "qcom,qaccept-regs", 1742 3, 0, &args); 1743 if (ret < 0) { 1744 dev_err(&pdev->dev, "failed to parse qaccept-regs\n"); 1745 return -EINVAL; 1746 } 1747 1748 qproc->qaccept_mdm = args.args[0]; 1749 qproc->qaccept_cx = args.args[1]; 1750 qproc->qaccept_axi = args.args[2]; 1751 } 1752 1753 if (qproc->has_ext_cntl_regs) { 1754 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, 1755 "qcom,ext-regs", 1756 2, 0, &args); 1757 if (ret < 0) { 1758 dev_err(&pdev->dev, "failed to parse ext-regs index 0\n"); 1759 return -EINVAL; 1760 } 1761 1762 qproc->conn_map = syscon_node_to_regmap(args.np); 1763 of_node_put(args.np); 1764 if (IS_ERR(qproc->conn_map)) 1765 return PTR_ERR(qproc->conn_map); 1766 1767 qproc->force_clk_on = args.args[0]; 1768 qproc->rscc_disable = args.args[1]; 1769 1770 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, 1771 "qcom,ext-regs", 1772 2, 1, &args); 1773 if (ret < 0) { 1774 dev_err(&pdev->dev, "failed to parse ext-regs index 1\n"); 1775 return -EINVAL; 1776 } 1777 1778 qproc->axim1_clk_off = args.args[0]; 1779 qproc->crypto_clk_off = args.args[1]; 1780 } 1781 1782 if (qproc->has_spare_reg) { 1783 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, 1784 "qcom,spare-regs", 1785 1, 0, &args); 1786 if (ret < 0) { 1787 dev_err(&pdev->dev, "failed to parse spare-regs\n"); 1788 return -EINVAL; 1789 } 1790 1791 qproc->conn_map = syscon_node_to_regmap(args.np); 1792 of_node_put(args.np); 1793 if (IS_ERR(qproc->conn_map)) 1794 return PTR_ERR(qproc->conn_map); 1795 1796 qproc->conn_box = args.args[0]; 1797 } 1798 1799 return 0; 1800 } 1801 1802 static int q6v5_init_clocks(struct device *dev, struct clk **clks, 1803 char **clk_names) 1804 { 1805 int i; 1806 1807 if (!clk_names) 1808 return 0; 1809 1810 for (i = 0; clk_names[i]; i++) { 1811 clks[i] = devm_clk_get(dev, clk_names[i]); 1812 if (IS_ERR(clks[i])) 1813 return dev_err_probe(dev, PTR_ERR(clks[i]), 1814 "Failed to get %s clock\n", 1815 clk_names[i]); 1816 } 1817 1818 return i; 1819 } 1820 1821 static int q6v5_pds_attach(struct device *dev, struct device **devs, 1822 char **pd_names) 1823 { 1824 size_t num_pds = 0; 1825 int ret; 1826 int i; 1827 1828 if (!pd_names) 1829 return 0; 1830 1831 while (pd_names[num_pds]) 1832 num_pds++; 1833 1834 for (i = 0; i < num_pds; i++) { 1835 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); 1836 if (IS_ERR_OR_NULL(devs[i])) { 1837 ret = PTR_ERR(devs[i]) ? : -ENODATA; 1838 goto unroll_attach; 1839 } 1840 } 1841 1842 return num_pds; 1843 1844 unroll_attach: 1845 for (i--; i >= 0; i--) 1846 dev_pm_domain_detach(devs[i], false); 1847 1848 return ret; 1849 } 1850 1851 static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds, 1852 size_t pd_count) 1853 { 1854 int i; 1855 1856 for (i = 0; i < pd_count; i++) 1857 dev_pm_domain_detach(pds[i], false); 1858 } 1859 1860 static int q6v5_init_reset(struct q6v5 *qproc) 1861 { 1862 qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev, 1863 "mss_restart"); 1864 if (IS_ERR(qproc->mss_restart)) { 1865 dev_err(qproc->dev, "failed to acquire mss restart\n"); 1866 return PTR_ERR(qproc->mss_restart); 1867 } 1868 1869 if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) { 1870 qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev, 1871 "pdc_reset"); 1872 if (IS_ERR(qproc->pdc_reset)) { 1873 dev_err(qproc->dev, "failed to acquire pdc reset\n"); 1874 return PTR_ERR(qproc->pdc_reset); 1875 } 1876 } 1877 1878 return 0; 1879 } 1880 1881 static int q6v5_alloc_memory_region(struct q6v5 *qproc) 1882 { 1883 struct device_node *child; 1884 struct reserved_mem *rmem; 1885 struct device_node *node; 1886 1887 /* 1888 * In the absence of mba/mpss sub-child, extract the mba and mpss 1889 * reserved memory regions from device's memory-region property. 1890 */ 1891 child = of_get_child_by_name(qproc->dev->of_node, "mba"); 1892 if (!child) { 1893 node = of_parse_phandle(qproc->dev->of_node, 1894 "memory-region", 0); 1895 } else { 1896 node = of_parse_phandle(child, "memory-region", 0); 1897 of_node_put(child); 1898 } 1899 1900 if (!node) { 1901 dev_err(qproc->dev, "no mba memory-region specified\n"); 1902 return -EINVAL; 1903 } 1904 1905 rmem = of_reserved_mem_lookup(node); 1906 of_node_put(node); 1907 if (!rmem) { 1908 dev_err(qproc->dev, "unable to resolve mba region\n"); 1909 return -EINVAL; 1910 } 1911 1912 qproc->mba_phys = rmem->base; 1913 qproc->mba_size = rmem->size; 1914 1915 if (!child) { 1916 node = of_parse_phandle(qproc->dev->of_node, 1917 "memory-region", 1); 1918 } else { 1919 child = of_get_child_by_name(qproc->dev->of_node, "mpss"); 1920 node = of_parse_phandle(child, "memory-region", 0); 1921 of_node_put(child); 1922 } 1923 1924 if (!node) { 1925 dev_err(qproc->dev, "no mpss memory-region specified\n"); 1926 return -EINVAL; 1927 } 1928 1929 rmem = of_reserved_mem_lookup(node); 1930 of_node_put(node); 1931 if (!rmem) { 1932 dev_err(qproc->dev, "unable to resolve mpss region\n"); 1933 return -EINVAL; 1934 } 1935 1936 qproc->mpss_phys = qproc->mpss_reloc = rmem->base; 1937 qproc->mpss_size = rmem->size; 1938 1939 if (!child) { 1940 node = of_parse_phandle(qproc->dev->of_node, "memory-region", 2); 1941 } else { 1942 child = of_get_child_by_name(qproc->dev->of_node, "metadata"); 1943 node = of_parse_phandle(child, "memory-region", 0); 1944 of_node_put(child); 1945 } 1946 1947 if (!node) 1948 return 0; 1949 1950 rmem = of_reserved_mem_lookup(node); 1951 if (!rmem) { 1952 dev_err(qproc->dev, "unable to resolve metadata region\n"); 1953 return -EINVAL; 1954 } 1955 1956 qproc->mdata_phys = rmem->base; 1957 qproc->mdata_size = rmem->size; 1958 1959 return 0; 1960 } 1961 1962 static int q6v5_probe(struct platform_device *pdev) 1963 { 1964 const struct rproc_hexagon_res *desc; 1965 struct device_node *node; 1966 struct q6v5 *qproc; 1967 struct rproc *rproc; 1968 const char *mba_image; 1969 int ret; 1970 1971 desc = of_device_get_match_data(&pdev->dev); 1972 if (!desc) 1973 return -EINVAL; 1974 1975 if (desc->need_mem_protection && !qcom_scm_is_available()) 1976 return -EPROBE_DEFER; 1977 1978 mba_image = desc->hexagon_mba_image; 1979 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name", 1980 0, &mba_image); 1981 if (ret < 0 && ret != -EINVAL) { 1982 dev_err(&pdev->dev, "unable to read mba firmware-name\n"); 1983 return ret; 1984 } 1985 1986 rproc = devm_rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops, 1987 mba_image, sizeof(*qproc)); 1988 if (!rproc) { 1989 dev_err(&pdev->dev, "failed to allocate rproc\n"); 1990 return -ENOMEM; 1991 } 1992 1993 rproc->auto_boot = false; 1994 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); 1995 1996 qproc = rproc->priv; 1997 qproc->dev = &pdev->dev; 1998 qproc->rproc = rproc; 1999 qproc->hexagon_mdt_image = "modem.mdt"; 2000 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name", 2001 1, &qproc->hexagon_mdt_image); 2002 if (ret < 0 && ret != -EINVAL) { 2003 dev_err(&pdev->dev, "unable to read mpss firmware-name\n"); 2004 return ret; 2005 } 2006 2007 platform_set_drvdata(pdev, qproc); 2008 2009 qproc->has_qaccept_regs = desc->has_qaccept_regs; 2010 qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs; 2011 qproc->has_vq6 = desc->has_vq6; 2012 qproc->has_spare_reg = desc->has_spare_reg; 2013 ret = q6v5_init_mem(qproc, pdev); 2014 if (ret) 2015 return ret; 2016 2017 ret = q6v5_alloc_memory_region(qproc); 2018 if (ret) 2019 return ret; 2020 2021 ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks, 2022 desc->proxy_clk_names); 2023 if (ret < 0) 2024 return ret; 2025 qproc->proxy_clk_count = ret; 2026 2027 ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks, 2028 desc->reset_clk_names); 2029 if (ret < 0) 2030 return ret; 2031 qproc->reset_clk_count = ret; 2032 2033 ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks, 2034 desc->active_clk_names); 2035 if (ret < 0) 2036 return ret; 2037 qproc->active_clk_count = ret; 2038 2039 ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs, 2040 desc->proxy_supply); 2041 if (ret < 0) 2042 return ret; 2043 qproc->proxy_reg_count = ret; 2044 2045 ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs, 2046 desc->active_supply); 2047 if (ret < 0) 2048 return ret; 2049 qproc->active_reg_count = ret; 2050 2051 ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds, 2052 desc->proxy_pd_names); 2053 /* Fallback to regulators for old device trees */ 2054 if (ret == -ENODATA && desc->fallback_proxy_supply) { 2055 ret = q6v5_regulator_init(&pdev->dev, 2056 qproc->fallback_proxy_regs, 2057 desc->fallback_proxy_supply); 2058 if (ret < 0) 2059 return ret; 2060 qproc->fallback_proxy_reg_count = ret; 2061 } else if (ret < 0) { 2062 dev_err(&pdev->dev, "Failed to init power domains\n"); 2063 return ret; 2064 } else { 2065 qproc->proxy_pd_count = ret; 2066 } 2067 2068 qproc->has_alt_reset = desc->has_alt_reset; 2069 ret = q6v5_init_reset(qproc); 2070 if (ret) 2071 goto detach_proxy_pds; 2072 2073 qproc->version = desc->version; 2074 qproc->need_mem_protection = desc->need_mem_protection; 2075 qproc->has_mba_logs = desc->has_mba_logs; 2076 2077 ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, "modem", 2078 qcom_msa_handover); 2079 if (ret) 2080 goto detach_proxy_pds; 2081 2082 qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS); 2083 qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS); 2084 qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss"); 2085 qcom_add_smd_subdev(rproc, &qproc->smd_subdev); 2086 qcom_add_pdm_subdev(rproc, &qproc->pdm_subdev); 2087 qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss"); 2088 qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12); 2089 if (IS_ERR(qproc->sysmon)) { 2090 ret = PTR_ERR(qproc->sysmon); 2091 goto remove_subdevs; 2092 } 2093 2094 ret = rproc_add(rproc); 2095 if (ret) 2096 goto remove_sysmon_subdev; 2097 2098 node = of_get_compatible_child(pdev->dev.of_node, "qcom,bam-dmux"); 2099 qproc->bam_dmux = of_platform_device_create(node, NULL, &pdev->dev); 2100 of_node_put(node); 2101 2102 return 0; 2103 2104 remove_sysmon_subdev: 2105 qcom_remove_sysmon_subdev(qproc->sysmon); 2106 remove_subdevs: 2107 qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev); 2108 qcom_remove_smd_subdev(rproc, &qproc->smd_subdev); 2109 qcom_remove_glink_subdev(rproc, &qproc->glink_subdev); 2110 detach_proxy_pds: 2111 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); 2112 2113 return ret; 2114 } 2115 2116 static void q6v5_remove(struct platform_device *pdev) 2117 { 2118 struct q6v5 *qproc = platform_get_drvdata(pdev); 2119 struct rproc *rproc = qproc->rproc; 2120 2121 if (qproc->bam_dmux) 2122 of_platform_device_destroy(&qproc->bam_dmux->dev, NULL); 2123 rproc_del(rproc); 2124 2125 qcom_q6v5_deinit(&qproc->q6v5); 2126 qcom_remove_sysmon_subdev(qproc->sysmon); 2127 qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev); 2128 qcom_remove_pdm_subdev(rproc, &qproc->pdm_subdev); 2129 qcom_remove_smd_subdev(rproc, &qproc->smd_subdev); 2130 qcom_remove_glink_subdev(rproc, &qproc->glink_subdev); 2131 2132 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); 2133 } 2134 2135 static const struct rproc_hexagon_res sc7180_mss = { 2136 .hexagon_mba_image = "mba.mbn", 2137 .proxy_clk_names = (char*[]){ 2138 "xo", 2139 NULL 2140 }, 2141 .reset_clk_names = (char*[]){ 2142 "iface", 2143 "bus", 2144 "snoc_axi", 2145 NULL 2146 }, 2147 .active_clk_names = (char*[]){ 2148 "mnoc_axi", 2149 "nav", 2150 NULL 2151 }, 2152 .proxy_pd_names = (char*[]){ 2153 "cx", 2154 "mx", 2155 "mss", 2156 NULL 2157 }, 2158 .need_mem_protection = true, 2159 .has_alt_reset = false, 2160 .has_mba_logs = true, 2161 .has_spare_reg = true, 2162 .has_qaccept_regs = false, 2163 .has_ext_cntl_regs = false, 2164 .has_vq6 = false, 2165 .version = MSS_SC7180, 2166 }; 2167 2168 static const struct rproc_hexagon_res sc7280_mss = { 2169 .hexagon_mba_image = "mba.mbn", 2170 .proxy_clk_names = (char*[]){ 2171 "xo", 2172 "pka", 2173 NULL 2174 }, 2175 .active_clk_names = (char*[]){ 2176 "iface", 2177 "offline", 2178 "snoc_axi", 2179 NULL 2180 }, 2181 .proxy_pd_names = (char*[]){ 2182 "cx", 2183 "mss", 2184 NULL 2185 }, 2186 .need_mem_protection = true, 2187 .has_alt_reset = false, 2188 .has_mba_logs = true, 2189 .has_spare_reg = false, 2190 .has_qaccept_regs = true, 2191 .has_ext_cntl_regs = true, 2192 .has_vq6 = true, 2193 .version = MSS_SC7280, 2194 }; 2195 2196 static const struct rproc_hexagon_res sdm660_mss = { 2197 .hexagon_mba_image = "mba.mbn", 2198 .proxy_clk_names = (char*[]){ 2199 "xo", 2200 "qdss", 2201 "mem", 2202 NULL 2203 }, 2204 .active_clk_names = (char*[]){ 2205 "iface", 2206 "bus", 2207 "gpll0_mss", 2208 "mnoc_axi", 2209 "snoc_axi", 2210 NULL 2211 }, 2212 .proxy_pd_names = (char*[]){ 2213 "cx", 2214 "mx", 2215 NULL 2216 }, 2217 .need_mem_protection = true, 2218 .has_alt_reset = false, 2219 .has_mba_logs = false, 2220 .has_spare_reg = false, 2221 .has_qaccept_regs = false, 2222 .has_ext_cntl_regs = false, 2223 .has_vq6 = false, 2224 .version = MSS_SDM660, 2225 }; 2226 2227 static const struct rproc_hexagon_res sdm845_mss = { 2228 .hexagon_mba_image = "mba.mbn", 2229 .proxy_clk_names = (char*[]){ 2230 "xo", 2231 "prng", 2232 NULL 2233 }, 2234 .reset_clk_names = (char*[]){ 2235 "iface", 2236 "snoc_axi", 2237 NULL 2238 }, 2239 .active_clk_names = (char*[]){ 2240 "bus", 2241 "mem", 2242 "gpll0_mss", 2243 "mnoc_axi", 2244 NULL 2245 }, 2246 .proxy_pd_names = (char*[]){ 2247 "cx", 2248 "mx", 2249 "mss", 2250 NULL 2251 }, 2252 .need_mem_protection = true, 2253 .has_alt_reset = true, 2254 .has_mba_logs = false, 2255 .has_spare_reg = false, 2256 .has_qaccept_regs = false, 2257 .has_ext_cntl_regs = false, 2258 .has_vq6 = false, 2259 .version = MSS_SDM845, 2260 }; 2261 2262 static const struct rproc_hexagon_res msm8998_mss = { 2263 .hexagon_mba_image = "mba.mbn", 2264 .proxy_clk_names = (char*[]){ 2265 "xo", 2266 "qdss", 2267 "mem", 2268 NULL 2269 }, 2270 .active_clk_names = (char*[]){ 2271 "iface", 2272 "bus", 2273 "gpll0_mss", 2274 "mnoc_axi", 2275 "snoc_axi", 2276 NULL 2277 }, 2278 .proxy_pd_names = (char*[]){ 2279 "cx", 2280 "mx", 2281 NULL 2282 }, 2283 .need_mem_protection = true, 2284 .has_alt_reset = false, 2285 .has_mba_logs = false, 2286 .has_spare_reg = false, 2287 .has_qaccept_regs = false, 2288 .has_ext_cntl_regs = false, 2289 .has_vq6 = false, 2290 .version = MSS_MSM8998, 2291 }; 2292 2293 static const struct rproc_hexagon_res msm8996_mss = { 2294 .hexagon_mba_image = "mba.mbn", 2295 .proxy_supply = (struct qcom_mss_reg_res[]) { 2296 { 2297 .supply = "pll", 2298 .uA = 100000, 2299 }, 2300 {} 2301 }, 2302 .proxy_clk_names = (char*[]){ 2303 "xo", 2304 "qdss", 2305 NULL 2306 }, 2307 .active_clk_names = (char*[]){ 2308 "iface", 2309 "bus", 2310 "mem", 2311 "gpll0_mss", 2312 "snoc_axi", 2313 "mnoc_axi", 2314 NULL 2315 }, 2316 .proxy_pd_names = (char*[]){ 2317 "mx", 2318 "cx", 2319 NULL 2320 }, 2321 .need_mem_protection = true, 2322 .has_alt_reset = false, 2323 .has_mba_logs = false, 2324 .has_spare_reg = false, 2325 .has_qaccept_regs = false, 2326 .has_ext_cntl_regs = false, 2327 .has_vq6 = false, 2328 .version = MSS_MSM8996, 2329 }; 2330 2331 static const struct rproc_hexagon_res msm8909_mss = { 2332 .hexagon_mba_image = "mba.mbn", 2333 .proxy_supply = (struct qcom_mss_reg_res[]) { 2334 { 2335 .supply = "pll", 2336 .uA = 100000, 2337 }, 2338 {} 2339 }, 2340 .proxy_clk_names = (char*[]){ 2341 "xo", 2342 NULL 2343 }, 2344 .active_clk_names = (char*[]){ 2345 "iface", 2346 "bus", 2347 "mem", 2348 NULL 2349 }, 2350 .proxy_pd_names = (char*[]){ 2351 "mx", 2352 "cx", 2353 NULL 2354 }, 2355 .need_mem_protection = false, 2356 .has_alt_reset = false, 2357 .has_mba_logs = false, 2358 .has_spare_reg = false, 2359 .has_qaccept_regs = false, 2360 .has_ext_cntl_regs = false, 2361 .has_vq6 = false, 2362 .version = MSS_MSM8909, 2363 }; 2364 2365 static const struct rproc_hexagon_res msm8916_mss = { 2366 .hexagon_mba_image = "mba.mbn", 2367 .proxy_supply = (struct qcom_mss_reg_res[]) { 2368 { 2369 .supply = "pll", 2370 .uA = 100000, 2371 }, 2372 {} 2373 }, 2374 .fallback_proxy_supply = (struct qcom_mss_reg_res[]) { 2375 { 2376 .supply = "mx", 2377 .uV = 1050000, 2378 }, 2379 { 2380 .supply = "cx", 2381 .uA = 100000, 2382 }, 2383 {} 2384 }, 2385 .proxy_clk_names = (char*[]){ 2386 "xo", 2387 NULL 2388 }, 2389 .active_clk_names = (char*[]){ 2390 "iface", 2391 "bus", 2392 "mem", 2393 NULL 2394 }, 2395 .proxy_pd_names = (char*[]){ 2396 "mx", 2397 "cx", 2398 NULL 2399 }, 2400 .need_mem_protection = false, 2401 .has_alt_reset = false, 2402 .has_mba_logs = false, 2403 .has_spare_reg = false, 2404 .has_qaccept_regs = false, 2405 .has_ext_cntl_regs = false, 2406 .has_vq6 = false, 2407 .version = MSS_MSM8916, 2408 }; 2409 2410 static const struct rproc_hexagon_res msm8953_mss = { 2411 .hexagon_mba_image = "mba.mbn", 2412 .proxy_supply = (struct qcom_mss_reg_res[]) { 2413 { 2414 .supply = "pll", 2415 .uA = 100000, 2416 }, 2417 {} 2418 }, 2419 .proxy_clk_names = (char*[]){ 2420 "xo", 2421 NULL 2422 }, 2423 .active_clk_names = (char*[]){ 2424 "iface", 2425 "bus", 2426 "mem", 2427 NULL 2428 }, 2429 .proxy_pd_names = (char*[]) { 2430 "cx", 2431 "mx", 2432 "mss", 2433 NULL 2434 }, 2435 .need_mem_protection = false, 2436 .has_alt_reset = false, 2437 .has_mba_logs = false, 2438 .has_spare_reg = false, 2439 .has_qaccept_regs = false, 2440 .has_ext_cntl_regs = false, 2441 .has_vq6 = false, 2442 .version = MSS_MSM8953, 2443 }; 2444 2445 static const struct rproc_hexagon_res msm8974_mss = { 2446 .hexagon_mba_image = "mba.b00", 2447 .proxy_supply = (struct qcom_mss_reg_res[]) { 2448 { 2449 .supply = "pll", 2450 .uA = 100000, 2451 }, 2452 {} 2453 }, 2454 .fallback_proxy_supply = (struct qcom_mss_reg_res[]) { 2455 { 2456 .supply = "mx", 2457 .uV = 1050000, 2458 }, 2459 { 2460 .supply = "cx", 2461 .uA = 100000, 2462 }, 2463 {} 2464 }, 2465 .active_supply = (struct qcom_mss_reg_res[]) { 2466 { 2467 .supply = "mss", 2468 .uV = 1050000, 2469 .uA = 100000, 2470 }, 2471 {} 2472 }, 2473 .proxy_clk_names = (char*[]){ 2474 "xo", 2475 NULL 2476 }, 2477 .active_clk_names = (char*[]){ 2478 "iface", 2479 "bus", 2480 "mem", 2481 NULL 2482 }, 2483 .proxy_pd_names = (char*[]){ 2484 "mx", 2485 "cx", 2486 NULL 2487 }, 2488 .need_mem_protection = false, 2489 .has_alt_reset = false, 2490 .has_mba_logs = false, 2491 .has_spare_reg = false, 2492 .has_qaccept_regs = false, 2493 .has_ext_cntl_regs = false, 2494 .has_vq6 = false, 2495 .version = MSS_MSM8974, 2496 }; 2497 2498 static const struct of_device_id q6v5_of_match[] = { 2499 { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss}, 2500 { .compatible = "qcom,msm8909-mss-pil", .data = &msm8909_mss}, 2501 { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss}, 2502 { .compatible = "qcom,msm8953-mss-pil", .data = &msm8953_mss}, 2503 { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss}, 2504 { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss}, 2505 { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss}, 2506 { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss}, 2507 { .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss}, 2508 { .compatible = "qcom,sdm660-mss-pil", .data = &sdm660_mss}, 2509 { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss}, 2510 { }, 2511 }; 2512 MODULE_DEVICE_TABLE(of, q6v5_of_match); 2513 2514 static struct platform_driver q6v5_driver = { 2515 .probe = q6v5_probe, 2516 .remove = q6v5_remove, 2517 .driver = { 2518 .name = "qcom-q6v5-mss", 2519 .of_match_table = q6v5_of_match, 2520 }, 2521 }; 2522 module_platform_driver(q6v5_driver); 2523 2524 MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver"); 2525 MODULE_LICENSE("GPL v2"); 2526