1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm Technology Inc. ADSP Peripheral Image Loader for SDM845. 4 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/firmware.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_domain.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/remoteproc.h> 23 #include <linux/reset.h> 24 #include <linux/soc/qcom/mdt_loader.h> 25 #include <linux/soc/qcom/smem.h> 26 #include <linux/soc/qcom/smem_state.h> 27 28 #include "qcom_common.h" 29 #include "qcom_pil_info.h" 30 #include "qcom_q6v5.h" 31 #include "remoteproc_internal.h" 32 33 /* time out value */ 34 #define ACK_TIMEOUT 1000 35 #define BOOT_FSM_TIMEOUT 10000 36 /* mask values */ 37 #define EVB_MASK GENMASK(27, 4) 38 /*QDSP6SS register offsets*/ 39 #define RST_EVB_REG 0x10 40 #define CORE_START_REG 0x400 41 #define BOOT_CMD_REG 0x404 42 #define BOOT_STATUS_REG 0x408 43 #define RET_CFG_REG 0x1C 44 /*TCSR register offsets*/ 45 #define LPASS_MASTER_IDLE_REG 0x8 46 #define LPASS_HALTACK_REG 0x4 47 #define LPASS_PWR_ON_REG 0x10 48 #define LPASS_HALTREQ_REG 0x0 49 50 #define QDSP6SS_XO_CBCR 0x38 51 #define QDSP6SS_CORE_CBCR 0x20 52 #define QDSP6SS_SLEEP_CBCR 0x3c 53 54 struct adsp_pil_data { 55 int crash_reason_smem; 56 const char *firmware_name; 57 58 const char *ssr_name; 59 const char *sysmon_name; 60 int ssctl_id; 61 62 const char **clk_ids; 63 int num_clks; 64 }; 65 66 struct qcom_adsp { 67 struct device *dev; 68 struct rproc *rproc; 69 70 struct qcom_q6v5 q6v5; 71 72 struct clk *xo; 73 74 int num_clks; 75 struct clk_bulk_data *clks; 76 77 void __iomem *qdsp6ss_base; 78 79 struct reset_control *pdc_sync_reset; 80 struct reset_control *restart; 81 82 struct regmap *halt_map; 83 unsigned int halt_lpass; 84 85 int crash_reason_smem; 86 const char *info_name; 87 88 struct completion start_done; 89 struct completion stop_done; 90 91 phys_addr_t mem_phys; 92 phys_addr_t mem_reloc; 93 void *mem_region; 94 size_t mem_size; 95 96 struct qcom_rproc_glink glink_subdev; 97 struct qcom_rproc_ssr ssr_subdev; 98 struct qcom_sysmon *sysmon; 99 }; 100 101 static int qcom_adsp_shutdown(struct qcom_adsp *adsp) 102 { 103 unsigned long timeout; 104 unsigned int val; 105 int ret; 106 107 /* Reset the retention logic */ 108 val = readl(adsp->qdsp6ss_base + RET_CFG_REG); 109 val |= 0x1; 110 writel(val, adsp->qdsp6ss_base + RET_CFG_REG); 111 112 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks); 113 114 /* QDSP6 master port needs to be explicitly halted */ 115 ret = regmap_read(adsp->halt_map, 116 adsp->halt_lpass + LPASS_PWR_ON_REG, &val); 117 if (ret || !val) 118 goto reset; 119 120 ret = regmap_read(adsp->halt_map, 121 adsp->halt_lpass + LPASS_MASTER_IDLE_REG, 122 &val); 123 if (ret || val) 124 goto reset; 125 126 regmap_write(adsp->halt_map, 127 adsp->halt_lpass + LPASS_HALTREQ_REG, 1); 128 129 /* Wait for halt ACK from QDSP6 */ 130 timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT); 131 for (;;) { 132 ret = regmap_read(adsp->halt_map, 133 adsp->halt_lpass + LPASS_HALTACK_REG, &val); 134 if (ret || val || time_after(jiffies, timeout)) 135 break; 136 137 usleep_range(1000, 1100); 138 } 139 140 ret = regmap_read(adsp->halt_map, 141 adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val); 142 if (ret || !val) 143 dev_err(adsp->dev, "port failed halt\n"); 144 145 reset: 146 /* Assert the LPASS PDC Reset */ 147 reset_control_assert(adsp->pdc_sync_reset); 148 /* Place the LPASS processor into reset */ 149 reset_control_assert(adsp->restart); 150 /* wait after asserting subsystem restart from AOSS */ 151 usleep_range(200, 300); 152 153 /* Clear the halt request for the AXIM and AHBM for Q6 */ 154 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0); 155 156 /* De-assert the LPASS PDC Reset */ 157 reset_control_deassert(adsp->pdc_sync_reset); 158 /* Remove the LPASS reset */ 159 reset_control_deassert(adsp->restart); 160 /* wait after de-asserting subsystem restart from AOSS */ 161 usleep_range(200, 300); 162 163 return 0; 164 } 165 166 static int adsp_load(struct rproc *rproc, const struct firmware *fw) 167 { 168 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 169 int ret; 170 171 ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0, 172 adsp->mem_region, adsp->mem_phys, 173 adsp->mem_size, &adsp->mem_reloc); 174 if (ret) 175 return ret; 176 177 qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size); 178 179 return 0; 180 } 181 182 static int adsp_start(struct rproc *rproc) 183 { 184 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 185 int ret; 186 unsigned int val; 187 188 ret = qcom_q6v5_prepare(&adsp->q6v5); 189 if (ret) 190 return ret; 191 192 ret = clk_prepare_enable(adsp->xo); 193 if (ret) 194 goto disable_irqs; 195 196 dev_pm_genpd_set_performance_state(adsp->dev, INT_MAX); 197 ret = pm_runtime_get_sync(adsp->dev); 198 if (ret) { 199 pm_runtime_put_noidle(adsp->dev); 200 goto disable_xo_clk; 201 } 202 203 ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks); 204 if (ret) { 205 dev_err(adsp->dev, "adsp clk_enable failed\n"); 206 goto disable_power_domain; 207 } 208 209 /* Enable the XO clock */ 210 writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR); 211 212 /* Enable the QDSP6SS sleep clock */ 213 writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR); 214 215 /* Enable the QDSP6 core clock */ 216 writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR); 217 218 /* Program boot address */ 219 writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG); 220 221 /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */ 222 writel(0x1, adsp->qdsp6ss_base + CORE_START_REG); 223 224 /* Trigger boot FSM to start QDSP6 */ 225 writel(0x1, adsp->qdsp6ss_base + BOOT_CMD_REG); 226 227 /* Wait for core to come out of reset */ 228 ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG, 229 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); 230 if (ret) { 231 dev_err(adsp->dev, "failed to bootup adsp\n"); 232 goto disable_adsp_clks; 233 } 234 235 ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5 * HZ)); 236 if (ret == -ETIMEDOUT) { 237 dev_err(adsp->dev, "start timed out\n"); 238 goto disable_adsp_clks; 239 } 240 241 return 0; 242 243 disable_adsp_clks: 244 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks); 245 disable_power_domain: 246 dev_pm_genpd_set_performance_state(adsp->dev, 0); 247 pm_runtime_put(adsp->dev); 248 disable_xo_clk: 249 clk_disable_unprepare(adsp->xo); 250 disable_irqs: 251 qcom_q6v5_unprepare(&adsp->q6v5); 252 253 return ret; 254 } 255 256 static void qcom_adsp_pil_handover(struct qcom_q6v5 *q6v5) 257 { 258 struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5); 259 260 clk_disable_unprepare(adsp->xo); 261 dev_pm_genpd_set_performance_state(adsp->dev, 0); 262 pm_runtime_put(adsp->dev); 263 } 264 265 static int adsp_stop(struct rproc *rproc) 266 { 267 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 268 int handover; 269 int ret; 270 271 ret = qcom_q6v5_request_stop(&adsp->q6v5, adsp->sysmon); 272 if (ret == -ETIMEDOUT) 273 dev_err(adsp->dev, "timed out on wait\n"); 274 275 ret = qcom_adsp_shutdown(adsp); 276 if (ret) 277 dev_err(adsp->dev, "failed to shutdown: %d\n", ret); 278 279 handover = qcom_q6v5_unprepare(&adsp->q6v5); 280 if (handover) 281 qcom_adsp_pil_handover(&adsp->q6v5); 282 283 return ret; 284 } 285 286 static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem) 287 { 288 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 289 int offset; 290 291 offset = da - adsp->mem_reloc; 292 if (offset < 0 || offset + len > adsp->mem_size) 293 return NULL; 294 295 return adsp->mem_region + offset; 296 } 297 298 static unsigned long adsp_panic(struct rproc *rproc) 299 { 300 struct qcom_adsp *adsp = rproc->priv; 301 302 return qcom_q6v5_panic(&adsp->q6v5); 303 } 304 305 static const struct rproc_ops adsp_ops = { 306 .start = adsp_start, 307 .stop = adsp_stop, 308 .da_to_va = adsp_da_to_va, 309 .parse_fw = qcom_register_dump_segments, 310 .load = adsp_load, 311 .panic = adsp_panic, 312 }; 313 314 static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids) 315 { 316 int num_clks = 0; 317 int i, ret; 318 319 adsp->xo = devm_clk_get(adsp->dev, "xo"); 320 if (IS_ERR(adsp->xo)) { 321 ret = PTR_ERR(adsp->xo); 322 if (ret != -EPROBE_DEFER) 323 dev_err(adsp->dev, "failed to get xo clock"); 324 return ret; 325 } 326 327 for (i = 0; clk_ids[i]; i++) 328 num_clks++; 329 330 adsp->num_clks = num_clks; 331 adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks, 332 sizeof(*adsp->clks), GFP_KERNEL); 333 if (!adsp->clks) 334 return -ENOMEM; 335 336 for (i = 0; i < adsp->num_clks; i++) 337 adsp->clks[i].id = clk_ids[i]; 338 339 return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks); 340 } 341 342 static int adsp_init_reset(struct qcom_adsp *adsp) 343 { 344 adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev, 345 "pdc_sync"); 346 if (IS_ERR(adsp->pdc_sync_reset)) { 347 dev_err(adsp->dev, "failed to acquire pdc_sync reset\n"); 348 return PTR_ERR(adsp->pdc_sync_reset); 349 } 350 351 adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart"); 352 353 /* Fall back to the old "cc_lpass" if "restart" is absent */ 354 if (!adsp->restart) 355 adsp->restart = devm_reset_control_get_exclusive(adsp->dev, "cc_lpass"); 356 357 if (IS_ERR(adsp->restart)) { 358 dev_err(adsp->dev, "failed to acquire restart\n"); 359 return PTR_ERR(adsp->restart); 360 } 361 362 return 0; 363 } 364 365 static int adsp_init_mmio(struct qcom_adsp *adsp, 366 struct platform_device *pdev) 367 { 368 struct device_node *syscon; 369 int ret; 370 371 adsp->qdsp6ss_base = devm_platform_ioremap_resource(pdev, 0); 372 if (IS_ERR(adsp->qdsp6ss_base)) { 373 dev_err(adsp->dev, "failed to map QDSP6SS registers\n"); 374 return PTR_ERR(adsp->qdsp6ss_base); 375 } 376 377 syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0); 378 if (!syscon) { 379 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); 380 return -EINVAL; 381 } 382 383 adsp->halt_map = syscon_node_to_regmap(syscon); 384 of_node_put(syscon); 385 if (IS_ERR(adsp->halt_map)) 386 return PTR_ERR(adsp->halt_map); 387 388 ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs", 389 1, &adsp->halt_lpass); 390 if (ret < 0) { 391 dev_err(&pdev->dev, "no offset in syscon\n"); 392 return ret; 393 } 394 395 return 0; 396 } 397 398 static int adsp_alloc_memory_region(struct qcom_adsp *adsp) 399 { 400 struct device_node *node; 401 struct resource r; 402 int ret; 403 404 node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0); 405 if (!node) { 406 dev_err(adsp->dev, "no memory-region specified\n"); 407 return -EINVAL; 408 } 409 410 ret = of_address_to_resource(node, 0, &r); 411 if (ret) 412 return ret; 413 414 adsp->mem_phys = adsp->mem_reloc = r.start; 415 adsp->mem_size = resource_size(&r); 416 adsp->mem_region = devm_ioremap_wc(adsp->dev, 417 adsp->mem_phys, adsp->mem_size); 418 if (!adsp->mem_region) { 419 dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n", 420 &r.start, adsp->mem_size); 421 return -EBUSY; 422 } 423 424 return 0; 425 } 426 427 static int adsp_probe(struct platform_device *pdev) 428 { 429 const struct adsp_pil_data *desc; 430 struct qcom_adsp *adsp; 431 struct rproc *rproc; 432 int ret; 433 434 desc = of_device_get_match_data(&pdev->dev); 435 if (!desc) 436 return -EINVAL; 437 438 rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops, 439 desc->firmware_name, sizeof(*adsp)); 440 if (!rproc) { 441 dev_err(&pdev->dev, "unable to allocate remoteproc\n"); 442 return -ENOMEM; 443 } 444 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); 445 446 adsp = (struct qcom_adsp *)rproc->priv; 447 adsp->dev = &pdev->dev; 448 adsp->rproc = rproc; 449 adsp->info_name = desc->sysmon_name; 450 platform_set_drvdata(pdev, adsp); 451 452 ret = adsp_alloc_memory_region(adsp); 453 if (ret) 454 goto free_rproc; 455 456 ret = adsp_init_clock(adsp, desc->clk_ids); 457 if (ret) 458 goto free_rproc; 459 460 pm_runtime_enable(adsp->dev); 461 462 ret = adsp_init_reset(adsp); 463 if (ret) 464 goto disable_pm; 465 466 ret = adsp_init_mmio(adsp, pdev); 467 if (ret) 468 goto disable_pm; 469 470 ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, NULL, 471 qcom_adsp_pil_handover); 472 if (ret) 473 goto disable_pm; 474 475 qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name); 476 qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name); 477 adsp->sysmon = qcom_add_sysmon_subdev(rproc, 478 desc->sysmon_name, 479 desc->ssctl_id); 480 if (IS_ERR(adsp->sysmon)) { 481 ret = PTR_ERR(adsp->sysmon); 482 goto disable_pm; 483 } 484 485 ret = rproc_add(rproc); 486 if (ret) 487 goto disable_pm; 488 489 return 0; 490 491 disable_pm: 492 pm_runtime_disable(adsp->dev); 493 free_rproc: 494 rproc_free(rproc); 495 496 return ret; 497 } 498 499 static int adsp_remove(struct platform_device *pdev) 500 { 501 struct qcom_adsp *adsp = platform_get_drvdata(pdev); 502 503 rproc_del(adsp->rproc); 504 505 qcom_q6v5_deinit(&adsp->q6v5); 506 qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev); 507 qcom_remove_sysmon_subdev(adsp->sysmon); 508 qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev); 509 pm_runtime_disable(adsp->dev); 510 rproc_free(adsp->rproc); 511 512 return 0; 513 } 514 515 static const struct adsp_pil_data adsp_resource_init = { 516 .crash_reason_smem = 423, 517 .firmware_name = "adsp.mdt", 518 .ssr_name = "lpass", 519 .sysmon_name = "adsp", 520 .ssctl_id = 0x14, 521 .clk_ids = (const char*[]) { 522 "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr", 523 "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL 524 }, 525 .num_clks = 7, 526 }; 527 528 static const struct adsp_pil_data cdsp_resource_init = { 529 .crash_reason_smem = 601, 530 .firmware_name = "cdsp.mdt", 531 .ssr_name = "cdsp", 532 .sysmon_name = "cdsp", 533 .ssctl_id = 0x17, 534 .clk_ids = (const char*[]) { 535 "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master", 536 "q6_axim", NULL 537 }, 538 .num_clks = 7, 539 }; 540 541 static const struct of_device_id adsp_of_match[] = { 542 { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init }, 543 { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init }, 544 { }, 545 }; 546 MODULE_DEVICE_TABLE(of, adsp_of_match); 547 548 static struct platform_driver adsp_pil_driver = { 549 .probe = adsp_probe, 550 .remove = adsp_remove, 551 .driver = { 552 .name = "qcom_q6v5_adsp", 553 .of_match_table = adsp_of_match, 554 }, 555 }; 556 557 module_platform_driver(adsp_pil_driver); 558 MODULE_DESCRIPTION("QTI SDM845 ADSP Peripheral Image Loader"); 559 MODULE_LICENSE("GPL v2"); 560