1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm Technology Inc. ADSP Peripheral Image Loader for SDM845. 4 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/firmware.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iommu.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_reserved_mem.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_domain.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regmap.h> 23 #include <linux/remoteproc.h> 24 #include <linux/reset.h> 25 #include <linux/soc/qcom/mdt_loader.h> 26 #include <linux/soc/qcom/smem.h> 27 #include <linux/soc/qcom/smem_state.h> 28 29 #include "qcom_common.h" 30 #include "qcom_pil_info.h" 31 #include "qcom_q6v5.h" 32 #include "remoteproc_internal.h" 33 34 /* time out value */ 35 #define ACK_TIMEOUT 1000 36 #define ACK_TIMEOUT_US 1000000 37 #define BOOT_FSM_TIMEOUT 10000 38 /* mask values */ 39 #define EVB_MASK GENMASK(27, 4) 40 /*QDSP6SS register offsets*/ 41 #define RST_EVB_REG 0x10 42 #define CORE_START_REG 0x400 43 #define BOOT_CMD_REG 0x404 44 #define BOOT_STATUS_REG 0x408 45 #define RET_CFG_REG 0x1C 46 /*TCSR register offsets*/ 47 #define LPASS_MASTER_IDLE_REG 0x8 48 #define LPASS_HALTACK_REG 0x4 49 #define LPASS_PWR_ON_REG 0x10 50 #define LPASS_HALTREQ_REG 0x0 51 52 #define SID_MASK_DEFAULT 0xF 53 54 #define QDSP6SS_XO_CBCR 0x38 55 #define QDSP6SS_CORE_CBCR 0x20 56 #define QDSP6SS_SLEEP_CBCR 0x3c 57 58 #define LPASS_BOOT_CORE_START BIT(0) 59 #define LPASS_BOOT_CMD_START BIT(0) 60 #define LPASS_EFUSE_Q6SS_EVB_SEL 0x0 61 62 struct adsp_pil_data { 63 int crash_reason_smem; 64 const char *firmware_name; 65 66 const char *ssr_name; 67 const char *sysmon_name; 68 int ssctl_id; 69 bool is_wpss; 70 bool has_iommu; 71 bool auto_boot; 72 73 const char **clk_ids; 74 int num_clks; 75 const char **pd_names; 76 unsigned int num_pds; 77 const char *load_state; 78 }; 79 80 struct qcom_adsp { 81 struct device *dev; 82 struct rproc *rproc; 83 84 struct qcom_q6v5 q6v5; 85 86 struct clk *xo; 87 88 int num_clks; 89 struct clk_bulk_data *clks; 90 91 void __iomem *qdsp6ss_base; 92 void __iomem *lpass_efuse; 93 94 struct reset_control *pdc_sync_reset; 95 struct reset_control *restart; 96 97 struct regmap *halt_map; 98 unsigned int halt_lpass; 99 100 int crash_reason_smem; 101 const char *info_name; 102 103 struct completion start_done; 104 struct completion stop_done; 105 106 phys_addr_t mem_phys; 107 phys_addr_t mem_reloc; 108 void __iomem *mem_region; 109 size_t mem_size; 110 bool has_iommu; 111 112 struct dev_pm_domain_list *pd_list; 113 114 struct qcom_rproc_glink glink_subdev; 115 struct qcom_rproc_pdm pdm_subdev; 116 struct qcom_rproc_ssr ssr_subdev; 117 struct qcom_sysmon *sysmon; 118 119 int (*shutdown)(struct qcom_adsp *adsp); 120 }; 121 122 static int qcom_rproc_pds_attach(struct qcom_adsp *adsp, const char **pd_names, 123 unsigned int num_pds) 124 { 125 struct device *dev = adsp->dev; 126 struct dev_pm_domain_attach_data pd_data = { 127 .pd_names = pd_names, 128 .num_pd_names = num_pds, 129 }; 130 int ret; 131 132 /* Handle single power domain */ 133 if (dev->pm_domain) 134 goto out; 135 136 if (!pd_names) 137 return 0; 138 139 ret = dev_pm_domain_attach_list(dev, &pd_data, &adsp->pd_list); 140 if (ret < 0) 141 return ret; 142 143 out: 144 pm_runtime_enable(dev); 145 return 0; 146 } 147 148 static void qcom_rproc_pds_detach(struct qcom_adsp *adsp) 149 { 150 struct device *dev = adsp->dev; 151 struct dev_pm_domain_list *pds = adsp->pd_list; 152 153 dev_pm_domain_detach_list(pds); 154 155 if (dev->pm_domain || pds) 156 pm_runtime_disable(adsp->dev); 157 } 158 159 static int qcom_rproc_pds_enable(struct qcom_adsp *adsp) 160 { 161 struct device *dev = adsp->dev; 162 struct dev_pm_domain_list *pds = adsp->pd_list; 163 int ret, i = 0; 164 165 if (!dev->pm_domain && !pds) 166 return 0; 167 168 if (dev->pm_domain) 169 dev_pm_genpd_set_performance_state(dev, INT_MAX); 170 171 while (pds && i < pds->num_pds) { 172 dev_pm_genpd_set_performance_state(pds->pd_devs[i], INT_MAX); 173 i++; 174 } 175 176 ret = pm_runtime_resume_and_get(dev); 177 if (ret < 0) { 178 while (pds && i > 0) { 179 i--; 180 dev_pm_genpd_set_performance_state(pds->pd_devs[i], 0); 181 } 182 183 if (dev->pm_domain) 184 dev_pm_genpd_set_performance_state(dev, 0); 185 } 186 187 return ret; 188 } 189 190 static void qcom_rproc_pds_disable(struct qcom_adsp *adsp) 191 { 192 struct device *dev = adsp->dev; 193 struct dev_pm_domain_list *pds = adsp->pd_list; 194 int i = 0; 195 196 if (!dev->pm_domain && !pds) 197 return; 198 199 if (dev->pm_domain) 200 dev_pm_genpd_set_performance_state(dev, 0); 201 202 while (pds && i < pds->num_pds) { 203 dev_pm_genpd_set_performance_state(pds->pd_devs[i], 0); 204 i++; 205 } 206 207 pm_runtime_put(dev); 208 } 209 210 static int qcom_wpss_shutdown(struct qcom_adsp *adsp) 211 { 212 unsigned int val; 213 214 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 1); 215 216 /* Wait for halt ACK from QDSP6 */ 217 regmap_read_poll_timeout(adsp->halt_map, 218 adsp->halt_lpass + LPASS_HALTACK_REG, val, 219 val, 1000, ACK_TIMEOUT_US); 220 221 /* Assert the WPSS PDC Reset */ 222 reset_control_assert(adsp->pdc_sync_reset); 223 224 /* Place the WPSS processor into reset */ 225 reset_control_assert(adsp->restart); 226 227 /* wait after asserting subsystem restart from AOSS */ 228 usleep_range(200, 205); 229 230 /* Remove the WPSS reset */ 231 reset_control_deassert(adsp->restart); 232 233 /* De-assert the WPSS PDC Reset */ 234 reset_control_deassert(adsp->pdc_sync_reset); 235 236 usleep_range(100, 105); 237 238 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks); 239 240 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0); 241 242 /* Wait for halt ACK from QDSP6 */ 243 regmap_read_poll_timeout(adsp->halt_map, 244 adsp->halt_lpass + LPASS_HALTACK_REG, val, 245 !val, 1000, ACK_TIMEOUT_US); 246 247 return 0; 248 } 249 250 static int qcom_adsp_shutdown(struct qcom_adsp *adsp) 251 { 252 unsigned long timeout; 253 unsigned int val; 254 int ret; 255 256 /* Reset the retention logic */ 257 val = readl(adsp->qdsp6ss_base + RET_CFG_REG); 258 val |= 0x1; 259 writel(val, adsp->qdsp6ss_base + RET_CFG_REG); 260 261 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks); 262 263 /* QDSP6 master port needs to be explicitly halted */ 264 ret = regmap_read(adsp->halt_map, 265 adsp->halt_lpass + LPASS_PWR_ON_REG, &val); 266 if (ret || !val) 267 goto reset; 268 269 ret = regmap_read(adsp->halt_map, 270 adsp->halt_lpass + LPASS_MASTER_IDLE_REG, 271 &val); 272 if (ret || val) 273 goto reset; 274 275 regmap_write(adsp->halt_map, 276 adsp->halt_lpass + LPASS_HALTREQ_REG, 1); 277 278 /* Wait for halt ACK from QDSP6 */ 279 timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT); 280 for (;;) { 281 ret = regmap_read(adsp->halt_map, 282 adsp->halt_lpass + LPASS_HALTACK_REG, &val); 283 if (ret || val || time_after(jiffies, timeout)) 284 break; 285 286 usleep_range(1000, 1100); 287 } 288 289 ret = regmap_read(adsp->halt_map, 290 adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val); 291 if (ret || !val) 292 dev_err(adsp->dev, "port failed halt\n"); 293 294 reset: 295 /* Assert the LPASS PDC Reset */ 296 reset_control_assert(adsp->pdc_sync_reset); 297 /* Place the LPASS processor into reset */ 298 reset_control_assert(adsp->restart); 299 /* wait after asserting subsystem restart from AOSS */ 300 usleep_range(200, 300); 301 302 /* Clear the halt request for the AXIM and AHBM for Q6 */ 303 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0); 304 305 /* De-assert the LPASS PDC Reset */ 306 reset_control_deassert(adsp->pdc_sync_reset); 307 /* Remove the LPASS reset */ 308 reset_control_deassert(adsp->restart); 309 /* wait after de-asserting subsystem restart from AOSS */ 310 usleep_range(200, 300); 311 312 return 0; 313 } 314 315 static int adsp_load(struct rproc *rproc, const struct firmware *fw) 316 { 317 struct qcom_adsp *adsp = rproc->priv; 318 int ret; 319 320 ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 321 (__force void *)adsp->mem_region, adsp->mem_phys, 322 adsp->mem_size, &adsp->mem_reloc); 323 if (ret) 324 return ret; 325 326 qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size); 327 328 return 0; 329 } 330 331 static void adsp_unmap_carveout(struct rproc *rproc) 332 { 333 struct qcom_adsp *adsp = rproc->priv; 334 335 if (adsp->has_iommu) 336 iommu_unmap(rproc->domain, adsp->mem_phys, adsp->mem_size); 337 } 338 339 static int adsp_map_carveout(struct rproc *rproc) 340 { 341 struct qcom_adsp *adsp = rproc->priv; 342 struct of_phandle_args args; 343 long long sid; 344 unsigned long iova; 345 int ret; 346 347 if (!adsp->has_iommu) 348 return 0; 349 350 if (!rproc->domain) 351 return -EINVAL; 352 353 ret = of_parse_phandle_with_args(adsp->dev->of_node, "iommus", "#iommu-cells", 0, &args); 354 if (ret < 0) 355 return ret; 356 357 sid = args.args[0] & SID_MASK_DEFAULT; 358 of_node_put(args.np); 359 360 /* Add SID configuration for ADSP Firmware to SMMU */ 361 iova = adsp->mem_phys | (sid << 32); 362 363 ret = iommu_map(rproc->domain, iova, adsp->mem_phys, 364 adsp->mem_size, IOMMU_READ | IOMMU_WRITE, 365 GFP_KERNEL); 366 if (ret) { 367 dev_err(adsp->dev, "Unable to map ADSP Physical Memory\n"); 368 return ret; 369 } 370 371 return 0; 372 } 373 374 static int adsp_start(struct rproc *rproc) 375 { 376 struct qcom_adsp *adsp = rproc->priv; 377 int ret; 378 unsigned int val; 379 380 ret = qcom_q6v5_prepare(&adsp->q6v5); 381 if (ret) 382 return ret; 383 384 ret = adsp_map_carveout(rproc); 385 if (ret) { 386 dev_err(adsp->dev, "ADSP smmu mapping failed\n"); 387 goto disable_irqs; 388 } 389 390 ret = clk_prepare_enable(adsp->xo); 391 if (ret) 392 goto adsp_smmu_unmap; 393 394 ret = qcom_rproc_pds_enable(adsp); 395 if (ret < 0) 396 goto disable_xo_clk; 397 398 ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks); 399 if (ret) { 400 dev_err(adsp->dev, "adsp clk_enable failed\n"); 401 goto disable_power_domain; 402 } 403 404 /* Enable the XO clock */ 405 writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR); 406 407 /* Enable the QDSP6SS sleep clock */ 408 writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR); 409 410 /* Enable the QDSP6 core clock */ 411 writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR); 412 413 /* Program boot address */ 414 writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG); 415 416 if (adsp->lpass_efuse) 417 writel(LPASS_EFUSE_Q6SS_EVB_SEL, adsp->lpass_efuse); 418 419 /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */ 420 writel(LPASS_BOOT_CORE_START, adsp->qdsp6ss_base + CORE_START_REG); 421 422 /* Trigger boot FSM to start QDSP6 */ 423 writel(LPASS_BOOT_CMD_START, adsp->qdsp6ss_base + BOOT_CMD_REG); 424 425 /* Wait for core to come out of reset */ 426 ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG, 427 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); 428 if (ret) { 429 dev_err(adsp->dev, "failed to bootup adsp\n"); 430 goto disable_adsp_clks; 431 } 432 433 ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5 * HZ)); 434 if (ret == -ETIMEDOUT) { 435 dev_err(adsp->dev, "start timed out\n"); 436 goto disable_adsp_clks; 437 } 438 439 return 0; 440 441 disable_adsp_clks: 442 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks); 443 disable_power_domain: 444 qcom_rproc_pds_disable(adsp); 445 disable_xo_clk: 446 clk_disable_unprepare(adsp->xo); 447 adsp_smmu_unmap: 448 adsp_unmap_carveout(rproc); 449 disable_irqs: 450 qcom_q6v5_unprepare(&adsp->q6v5); 451 452 return ret; 453 } 454 455 static void qcom_adsp_pil_handover(struct qcom_q6v5 *q6v5) 456 { 457 struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5); 458 459 clk_disable_unprepare(adsp->xo); 460 qcom_rproc_pds_disable(adsp); 461 } 462 463 static int adsp_stop(struct rproc *rproc) 464 { 465 struct qcom_adsp *adsp = rproc->priv; 466 int handover; 467 int ret; 468 469 ret = qcom_q6v5_request_stop(&adsp->q6v5, adsp->sysmon); 470 if (ret == -ETIMEDOUT) 471 dev_err(adsp->dev, "timed out on wait\n"); 472 473 ret = adsp->shutdown(adsp); 474 if (ret) 475 dev_err(adsp->dev, "failed to shutdown: %d\n", ret); 476 477 adsp_unmap_carveout(rproc); 478 479 handover = qcom_q6v5_unprepare(&adsp->q6v5); 480 if (handover) 481 qcom_adsp_pil_handover(&adsp->q6v5); 482 483 return ret; 484 } 485 486 static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem) 487 { 488 struct qcom_adsp *adsp = rproc->priv; 489 int offset; 490 491 offset = da - adsp->mem_reloc; 492 if (offset < 0 || offset + len > adsp->mem_size) 493 return NULL; 494 495 return (__force void *)adsp->mem_region + offset; 496 } 497 498 static int adsp_parse_firmware(struct rproc *rproc, const struct firmware *fw) 499 { 500 struct qcom_adsp *adsp = rproc->priv; 501 int ret; 502 503 ret = qcom_register_dump_segments(rproc, fw); 504 if (ret) { 505 dev_err(&rproc->dev, "Error in registering dump segments\n"); 506 return ret; 507 } 508 509 if (adsp->has_iommu) { 510 ret = rproc_elf_load_rsc_table(rproc, fw); 511 if (ret) { 512 dev_err(&rproc->dev, "Error in loading resource table\n"); 513 return ret; 514 } 515 } 516 return 0; 517 } 518 519 static unsigned long adsp_panic(struct rproc *rproc) 520 { 521 struct qcom_adsp *adsp = rproc->priv; 522 523 return qcom_q6v5_panic(&adsp->q6v5); 524 } 525 526 static const struct rproc_ops adsp_ops = { 527 .start = adsp_start, 528 .stop = adsp_stop, 529 .da_to_va = adsp_da_to_va, 530 .parse_fw = adsp_parse_firmware, 531 .load = adsp_load, 532 .panic = adsp_panic, 533 }; 534 535 static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids) 536 { 537 int num_clks = 0; 538 int i; 539 540 adsp->xo = devm_clk_get(adsp->dev, "xo"); 541 if (IS_ERR(adsp->xo)) 542 return dev_err_probe(adsp->dev, PTR_ERR(adsp->xo), "failed to get xo clock"); 543 544 for (i = 0; clk_ids[i]; i++) 545 num_clks++; 546 547 adsp->num_clks = num_clks; 548 adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks, 549 sizeof(*adsp->clks), GFP_KERNEL); 550 if (!adsp->clks) 551 return -ENOMEM; 552 553 for (i = 0; i < adsp->num_clks; i++) 554 adsp->clks[i].id = clk_ids[i]; 555 556 return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks); 557 } 558 559 static int adsp_init_reset(struct qcom_adsp *adsp) 560 { 561 adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev, 562 "pdc_sync"); 563 if (IS_ERR(adsp->pdc_sync_reset)) { 564 dev_err(adsp->dev, "failed to acquire pdc_sync reset\n"); 565 return PTR_ERR(adsp->pdc_sync_reset); 566 } 567 568 adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart"); 569 570 /* Fall back to the old "cc_lpass" if "restart" is absent */ 571 if (!adsp->restart) 572 adsp->restart = devm_reset_control_get_exclusive(adsp->dev, "cc_lpass"); 573 574 if (IS_ERR(adsp->restart)) { 575 dev_err(adsp->dev, "failed to acquire restart\n"); 576 return PTR_ERR(adsp->restart); 577 } 578 579 return 0; 580 } 581 582 static int adsp_init_mmio(struct qcom_adsp *adsp, 583 struct platform_device *pdev) 584 { 585 struct resource *efuse_region; 586 struct device_node *syscon; 587 int ret; 588 589 adsp->qdsp6ss_base = devm_platform_ioremap_resource(pdev, 0); 590 if (IS_ERR(adsp->qdsp6ss_base)) { 591 dev_err(adsp->dev, "failed to map QDSP6SS registers\n"); 592 return PTR_ERR(adsp->qdsp6ss_base); 593 } 594 595 efuse_region = platform_get_resource(pdev, IORESOURCE_MEM, 1); 596 if (!efuse_region) { 597 adsp->lpass_efuse = NULL; 598 dev_dbg(adsp->dev, "failed to get efuse memory region\n"); 599 } else { 600 adsp->lpass_efuse = devm_ioremap_resource(&pdev->dev, efuse_region); 601 if (IS_ERR(adsp->lpass_efuse)) { 602 dev_err(adsp->dev, "failed to map efuse registers\n"); 603 return PTR_ERR(adsp->lpass_efuse); 604 } 605 } 606 syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0); 607 if (!syscon) { 608 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); 609 return -EINVAL; 610 } 611 612 adsp->halt_map = syscon_node_to_regmap(syscon); 613 of_node_put(syscon); 614 if (IS_ERR(adsp->halt_map)) 615 return PTR_ERR(adsp->halt_map); 616 617 ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs", 618 1, &adsp->halt_lpass); 619 if (ret < 0) { 620 dev_err(&pdev->dev, "no offset in syscon\n"); 621 return ret; 622 } 623 624 return 0; 625 } 626 627 static int adsp_alloc_memory_region(struct qcom_adsp *adsp) 628 { 629 int ret; 630 struct resource res; 631 632 ret = of_reserved_mem_region_to_resource(adsp->dev->of_node, 0, &res); 633 if (ret) { 634 dev_err(adsp->dev, "unable to resolve memory-region\n"); 635 return ret; 636 } 637 638 adsp->mem_phys = adsp->mem_reloc = res.start; 639 adsp->mem_size = resource_size(&res); 640 adsp->mem_region = devm_ioremap_resource_wc(adsp->dev, &res); 641 if (IS_ERR(adsp->mem_region)) { 642 dev_err(adsp->dev, "unable to map memory region: %pR\n", &res); 643 return PTR_ERR(adsp->mem_region); 644 645 } 646 647 return 0; 648 } 649 650 static int adsp_probe(struct platform_device *pdev) 651 { 652 const struct adsp_pil_data *desc; 653 const char *firmware_name; 654 struct qcom_adsp *adsp; 655 struct rproc *rproc; 656 int ret; 657 658 desc = of_device_get_match_data(&pdev->dev); 659 if (!desc) 660 return -EINVAL; 661 662 firmware_name = desc->firmware_name; 663 ret = of_property_read_string(pdev->dev.of_node, "firmware-name", 664 &firmware_name); 665 if (ret < 0 && ret != -EINVAL) { 666 dev_err(&pdev->dev, "unable to read firmware-name\n"); 667 return ret; 668 } 669 670 rproc = devm_rproc_alloc(&pdev->dev, pdev->name, &adsp_ops, 671 firmware_name, sizeof(*adsp)); 672 if (!rproc) { 673 dev_err(&pdev->dev, "unable to allocate remoteproc\n"); 674 return -ENOMEM; 675 } 676 677 rproc->auto_boot = desc->auto_boot; 678 rproc->has_iommu = desc->has_iommu; 679 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); 680 681 adsp = rproc->priv; 682 adsp->dev = &pdev->dev; 683 adsp->rproc = rproc; 684 adsp->info_name = desc->sysmon_name; 685 adsp->has_iommu = desc->has_iommu; 686 687 platform_set_drvdata(pdev, adsp); 688 689 if (desc->is_wpss) 690 adsp->shutdown = qcom_wpss_shutdown; 691 else 692 adsp->shutdown = qcom_adsp_shutdown; 693 694 ret = adsp_alloc_memory_region(adsp); 695 if (ret) 696 return ret; 697 698 ret = adsp_init_clock(adsp, desc->clk_ids); 699 if (ret) 700 return ret; 701 702 ret = qcom_rproc_pds_attach(adsp, desc->pd_names, desc->num_pds); 703 if (ret < 0) 704 return dev_err_probe(&pdev->dev, ret, 705 "Failed to attach proxy power domains\n"); 706 707 ret = adsp_init_reset(adsp); 708 if (ret) 709 goto disable_pm; 710 711 ret = adsp_init_mmio(adsp, pdev); 712 if (ret) 713 goto disable_pm; 714 715 ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, 716 desc->load_state, qcom_adsp_pil_handover); 717 if (ret) 718 goto disable_pm; 719 720 qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name); 721 qcom_add_pdm_subdev(rproc, &adsp->pdm_subdev); 722 qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name); 723 adsp->sysmon = qcom_add_sysmon_subdev(rproc, 724 desc->sysmon_name, 725 desc->ssctl_id); 726 if (IS_ERR(adsp->sysmon)) { 727 ret = PTR_ERR(adsp->sysmon); 728 goto deinit_remove_glink_pdm_ssr; 729 } 730 731 ret = rproc_add(rproc); 732 if (ret) 733 goto remove_sysmon; 734 735 return 0; 736 737 remove_sysmon: 738 qcom_remove_sysmon_subdev(adsp->sysmon); 739 deinit_remove_glink_pdm_ssr: 740 qcom_q6v5_deinit(&adsp->q6v5); 741 qcom_remove_glink_subdev(rproc, &adsp->glink_subdev); 742 qcom_remove_pdm_subdev(rproc, &adsp->pdm_subdev); 743 qcom_remove_ssr_subdev(rproc, &adsp->ssr_subdev); 744 disable_pm: 745 qcom_rproc_pds_detach(adsp); 746 747 return ret; 748 } 749 750 static void adsp_remove(struct platform_device *pdev) 751 { 752 struct qcom_adsp *adsp = platform_get_drvdata(pdev); 753 754 rproc_del(adsp->rproc); 755 756 qcom_q6v5_deinit(&adsp->q6v5); 757 qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev); 758 qcom_remove_pdm_subdev(adsp->rproc, &adsp->pdm_subdev); 759 qcom_remove_sysmon_subdev(adsp->sysmon); 760 qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev); 761 qcom_rproc_pds_detach(adsp); 762 } 763 764 static const struct adsp_pil_data adsp_resource_init = { 765 .crash_reason_smem = 423, 766 .firmware_name = "adsp.mdt", 767 .ssr_name = "lpass", 768 .sysmon_name = "adsp", 769 .ssctl_id = 0x14, 770 .is_wpss = false, 771 .auto_boot = true, 772 .clk_ids = (const char*[]) { 773 "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr", 774 "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL 775 }, 776 .num_clks = 7, 777 .pd_names = (const char*[]) { "cx" }, 778 .num_pds = 1, 779 }; 780 781 static const struct adsp_pil_data adsp_sc7280_resource_init = { 782 .crash_reason_smem = 423, 783 .firmware_name = "adsp.pbn", 784 .load_state = "adsp", 785 .ssr_name = "lpass", 786 .sysmon_name = "adsp", 787 .ssctl_id = 0x14, 788 .has_iommu = true, 789 .auto_boot = true, 790 .clk_ids = (const char*[]) { 791 "gcc_cfg_noc_lpass", NULL 792 }, 793 .num_clks = 1, 794 }; 795 796 static const struct adsp_pil_data cdsp_resource_init = { 797 .crash_reason_smem = 601, 798 .firmware_name = "cdsp.mdt", 799 .ssr_name = "cdsp", 800 .sysmon_name = "cdsp", 801 .ssctl_id = 0x17, 802 .is_wpss = false, 803 .auto_boot = true, 804 .clk_ids = (const char*[]) { 805 "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master", 806 "q6_axim", NULL 807 }, 808 .num_clks = 7, 809 .pd_names = (const char*[]) { "cx" }, 810 .num_pds = 1, 811 }; 812 813 static const struct adsp_pil_data wpss_resource_init = { 814 .crash_reason_smem = 626, 815 .firmware_name = "wpss.mdt", 816 .ssr_name = "wpss", 817 .sysmon_name = "wpss", 818 .ssctl_id = 0x19, 819 .is_wpss = true, 820 .auto_boot = false, 821 .load_state = "wpss", 822 .clk_ids = (const char*[]) { 823 "ahb_bdg", "ahb", "rscp", NULL 824 }, 825 .num_clks = 3, 826 .pd_names = (const char*[]) { "cx", "mx" }, 827 .num_pds = 2, 828 }; 829 830 static const struct of_device_id adsp_of_match[] = { 831 { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init }, 832 { .compatible = "qcom,sc7280-adsp-pil", .data = &adsp_sc7280_resource_init }, 833 { .compatible = "qcom,sc7280-wpss-pil", .data = &wpss_resource_init }, 834 { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init }, 835 { }, 836 }; 837 MODULE_DEVICE_TABLE(of, adsp_of_match); 838 839 static struct platform_driver adsp_pil_driver = { 840 .probe = adsp_probe, 841 .remove = adsp_remove, 842 .driver = { 843 .name = "qcom_q6v5_adsp", 844 .of_match_table = adsp_of_match, 845 }, 846 }; 847 848 module_platform_driver(adsp_pil_driver); 849 MODULE_DESCRIPTION("QTI SDM845 ADSP Peripheral Image Loader"); 850 MODULE_LICENSE("GPL v2"); 851