1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2019 MediaTek Inc. 4 */ 5 6 #ifndef __RPROC_MTK_COMMON_H 7 #define __RPROC_MTK_COMMON_H 8 9 #include <linux/interrupt.h> 10 #include <linux/kernel.h> 11 #include <linux/platform_device.h> 12 #include <linux/remoteproc.h> 13 #include <linux/remoteproc/mtk_scp.h> 14 15 #define MT8183_SW_RSTN 0x0 16 #define MT8183_SW_RSTN_BIT BIT(0) 17 #define MT8183_SCP_TO_HOST 0x1C 18 #define MT8183_SCP_IPC_INT_BIT BIT(0) 19 #define MT8183_SCP_WDT_INT_BIT BIT(8) 20 #define MT8183_HOST_TO_SCP 0x28 21 #define MT8183_HOST_IPC_INT_BIT BIT(0) 22 #define MT8183_WDT_CFG 0x84 23 #define MT8183_SCP_CLK_SW_SEL 0x4000 24 #define MT8183_SCP_CLK_DIV_SEL 0x4024 25 #define MT8183_SCP_SRAM_PDN 0x402C 26 #define MT8183_SCP_L1_SRAM_PD 0x4080 27 #define MT8183_SCP_TCM_TAIL_SRAM_PD 0x4094 28 29 #define MT8183_SCP_CACHE_SEL(x) (0x14000 + (x) * 0x3000) 30 #define MT8183_SCP_CACHE_CON MT8183_SCP_CACHE_SEL(0) 31 #define MT8183_SCP_DCACHE_CON MT8183_SCP_CACHE_SEL(1) 32 #define MT8183_SCP_CACHESIZE_8KB BIT(8) 33 #define MT8183_SCP_CACHE_CON_WAYEN BIT(10) 34 35 #define MT8186_SCP_L1_SRAM_PD_P1 0x40B0 36 #define MT8186_SCP_L1_SRAM_PD_p2 0x40B4 37 38 #define MT8192_L2TCM_SRAM_PD_0 0x10C0 39 #define MT8192_L2TCM_SRAM_PD_1 0x10C4 40 #define MT8192_L2TCM_SRAM_PD_2 0x10C8 41 #define MT8192_L1TCM_SRAM_PDN 0x102C 42 #define MT8192_CPU0_SRAM_PD 0x1080 43 44 #define MT8192_SCP2APMCU_IPC_SET 0x4080 45 #define MT8192_SCP2APMCU_IPC_CLR 0x4084 46 #define MT8192_SCP_IPC_INT_BIT BIT(0) 47 #define MT8192_SCP2SPM_IPC_CLR 0x4094 48 #define MT8192_GIPC_IN_SET 0x4098 49 #define MT8192_HOST_IPC_INT_BIT BIT(0) 50 #define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4) 51 52 #define MT8192_CORE0_SW_RSTN_CLR 0x10000 53 #define MT8192_CORE0_SW_RSTN_SET 0x10004 54 #define MT8192_CORE0_MEM_ATT_PREDEF 0x10008 55 #define MT8192_CORE0_WDT_IRQ 0x10030 56 #define MT8192_CORE0_WDT_CFG 0x10034 57 58 #define MT8195_SYS_STATUS 0x4004 59 #define MT8195_CORE0_WDT BIT(16) 60 #define MT8195_CORE1_WDT BIT(17) 61 62 #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) 63 64 #define MT8195_CPU1_SRAM_PD 0x1084 65 #define MT8195_SSHUB2APMCU_IPC_SET 0x4088 66 #define MT8195_SSHUB2APMCU_IPC_CLR 0x408C 67 #define MT8195_CORE1_SW_RSTN_CLR 0x20000 68 #define MT8195_CORE1_SW_RSTN_SET 0x20004 69 #define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 70 #define MT8195_CORE1_WDT_IRQ 0x20030 71 #define MT8195_CORE1_WDT_CFG 0x20034 72 73 #define MT8195_SEC_CTRL 0x85000 74 #define MT8195_CORE_OFFSET_ENABLE_D BIT(13) 75 #define MT8195_CORE_OFFSET_ENABLE_I BIT(12) 76 #define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0 77 #define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4 78 #define MT8195_L2TCM_OFFSET 0x850d0 79 80 #define SCP_FW_VER_LEN 32 81 82 struct scp_run { 83 u32 signaled; 84 s8 fw_ver[SCP_FW_VER_LEN]; 85 u32 dec_capability; 86 u32 enc_capability; 87 wait_queue_head_t wq; 88 }; 89 90 struct scp_ipi_desc { 91 /* For protecting handler. */ 92 struct mutex lock; 93 scp_ipi_handler_t handler; 94 void *priv; 95 }; 96 97 struct mtk_scp; 98 99 struct mtk_scp_sizes_data { 100 size_t max_dram_size; 101 size_t ipi_share_buffer_size; 102 }; 103 104 struct mtk_scp_of_data { 105 int (*scp_clk_get)(struct mtk_scp *scp); 106 int (*scp_before_load)(struct mtk_scp *scp); 107 void (*scp_irq_handler)(struct mtk_scp *scp); 108 void (*scp_reset_assert)(struct mtk_scp *scp); 109 void (*scp_reset_deassert)(struct mtk_scp *scp); 110 void (*scp_stop)(struct mtk_scp *scp); 111 void *(*scp_da_to_va)(struct mtk_scp *scp, u64 da, size_t len); 112 113 u32 host_to_scp_reg; 114 u32 host_to_scp_int_bit; 115 116 size_t ipi_buf_offset; 117 const struct mtk_scp_sizes_data *scp_sizes; 118 }; 119 120 struct mtk_scp_of_cluster { 121 void __iomem *reg_base; 122 void __iomem *l1tcm_base; 123 size_t l1tcm_size; 124 phys_addr_t l1tcm_phys; 125 struct list_head mtk_scp_list; 126 /* Prevent concurrent operations of this structure and L2TCM power control. */ 127 struct mutex cluster_lock; 128 u32 l2tcm_refcnt; 129 }; 130 131 struct mtk_scp { 132 struct device *dev; 133 struct rproc *rproc; 134 struct clk *clk; 135 void __iomem *sram_base; 136 size_t sram_size; 137 phys_addr_t sram_phys; 138 139 const struct mtk_scp_of_data *data; 140 141 struct mtk_share_obj __iomem *recv_buf; 142 struct mtk_share_obj __iomem *send_buf; 143 struct scp_run run; 144 /* To prevent multiple ipi_send run concurrently. */ 145 struct mutex send_lock; 146 struct scp_ipi_desc ipi_desc[SCP_IPI_MAX]; 147 bool ipi_id_ack[SCP_IPI_MAX]; 148 wait_queue_head_t ack_wq; 149 u8 *share_buf; 150 151 void *cpu_addr; 152 dma_addr_t dma_addr; 153 154 struct rproc_subdev *rpmsg_subdev; 155 156 struct list_head elem; 157 struct mtk_scp_of_cluster *cluster; 158 }; 159 160 /** 161 * struct mtk_share_obj - SRAM buffer shared with AP and SCP 162 * 163 * @id: IPI id 164 * @len: share buffer length 165 * @share_buf: share buffer data 166 */ 167 struct mtk_share_obj { 168 u32 id; 169 u32 len; 170 u8 *share_buf; 171 }; 172 173 void scp_memcpy_aligned(void __iomem *dst, const void *src, unsigned int len); 174 void scp_ipi_lock(struct mtk_scp *scp, u32 id); 175 void scp_ipi_unlock(struct mtk_scp *scp, u32 id); 176 177 #endif 178