1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> 4 */ 5 6 #include <dt-bindings/firmware/imx/rsrc.h> 7 #include <linux/arm-smccc.h> 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/firmware/imx/sci.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/mailbox_client.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_reserved_mem.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_domain.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/reboot.h> 23 #include <linux/regmap.h> 24 #include <linux/remoteproc.h> 25 #include <linux/workqueue.h> 26 27 #include "imx_rproc.h" 28 #include "remoteproc_internal.h" 29 30 #define IMX7D_SRC_SCR 0x0C 31 #define IMX7D_ENABLE_M4 BIT(3) 32 #define IMX7D_SW_M4P_RST BIT(2) 33 #define IMX7D_SW_M4C_RST BIT(1) 34 #define IMX7D_SW_M4C_NON_SCLR_RST BIT(0) 35 36 #define IMX7D_M4_RST_MASK (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \ 37 | IMX7D_SW_M4C_RST \ 38 | IMX7D_SW_M4C_NON_SCLR_RST) 39 40 #define IMX7D_M4_START (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \ 41 | IMX7D_SW_M4C_RST) 42 #define IMX7D_M4_STOP (IMX7D_ENABLE_M4 | IMX7D_SW_M4C_RST | \ 43 IMX7D_SW_M4C_NON_SCLR_RST) 44 45 #define IMX8M_M7_STOP (IMX7D_ENABLE_M4 | IMX7D_SW_M4C_RST) 46 #define IMX8M_M7_POLL IMX7D_ENABLE_M4 47 48 #define IMX8M_GPR22 0x58 49 #define IMX8M_GPR22_CM7_CPUWAIT BIT(0) 50 51 /* Address: 0x020D8000 */ 52 #define IMX6SX_SRC_SCR 0x00 53 #define IMX6SX_ENABLE_M4 BIT(22) 54 #define IMX6SX_SW_M4P_RST BIT(12) 55 #define IMX6SX_SW_M4C_NON_SCLR_RST BIT(4) 56 #define IMX6SX_SW_M4C_RST BIT(3) 57 58 #define IMX6SX_M4_START (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \ 59 | IMX6SX_SW_M4C_RST) 60 #define IMX6SX_M4_STOP (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4C_RST | \ 61 IMX6SX_SW_M4C_NON_SCLR_RST) 62 #define IMX6SX_M4_RST_MASK (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \ 63 | IMX6SX_SW_M4C_NON_SCLR_RST \ 64 | IMX6SX_SW_M4C_RST) 65 66 #define IMX_RPROC_MEM_MAX 32 67 68 #define IMX_SIP_RPROC 0xC2000005 69 #define IMX_SIP_RPROC_START 0x00 70 #define IMX_SIP_RPROC_STARTED 0x01 71 #define IMX_SIP_RPROC_STOP 0x02 72 73 #define IMX_SC_IRQ_GROUP_REBOOTED 5 74 75 /** 76 * struct imx_rproc_mem - slim internal memory structure 77 * @cpu_addr: MPU virtual address of the memory region 78 * @sys_addr: Bus address used to access the memory region 79 * @size: Size of the memory region 80 */ 81 struct imx_rproc_mem { 82 void __iomem *cpu_addr; 83 phys_addr_t sys_addr; 84 size_t size; 85 }; 86 87 /* att flags: lower 16 bits specifying core, higher 16 bits for flags */ 88 /* M4 own area. Can be mapped at probe */ 89 #define ATT_OWN BIT(31) 90 #define ATT_IOMEM BIT(30) 91 92 #define ATT_CORE_MASK 0xffff 93 #define ATT_CORE(I) BIT((I)) 94 95 static int imx_rproc_xtr_mbox_init(struct rproc *rproc, bool tx_block); 96 static void imx_rproc_free_mbox(struct rproc *rproc); 97 98 struct imx_rproc { 99 struct device *dev; 100 struct regmap *regmap; 101 struct regmap *gpr; 102 struct rproc *rproc; 103 const struct imx_rproc_dcfg *dcfg; 104 struct imx_rproc_mem mem[IMX_RPROC_MEM_MAX]; 105 struct clk *clk; 106 struct mbox_client cl; 107 struct mbox_chan *tx_ch; 108 struct mbox_chan *rx_ch; 109 struct work_struct rproc_work; 110 struct workqueue_struct *workqueue; 111 void __iomem *rsc_table; 112 struct imx_sc_ipc *ipc_handle; 113 struct notifier_block rproc_nb; 114 u32 rproc_pt; /* partition id */ 115 u32 rsrc_id; /* resource id */ 116 u32 entry; /* cpu start address */ 117 u32 core_index; 118 struct dev_pm_domain_list *pd_list; 119 }; 120 121 static const struct imx_rproc_att imx_rproc_att_imx93[] = { 122 /* dev addr , sys addr , size , flags */ 123 /* TCM CODE NON-SECURE */ 124 { 0x0FFC0000, 0x201C0000, 0x00040000, ATT_OWN | ATT_IOMEM }, 125 126 /* TCM CODE SECURE */ 127 { 0x1FFC0000, 0x201C0000, 0x00040000, ATT_OWN | ATT_IOMEM }, 128 129 /* TCM SYS NON-SECURE*/ 130 { 0x20000000, 0x20200000, 0x00040000, ATT_OWN | ATT_IOMEM }, 131 132 /* TCM SYS SECURE*/ 133 { 0x30000000, 0x20200000, 0x00040000, ATT_OWN | ATT_IOMEM }, 134 135 /* DDR */ 136 { 0x80000000, 0x80000000, 0x10000000, 0 }, 137 { 0x90000000, 0x80000000, 0x10000000, 0 }, 138 139 { 0xC0000000, 0xC0000000, 0x10000000, 0 }, 140 { 0xD0000000, 0xC0000000, 0x10000000, 0 }, 141 }; 142 143 static const struct imx_rproc_att imx_rproc_att_imx8qm[] = { 144 /* dev addr , sys addr , size , flags */ 145 { 0x08000000, 0x08000000, 0x10000000, 0}, 146 /* TCML */ 147 { 0x1FFE0000, 0x34FE0000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(0)}, 148 { 0x1FFE0000, 0x38FE0000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(1)}, 149 /* TCMU */ 150 { 0x20000000, 0x35000000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(0)}, 151 { 0x20000000, 0x39000000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(1)}, 152 /* DDR (Data) */ 153 { 0x80000000, 0x80000000, 0x60000000, 0 }, 154 }; 155 156 static const struct imx_rproc_att imx_rproc_att_imx8qxp[] = { 157 { 0x08000000, 0x08000000, 0x10000000, 0 }, 158 /* TCML/U */ 159 { 0x1FFE0000, 0x34FE0000, 0x00040000, ATT_OWN | ATT_IOMEM }, 160 /* OCRAM(Low 96KB) */ 161 { 0x21000000, 0x00100000, 0x00018000, 0 }, 162 /* OCRAM */ 163 { 0x21100000, 0x00100000, 0x00040000, 0 }, 164 /* DDR (Data) */ 165 { 0x80000000, 0x80000000, 0x60000000, 0 }, 166 }; 167 168 static const struct imx_rproc_att imx_rproc_att_imx8mn[] = { 169 /* dev addr , sys addr , size , flags */ 170 /* ITCM */ 171 { 0x00000000, 0x007E0000, 0x00020000, ATT_OWN | ATT_IOMEM }, 172 /* OCRAM_S */ 173 { 0x00180000, 0x00180000, 0x00009000, 0 }, 174 /* OCRAM */ 175 { 0x00900000, 0x00900000, 0x00020000, 0 }, 176 /* OCRAM */ 177 { 0x00920000, 0x00920000, 0x00020000, 0 }, 178 /* OCRAM */ 179 { 0x00940000, 0x00940000, 0x00050000, 0 }, 180 /* QSPI Code - alias */ 181 { 0x08000000, 0x08000000, 0x08000000, 0 }, 182 /* DDR (Code) - alias */ 183 { 0x10000000, 0x40000000, 0x0FFE0000, 0 }, 184 /* DTCM */ 185 { 0x20000000, 0x00800000, 0x00020000, ATT_OWN | ATT_IOMEM }, 186 /* OCRAM_S - alias */ 187 { 0x20180000, 0x00180000, 0x00008000, ATT_OWN }, 188 /* OCRAM */ 189 { 0x20200000, 0x00900000, 0x00020000, ATT_OWN }, 190 /* OCRAM */ 191 { 0x20220000, 0x00920000, 0x00020000, ATT_OWN }, 192 /* OCRAM */ 193 { 0x20240000, 0x00940000, 0x00040000, ATT_OWN }, 194 /* DDR (Data) */ 195 { 0x40000000, 0x40000000, 0x80000000, 0 }, 196 }; 197 198 static const struct imx_rproc_att imx_rproc_att_imx8mq[] = { 199 /* dev addr , sys addr , size , flags */ 200 /* TCML - alias */ 201 { 0x00000000, 0x007e0000, 0x00020000, ATT_IOMEM}, 202 /* OCRAM_S */ 203 { 0x00180000, 0x00180000, 0x00008000, 0 }, 204 /* OCRAM */ 205 { 0x00900000, 0x00900000, 0x00020000, 0 }, 206 /* OCRAM */ 207 { 0x00920000, 0x00920000, 0x00020000, 0 }, 208 /* QSPI Code - alias */ 209 { 0x08000000, 0x08000000, 0x08000000, 0 }, 210 /* DDR (Code) - alias */ 211 { 0x10000000, 0x40000000, 0x0FFE0000, 0 }, 212 /* TCML/U */ 213 { 0x1FFE0000, 0x007E0000, 0x00040000, ATT_OWN | ATT_IOMEM}, 214 /* OCRAM_S */ 215 { 0x20180000, 0x00180000, 0x00008000, ATT_OWN }, 216 /* OCRAM */ 217 { 0x20200000, 0x00900000, 0x00020000, ATT_OWN }, 218 /* OCRAM */ 219 { 0x20220000, 0x00920000, 0x00020000, ATT_OWN }, 220 /* DDR (Data) */ 221 { 0x40000000, 0x40000000, 0x80000000, 0 }, 222 }; 223 224 static const struct imx_rproc_att imx_rproc_att_imx8ulp[] = { 225 {0x1FFC0000, 0x1FFC0000, 0xC0000, ATT_OWN}, 226 {0x21000000, 0x21000000, 0x10000, ATT_OWN}, 227 {0x80000000, 0x80000000, 0x60000000, 0} 228 }; 229 230 static const struct imx_rproc_att imx_rproc_att_imx7ulp[] = { 231 {0x1FFD0000, 0x1FFD0000, 0x30000, ATT_OWN}, 232 {0x20000000, 0x20000000, 0x10000, ATT_OWN}, 233 {0x2F000000, 0x2F000000, 0x20000, ATT_OWN}, 234 {0x2F020000, 0x2F020000, 0x20000, ATT_OWN}, 235 {0x60000000, 0x60000000, 0x40000000, 0} 236 }; 237 238 static const struct imx_rproc_att imx_rproc_att_imx7d[] = { 239 /* dev addr , sys addr , size , flags */ 240 /* OCRAM_S (M4 Boot code) - alias */ 241 { 0x00000000, 0x00180000, 0x00008000, 0 }, 242 /* OCRAM_S (Code) */ 243 { 0x00180000, 0x00180000, 0x00008000, ATT_OWN }, 244 /* OCRAM (Code) - alias */ 245 { 0x00900000, 0x00900000, 0x00020000, 0 }, 246 /* OCRAM_EPDC (Code) - alias */ 247 { 0x00920000, 0x00920000, 0x00020000, 0 }, 248 /* OCRAM_PXP (Code) - alias */ 249 { 0x00940000, 0x00940000, 0x00008000, 0 }, 250 /* TCML (Code) */ 251 { 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM }, 252 /* DDR (Code) - alias, first part of DDR (Data) */ 253 { 0x10000000, 0x80000000, 0x0FFF0000, 0 }, 254 255 /* TCMU (Data) */ 256 { 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM }, 257 /* OCRAM (Data) */ 258 { 0x20200000, 0x00900000, 0x00020000, 0 }, 259 /* OCRAM_EPDC (Data) */ 260 { 0x20220000, 0x00920000, 0x00020000, 0 }, 261 /* OCRAM_PXP (Data) */ 262 { 0x20240000, 0x00940000, 0x00008000, 0 }, 263 /* DDR (Data) */ 264 { 0x80000000, 0x80000000, 0x60000000, 0 }, 265 }; 266 267 static const struct imx_rproc_att imx_rproc_att_imx6sx[] = { 268 /* dev addr , sys addr , size , flags */ 269 /* TCML (M4 Boot Code) - alias */ 270 { 0x00000000, 0x007F8000, 0x00008000, ATT_IOMEM }, 271 /* OCRAM_S (Code) */ 272 { 0x00180000, 0x008F8000, 0x00004000, 0 }, 273 /* OCRAM_S (Code) - alias */ 274 { 0x00180000, 0x008FC000, 0x00004000, 0 }, 275 /* TCML (Code) */ 276 { 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM }, 277 /* DDR (Code) - alias, first part of DDR (Data) */ 278 { 0x10000000, 0x80000000, 0x0FFF8000, 0 }, 279 280 /* TCMU (Data) */ 281 { 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM }, 282 /* OCRAM_S (Data) - alias? */ 283 { 0x208F8000, 0x008F8000, 0x00004000, 0 }, 284 /* DDR (Data) */ 285 { 0x80000000, 0x80000000, 0x60000000, 0 }, 286 }; 287 288 static int imx_rproc_arm_smc_start(struct rproc *rproc) 289 { 290 struct arm_smccc_res res; 291 292 arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_START, 0, 0, 0, 0, 0, 0, &res); 293 294 return res.a0; 295 } 296 297 static int imx_rproc_mmio_start(struct rproc *rproc) 298 { 299 struct imx_rproc *priv = rproc->priv; 300 const struct imx_rproc_dcfg *dcfg = priv->dcfg; 301 302 if (priv->gpr) 303 return regmap_clear_bits(priv->gpr, dcfg->gpr_reg, dcfg->gpr_wait); 304 305 return regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, dcfg->src_start); 306 } 307 308 static int imx_rproc_scu_api_start(struct rproc *rproc) 309 { 310 struct imx_rproc *priv = rproc->priv; 311 312 return imx_sc_pm_cpu_start(priv->ipc_handle, priv->rsrc_id, true, priv->entry); 313 } 314 315 static int imx_rproc_start(struct rproc *rproc) 316 { 317 struct imx_rproc *priv = rproc->priv; 318 const struct imx_rproc_dcfg *dcfg = priv->dcfg; 319 struct device *dev = priv->dev; 320 int ret; 321 322 ret = imx_rproc_xtr_mbox_init(rproc, true); 323 if (ret) 324 return ret; 325 326 if (!dcfg->ops || !dcfg->ops->start) 327 return -EOPNOTSUPP; 328 329 ret = dcfg->ops->start(rproc); 330 if (ret) 331 dev_err(dev, "Failed to enable remote core!\n"); 332 333 return ret; 334 } 335 336 static int imx_rproc_arm_smc_stop(struct rproc *rproc) 337 { 338 struct imx_rproc *priv = rproc->priv; 339 struct arm_smccc_res res; 340 341 arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_STOP, 0, 0, 0, 0, 0, 0, &res); 342 if (res.a1) 343 dev_info(priv->dev, "Not in wfi, force stopped\n"); 344 345 return res.a0; 346 } 347 348 static int imx_rproc_mmio_stop(struct rproc *rproc) 349 { 350 struct imx_rproc *priv = rproc->priv; 351 const struct imx_rproc_dcfg *dcfg = priv->dcfg; 352 int ret; 353 354 if (priv->gpr) { 355 ret = regmap_set_bits(priv->gpr, dcfg->gpr_reg, dcfg->gpr_wait); 356 if (ret) { 357 dev_err(priv->dev, "Failed to quiescence M4 platform!\n"); 358 return ret; 359 } 360 } 361 362 return regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, dcfg->src_stop); 363 } 364 365 static int imx_rproc_scu_api_stop(struct rproc *rproc) 366 { 367 struct imx_rproc *priv = rproc->priv; 368 369 return imx_sc_pm_cpu_start(priv->ipc_handle, priv->rsrc_id, false, priv->entry); 370 } 371 372 static int imx_rproc_stop(struct rproc *rproc) 373 { 374 struct imx_rproc *priv = rproc->priv; 375 const struct imx_rproc_dcfg *dcfg = priv->dcfg; 376 struct device *dev = priv->dev; 377 int ret; 378 379 if (!dcfg->ops || !dcfg->ops->stop) 380 return -EOPNOTSUPP; 381 382 ret = dcfg->ops->stop(rproc); 383 if (ret) 384 dev_err(dev, "Failed to stop remote core\n"); 385 else 386 imx_rproc_free_mbox(rproc); 387 388 return ret; 389 } 390 391 static int imx_rproc_da_to_sys(struct imx_rproc *priv, u64 da, 392 size_t len, u64 *sys, bool *is_iomem) 393 { 394 const struct imx_rproc_dcfg *dcfg = priv->dcfg; 395 int i; 396 397 /* parse address translation table */ 398 for (i = 0; i < dcfg->att_size; i++) { 399 const struct imx_rproc_att *att = &dcfg->att[i]; 400 401 /* 402 * Ignore entries not belong to current core: 403 * i.MX8QM has dual general M4_[0,1] cores, M4_0's own entries 404 * has "ATT_CORE(0) & BIT(0)" true, M4_1's own entries has 405 * "ATT_CORE(1) & BIT(1)" true. 406 */ 407 if (att->flags & ATT_CORE_MASK) { 408 if (!((BIT(priv->core_index)) & (att->flags & ATT_CORE_MASK))) 409 continue; 410 } 411 412 if (da >= att->da && da + len < att->da + att->size) { 413 unsigned int offset = da - att->da; 414 415 *sys = att->sa + offset; 416 if (is_iomem) 417 *is_iomem = att->flags & ATT_IOMEM; 418 return 0; 419 } 420 } 421 422 dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%zx\n", 423 da, len); 424 return -ENOENT; 425 } 426 427 static void *imx_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem) 428 { 429 struct imx_rproc *priv = rproc->priv; 430 void *va = NULL; 431 u64 sys; 432 int i; 433 434 if (len == 0) 435 return NULL; 436 437 /* 438 * On device side we have many aliases, so we need to convert device 439 * address (M4) to system bus address first. 440 */ 441 if (imx_rproc_da_to_sys(priv, da, len, &sys, is_iomem)) 442 return NULL; 443 444 for (i = 0; i < IMX_RPROC_MEM_MAX; i++) { 445 if (sys >= priv->mem[i].sys_addr && sys + len < 446 priv->mem[i].sys_addr + priv->mem[i].size) { 447 unsigned int offset = sys - priv->mem[i].sys_addr; 448 /* __force to make sparse happy with type conversion */ 449 va = (__force void *)(priv->mem[i].cpu_addr + offset); 450 break; 451 } 452 } 453 454 dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%p\n", 455 da, len, va); 456 457 return va; 458 } 459 460 static int imx_rproc_mem_alloc(struct rproc *rproc, 461 struct rproc_mem_entry *mem) 462 { 463 struct device *dev = rproc->dev.parent; 464 void *va; 465 466 dev_dbg(dev, "map memory: %p+%zx\n", &mem->dma, mem->len); 467 va = ioremap_wc(mem->dma, mem->len); 468 if (IS_ERR_OR_NULL(va)) { 469 dev_err(dev, "Unable to map memory region: %p+%zx\n", 470 &mem->dma, mem->len); 471 return -ENOMEM; 472 } 473 474 /* Update memory entry va */ 475 mem->va = va; 476 477 return 0; 478 } 479 480 static int imx_rproc_mem_release(struct rproc *rproc, 481 struct rproc_mem_entry *mem) 482 { 483 dev_dbg(rproc->dev.parent, "unmap memory: %pa\n", &mem->dma); 484 iounmap(mem->va); 485 486 return 0; 487 } 488 489 static int imx_rproc_prepare(struct rproc *rproc) 490 { 491 struct imx_rproc *priv = rproc->priv; 492 struct device_node *np = priv->dev->of_node; 493 struct of_phandle_iterator it; 494 struct rproc_mem_entry *mem; 495 struct reserved_mem *rmem; 496 u32 da; 497 498 /* Register associated reserved memory regions */ 499 of_phandle_iterator_init(&it, np, "memory-region", NULL, 0); 500 while (of_phandle_iterator_next(&it) == 0) { 501 /* 502 * Ignore the first memory region which will be used vdev buffer. 503 * No need to do extra handlings, rproc_add_virtio_dev will handle it. 504 */ 505 if (!strcmp(it.node->name, "vdev0buffer")) 506 continue; 507 508 if (!strcmp(it.node->name, "rsc-table")) 509 continue; 510 511 rmem = of_reserved_mem_lookup(it.node); 512 if (!rmem) { 513 of_node_put(it.node); 514 dev_err(priv->dev, "unable to acquire memory-region\n"); 515 return -EINVAL; 516 } 517 518 /* No need to translate pa to da, i.MX use same map */ 519 da = rmem->base; 520 521 /* Register memory region */ 522 mem = rproc_mem_entry_init(priv->dev, NULL, (dma_addr_t)rmem->base, rmem->size, da, 523 imx_rproc_mem_alloc, imx_rproc_mem_release, 524 it.node->name); 525 526 if (mem) { 527 rproc_coredump_add_segment(rproc, da, rmem->size); 528 } else { 529 of_node_put(it.node); 530 return -ENOMEM; 531 } 532 533 rproc_add_carveout(rproc, mem); 534 } 535 536 return 0; 537 } 538 539 static int imx_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) 540 { 541 int ret; 542 543 ret = rproc_elf_load_rsc_table(rproc, fw); 544 if (ret) 545 dev_info(&rproc->dev, "No resource table in elf\n"); 546 547 return 0; 548 } 549 550 static void imx_rproc_kick(struct rproc *rproc, int vqid) 551 { 552 struct imx_rproc *priv = rproc->priv; 553 int err; 554 __u32 mmsg; 555 556 if (!priv->tx_ch) { 557 dev_err(priv->dev, "No initialized mbox tx channel\n"); 558 return; 559 } 560 561 /* 562 * Send the index of the triggered virtqueue as the mu payload. 563 * Let remote processor know which virtqueue is used. 564 */ 565 mmsg = vqid << 16; 566 567 err = mbox_send_message(priv->tx_ch, (void *)&mmsg); 568 if (err < 0) 569 dev_err(priv->dev, "%s: failed (%d, err:%d)\n", 570 __func__, vqid, err); 571 } 572 573 static int imx_rproc_attach(struct rproc *rproc) 574 { 575 return imx_rproc_xtr_mbox_init(rproc, true); 576 } 577 578 static int imx_rproc_detach(struct rproc *rproc) 579 { 580 struct imx_rproc *priv = rproc->priv; 581 const struct imx_rproc_dcfg *dcfg = priv->dcfg; 582 583 if (dcfg->method != IMX_RPROC_SCU_API) 584 return -EOPNOTSUPP; 585 586 if (imx_sc_rm_is_resource_owned(priv->ipc_handle, priv->rsrc_id)) 587 return -EOPNOTSUPP; 588 589 imx_rproc_free_mbox(rproc); 590 591 return 0; 592 } 593 594 static struct resource_table *imx_rproc_get_loaded_rsc_table(struct rproc *rproc, size_t *table_sz) 595 { 596 struct imx_rproc *priv = rproc->priv; 597 598 /* The resource table has already been mapped in imx_rproc_addr_init */ 599 if (!priv->rsc_table) 600 return NULL; 601 602 *table_sz = SZ_1K; 603 return (struct resource_table *)priv->rsc_table; 604 } 605 606 static struct resource_table * 607 imx_rproc_elf_find_loaded_rsc_table(struct rproc *rproc, const struct firmware *fw) 608 { 609 struct imx_rproc *priv = rproc->priv; 610 611 if (priv->rsc_table) 612 return (struct resource_table *)priv->rsc_table; 613 614 return rproc_elf_find_loaded_rsc_table(rproc, fw); 615 } 616 617 static const struct rproc_ops imx_rproc_ops = { 618 .prepare = imx_rproc_prepare, 619 .attach = imx_rproc_attach, 620 .detach = imx_rproc_detach, 621 .start = imx_rproc_start, 622 .stop = imx_rproc_stop, 623 .kick = imx_rproc_kick, 624 .da_to_va = imx_rproc_da_to_va, 625 .load = rproc_elf_load_segments, 626 .parse_fw = imx_rproc_parse_fw, 627 .find_loaded_rsc_table = imx_rproc_elf_find_loaded_rsc_table, 628 .get_loaded_rsc_table = imx_rproc_get_loaded_rsc_table, 629 .sanity_check = rproc_elf_sanity_check, 630 .get_boot_addr = rproc_elf_get_boot_addr, 631 }; 632 633 static int imx_rproc_addr_init(struct imx_rproc *priv, 634 struct platform_device *pdev) 635 { 636 const struct imx_rproc_dcfg *dcfg = priv->dcfg; 637 struct device *dev = &pdev->dev; 638 struct device_node *np = dev->of_node; 639 int a, b = 0, err, nph; 640 641 /* remap required addresses */ 642 for (a = 0; a < dcfg->att_size; a++) { 643 const struct imx_rproc_att *att = &dcfg->att[a]; 644 645 if (!(att->flags & ATT_OWN)) 646 continue; 647 648 if (b >= IMX_RPROC_MEM_MAX) 649 break; 650 651 if (att->flags & ATT_IOMEM) 652 priv->mem[b].cpu_addr = devm_ioremap(&pdev->dev, 653 att->sa, att->size); 654 else 655 priv->mem[b].cpu_addr = devm_ioremap_wc(&pdev->dev, 656 att->sa, att->size); 657 if (!priv->mem[b].cpu_addr) { 658 dev_err(dev, "failed to remap %#x bytes from %#x\n", att->size, att->sa); 659 return -ENOMEM; 660 } 661 priv->mem[b].sys_addr = att->sa; 662 priv->mem[b].size = att->size; 663 b++; 664 } 665 666 /* memory-region is optional property */ 667 nph = of_count_phandle_with_args(np, "memory-region", NULL); 668 if (nph <= 0) 669 return 0; 670 671 /* remap optional addresses */ 672 for (a = 0; a < nph; a++) { 673 struct device_node *node; 674 struct resource res; 675 676 node = of_parse_phandle(np, "memory-region", a); 677 if (!node) 678 continue; 679 /* Not map vdevbuffer, vdevring region */ 680 if (!strncmp(node->name, "vdev", strlen("vdev"))) { 681 of_node_put(node); 682 continue; 683 } 684 err = of_address_to_resource(node, 0, &res); 685 if (err) { 686 dev_err(dev, "unable to resolve memory region\n"); 687 of_node_put(node); 688 return err; 689 } 690 691 if (b >= IMX_RPROC_MEM_MAX) { 692 of_node_put(node); 693 break; 694 } 695 696 /* Not use resource version, because we might share region */ 697 priv->mem[b].cpu_addr = devm_ioremap_wc(&pdev->dev, res.start, resource_size(&res)); 698 if (!priv->mem[b].cpu_addr) { 699 dev_err(dev, "failed to remap %pr\n", &res); 700 of_node_put(node); 701 return -ENOMEM; 702 } 703 priv->mem[b].sys_addr = res.start; 704 priv->mem[b].size = resource_size(&res); 705 if (!strcmp(node->name, "rsc-table")) 706 priv->rsc_table = priv->mem[b].cpu_addr; 707 of_node_put(node); 708 b++; 709 } 710 711 return 0; 712 } 713 714 static int imx_rproc_notified_idr_cb(int id, void *ptr, void *data) 715 { 716 struct rproc *rproc = data; 717 718 rproc_vq_interrupt(rproc, id); 719 720 return 0; 721 } 722 723 static void imx_rproc_vq_work(struct work_struct *work) 724 { 725 struct imx_rproc *priv = container_of(work, struct imx_rproc, 726 rproc_work); 727 struct rproc *rproc = priv->rproc; 728 729 idr_for_each(&rproc->notifyids, imx_rproc_notified_idr_cb, rproc); 730 } 731 732 static void imx_rproc_rx_callback(struct mbox_client *cl, void *msg) 733 { 734 struct rproc *rproc = dev_get_drvdata(cl->dev); 735 struct imx_rproc *priv = rproc->priv; 736 737 queue_work(priv->workqueue, &priv->rproc_work); 738 } 739 740 static int imx_rproc_xtr_mbox_init(struct rproc *rproc, bool tx_block) 741 { 742 struct imx_rproc *priv = rproc->priv; 743 struct device *dev = priv->dev; 744 struct mbox_client *cl; 745 746 /* 747 * stop() and detach() will free the mbox channels, so need 748 * to request mbox channels in start() and attach(). 749 * 750 * Because start() and attach() not able to handle mbox defer 751 * probe, imx_rproc_xtr_mbox_init is also called in probe(). 752 * The check is to avoid request mbox again when start() or 753 * attach() after probe() returns success. 754 */ 755 if (priv->tx_ch && priv->rx_ch) 756 return 0; 757 758 if (!of_property_present(dev->of_node, "mbox-names")) 759 return 0; 760 761 cl = &priv->cl; 762 cl->dev = dev; 763 cl->tx_block = tx_block; 764 cl->tx_tout = 100; 765 cl->knows_txdone = false; 766 cl->rx_callback = imx_rproc_rx_callback; 767 768 priv->tx_ch = mbox_request_channel_byname(cl, "tx"); 769 if (IS_ERR(priv->tx_ch)) 770 return dev_err_probe(cl->dev, PTR_ERR(priv->tx_ch), 771 "failed to request tx mailbox channel\n"); 772 773 priv->rx_ch = mbox_request_channel_byname(cl, "rx"); 774 if (IS_ERR(priv->rx_ch)) { 775 mbox_free_channel(priv->tx_ch); 776 return dev_err_probe(cl->dev, PTR_ERR(priv->rx_ch), 777 "failed to request rx mailbox channel\n"); 778 } 779 780 return 0; 781 } 782 783 static void imx_rproc_free_mbox(struct rproc *rproc) 784 { 785 struct imx_rproc *priv = rproc->priv; 786 787 if (priv->tx_ch) { 788 mbox_free_channel(priv->tx_ch); 789 priv->tx_ch = NULL; 790 } 791 792 if (priv->rx_ch) { 793 mbox_free_channel(priv->rx_ch); 794 priv->rx_ch = NULL; 795 } 796 } 797 798 static void imx_rproc_put_scu(struct rproc *rproc) 799 { 800 struct imx_rproc *priv = rproc->priv; 801 const struct imx_rproc_dcfg *dcfg = priv->dcfg; 802 803 if (dcfg->method != IMX_RPROC_SCU_API) 804 return; 805 806 if (imx_sc_rm_is_resource_owned(priv->ipc_handle, priv->rsrc_id)) { 807 dev_pm_domain_detach_list(priv->pd_list); 808 return; 809 } 810 811 imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_REBOOTED, BIT(priv->rproc_pt), false); 812 imx_scu_irq_unregister_notifier(&priv->rproc_nb); 813 } 814 815 static int imx_rproc_partition_notify(struct notifier_block *nb, 816 unsigned long event, void *group) 817 { 818 struct imx_rproc *priv = container_of(nb, struct imx_rproc, rproc_nb); 819 820 /* Ignore other irqs */ 821 if (!((event & BIT(priv->rproc_pt)) && (*(u8 *)group == IMX_SC_IRQ_GROUP_REBOOTED))) 822 return 0; 823 824 rproc_report_crash(priv->rproc, RPROC_WATCHDOG); 825 826 pr_info("Partition%d reset!\n", priv->rproc_pt); 827 828 return 0; 829 } 830 831 static int imx_rproc_attach_pd(struct imx_rproc *priv) 832 { 833 struct device *dev = priv->dev; 834 int ret, i; 835 bool detached = true; 836 837 /* 838 * If there is only one power-domain entry, the platform driver framework 839 * will handle it, no need handle it in this driver. 840 */ 841 if (dev->pm_domain) 842 return 0; 843 844 ret = dev_pm_domain_attach_list(dev, NULL, &priv->pd_list); 845 if (ret < 0) 846 return ret; 847 /* 848 * If all the power domain devices are already turned on, the remote 849 * core is already powered up and running when the kernel booted (e.g., 850 * started by U-Boot's bootaux command). In this case attach to it. 851 */ 852 for (i = 0; i < ret; i++) { 853 if (!dev_pm_genpd_is_on(priv->pd_list->pd_devs[i])) { 854 detached = false; 855 break; 856 } 857 } 858 859 if (detached) 860 priv->rproc->state = RPROC_DETACHED; 861 862 return 0; 863 } 864 865 static int imx_rproc_arm_smc_detect_mode(struct rproc *rproc) 866 { 867 struct imx_rproc *priv = rproc->priv; 868 struct arm_smccc_res res; 869 870 arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_STARTED, 0, 0, 0, 0, 0, 0, &res); 871 if (res.a0) 872 priv->rproc->state = RPROC_DETACHED; 873 874 return 0; 875 } 876 877 static int imx_rproc_mmio_detect_mode(struct rproc *rproc) 878 { 879 const struct regmap_config config = { .name = "imx-rproc" }; 880 struct imx_rproc *priv = rproc->priv; 881 const struct imx_rproc_dcfg *dcfg = priv->dcfg; 882 struct device *dev = priv->dev; 883 struct regmap *regmap; 884 u32 val; 885 int ret; 886 887 priv->gpr = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,iomuxc-gpr"); 888 if (IS_ERR(priv->gpr)) 889 priv->gpr = NULL; 890 891 regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon"); 892 if (IS_ERR(regmap)) { 893 dev_err(dev, "failed to find syscon\n"); 894 return PTR_ERR(regmap); 895 } 896 897 priv->regmap = regmap; 898 regmap_attach_dev(dev, regmap, &config); 899 900 if (priv->gpr) { 901 ret = regmap_read(priv->gpr, dcfg->gpr_reg, &val); 902 if (val & dcfg->gpr_wait) { 903 /* 904 * After cold boot, the CM indicates its in wait 905 * state, but not fully powered off. Power it off 906 * fully so firmware can be loaded into it. 907 */ 908 imx_rproc_stop(priv->rproc); 909 return 0; 910 } 911 } 912 913 ret = regmap_read(regmap, dcfg->src_reg, &val); 914 if (ret) { 915 dev_err(dev, "Failed to read src\n"); 916 return ret; 917 } 918 919 if ((val & dcfg->src_mask) != dcfg->src_stop) 920 priv->rproc->state = RPROC_DETACHED; 921 922 return 0; 923 } 924 925 static int imx_rproc_scu_api_detect_mode(struct rproc *rproc) 926 { 927 struct imx_rproc *priv = rproc->priv; 928 struct device *dev = priv->dev; 929 int ret; 930 u8 pt; 931 932 ret = imx_scu_get_handle(&priv->ipc_handle); 933 if (ret) 934 return ret; 935 ret = of_property_read_u32(dev->of_node, "fsl,resource-id", &priv->rsrc_id); 936 if (ret) { 937 dev_err(dev, "No fsl,resource-id property\n"); 938 return ret; 939 } 940 941 if (priv->rsrc_id == IMX_SC_R_M4_1_PID0) 942 priv->core_index = 1; 943 else 944 priv->core_index = 0; 945 946 /* 947 * If Mcore resource is not owned by Acore partition, It is kicked by ROM, 948 * and Linux could only do IPC with Mcore and nothing else. 949 */ 950 if (imx_sc_rm_is_resource_owned(priv->ipc_handle, priv->rsrc_id)) { 951 if (of_property_read_u32(dev->of_node, "fsl,entry-address", &priv->entry)) 952 return -EINVAL; 953 954 return imx_rproc_attach_pd(priv); 955 } 956 957 priv->rproc->state = RPROC_DETACHED; 958 priv->rproc->recovery_disabled = false; 959 rproc_set_feature(priv->rproc, RPROC_FEAT_ATTACH_ON_RECOVERY); 960 961 /* Get partition id and enable irq in SCFW */ 962 ret = imx_sc_rm_get_resource_owner(priv->ipc_handle, priv->rsrc_id, &pt); 963 if (ret) { 964 dev_err(dev, "not able to get resource owner\n"); 965 return ret; 966 } 967 968 priv->rproc_pt = pt; 969 priv->rproc_nb.notifier_call = imx_rproc_partition_notify; 970 971 ret = imx_scu_irq_register_notifier(&priv->rproc_nb); 972 if (ret) { 973 dev_err(dev, "register scu notifier failed, %d\n", ret); 974 return ret; 975 } 976 977 ret = imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_REBOOTED, BIT(priv->rproc_pt), 978 true); 979 if (ret) { 980 imx_scu_irq_unregister_notifier(&priv->rproc_nb); 981 dev_err(dev, "Enable irq failed, %d\n", ret); 982 return ret; 983 } 984 985 return 0; 986 } 987 988 static int imx_rproc_detect_mode(struct imx_rproc *priv) 989 { 990 const struct imx_rproc_dcfg *dcfg = priv->dcfg; 991 992 /* 993 * To i.MX{7,8} ULP, Linux is under control of RTOS, no need 994 * dcfg->ops or dcfg->ops->detect_mode, it is state RPROC_DETACHED. 995 */ 996 if (!dcfg->ops || !dcfg->ops->detect_mode) { 997 priv->rproc->state = RPROC_DETACHED; 998 return 0; 999 } 1000 1001 return dcfg->ops->detect_mode(priv->rproc); 1002 } 1003 1004 static int imx_rproc_clk_enable(struct imx_rproc *priv) 1005 { 1006 const struct imx_rproc_dcfg *dcfg = priv->dcfg; 1007 struct device *dev = priv->dev; 1008 int ret; 1009 1010 /* Remote core is not under control of Linux or it is managed by SCU API */ 1011 if (dcfg->method == IMX_RPROC_NONE || dcfg->method == IMX_RPROC_SCU_API) 1012 return 0; 1013 1014 priv->clk = devm_clk_get(dev, NULL); 1015 if (IS_ERR(priv->clk)) { 1016 dev_err(dev, "Failed to get clock\n"); 1017 return PTR_ERR(priv->clk); 1018 } 1019 1020 /* 1021 * clk for M4 block including memory. Should be 1022 * enabled before .start for FW transfer. 1023 */ 1024 ret = clk_prepare_enable(priv->clk); 1025 if (ret) { 1026 dev_err(dev, "Failed to enable clock\n"); 1027 return ret; 1028 } 1029 1030 return 0; 1031 } 1032 1033 static int imx_rproc_sys_off_handler(struct sys_off_data *data) 1034 { 1035 struct rproc *rproc = data->cb_data; 1036 int ret; 1037 1038 imx_rproc_free_mbox(rproc); 1039 1040 ret = imx_rproc_xtr_mbox_init(rproc, false); 1041 if (ret) { 1042 dev_err(&rproc->dev, "Failed to request non-blocking mbox\n"); 1043 return NOTIFY_BAD; 1044 } 1045 1046 return NOTIFY_DONE; 1047 } 1048 1049 static int imx_rproc_probe(struct platform_device *pdev) 1050 { 1051 struct device *dev = &pdev->dev; 1052 struct device_node *np = dev->of_node; 1053 struct imx_rproc *priv; 1054 struct rproc *rproc; 1055 const struct imx_rproc_dcfg *dcfg; 1056 int ret; 1057 1058 /* set some other name then imx */ 1059 rproc = devm_rproc_alloc(dev, "imx-rproc", &imx_rproc_ops, 1060 NULL, sizeof(*priv)); 1061 if (!rproc) 1062 return -ENOMEM; 1063 1064 dcfg = of_device_get_match_data(dev); 1065 if (!dcfg) 1066 return -EINVAL; 1067 1068 priv = rproc->priv; 1069 priv->rproc = rproc; 1070 priv->dcfg = dcfg; 1071 priv->dev = dev; 1072 1073 dev_set_drvdata(dev, rproc); 1074 priv->workqueue = create_workqueue(dev_name(dev)); 1075 if (!priv->workqueue) { 1076 dev_err(dev, "cannot create workqueue\n"); 1077 return -ENOMEM; 1078 } 1079 1080 INIT_WORK(&priv->rproc_work, imx_rproc_vq_work); 1081 1082 ret = imx_rproc_xtr_mbox_init(rproc, true); 1083 if (ret) 1084 goto err_put_wkq; 1085 1086 ret = imx_rproc_addr_init(priv, pdev); 1087 if (ret) { 1088 dev_err(dev, "failed on imx_rproc_addr_init\n"); 1089 goto err_put_mbox; 1090 } 1091 1092 ret = imx_rproc_detect_mode(priv); 1093 if (ret) 1094 goto err_put_mbox; 1095 1096 ret = imx_rproc_clk_enable(priv); 1097 if (ret) 1098 goto err_put_scu; 1099 1100 if (rproc->state != RPROC_DETACHED) 1101 rproc->auto_boot = of_property_read_bool(np, "fsl,auto-boot"); 1102 1103 if (dcfg->flags & IMX_RPROC_NEED_SYSTEM_OFF) { 1104 /* 1105 * setup mailbox to non-blocking mode in 1106 * [SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_MODE_RESTART_PREPARE] 1107 * phase before invoking [SYS_OFF_MODE_POWER_OFF, SYS_OFF_MODE_RESTART] 1108 * atomic chain, see kernel/reboot.c. 1109 */ 1110 ret = devm_register_sys_off_handler(dev, SYS_OFF_MODE_POWER_OFF_PREPARE, 1111 SYS_OFF_PRIO_DEFAULT, 1112 imx_rproc_sys_off_handler, rproc); 1113 if (ret) { 1114 dev_err(dev, "register power off handler failure\n"); 1115 goto err_put_clk; 1116 } 1117 1118 ret = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART_PREPARE, 1119 SYS_OFF_PRIO_DEFAULT, 1120 imx_rproc_sys_off_handler, rproc); 1121 if (ret) { 1122 dev_err(dev, "register restart handler failure\n"); 1123 goto err_put_clk; 1124 } 1125 } 1126 1127 if (dcfg->method == IMX_RPROC_SCU_API) { 1128 pm_runtime_enable(dev); 1129 ret = pm_runtime_resume_and_get(dev); 1130 if (ret) { 1131 dev_err(dev, "pm_runtime get failed: %d\n", ret); 1132 goto err_put_clk; 1133 } 1134 } 1135 1136 ret = rproc_add(rproc); 1137 if (ret) { 1138 dev_err(dev, "rproc_add failed\n"); 1139 goto err_put_clk; 1140 } 1141 1142 return 0; 1143 1144 err_put_clk: 1145 clk_disable_unprepare(priv->clk); 1146 err_put_scu: 1147 imx_rproc_put_scu(rproc); 1148 err_put_mbox: 1149 imx_rproc_free_mbox(rproc); 1150 err_put_wkq: 1151 destroy_workqueue(priv->workqueue); 1152 1153 return ret; 1154 } 1155 1156 static void imx_rproc_remove(struct platform_device *pdev) 1157 { 1158 struct rproc *rproc = platform_get_drvdata(pdev); 1159 struct imx_rproc *priv = rproc->priv; 1160 1161 if (priv->dcfg->method == IMX_RPROC_SCU_API) { 1162 pm_runtime_disable(priv->dev); 1163 pm_runtime_put(priv->dev); 1164 } 1165 clk_disable_unprepare(priv->clk); 1166 rproc_del(rproc); 1167 imx_rproc_put_scu(rproc); 1168 imx_rproc_free_mbox(rproc); 1169 destroy_workqueue(priv->workqueue); 1170 } 1171 1172 static const struct imx_rproc_plat_ops imx_rproc_ops_arm_smc = { 1173 .start = imx_rproc_arm_smc_start, 1174 .stop = imx_rproc_arm_smc_stop, 1175 .detect_mode = imx_rproc_arm_smc_detect_mode, 1176 }; 1177 1178 static const struct imx_rproc_plat_ops imx_rproc_ops_mmio = { 1179 .start = imx_rproc_mmio_start, 1180 .stop = imx_rproc_mmio_stop, 1181 .detect_mode = imx_rproc_mmio_detect_mode, 1182 }; 1183 1184 static const struct imx_rproc_plat_ops imx_rproc_ops_scu_api = { 1185 .start = imx_rproc_scu_api_start, 1186 .stop = imx_rproc_scu_api_stop, 1187 .detect_mode = imx_rproc_scu_api_detect_mode, 1188 }; 1189 1190 static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mn_mmio = { 1191 .src_reg = IMX7D_SRC_SCR, 1192 .src_mask = IMX7D_M4_RST_MASK, 1193 .src_start = IMX7D_M4_START, 1194 .src_stop = IMX8M_M7_STOP, 1195 .gpr_reg = IMX8M_GPR22, 1196 .gpr_wait = IMX8M_GPR22_CM7_CPUWAIT, 1197 .att = imx_rproc_att_imx8mn, 1198 .att_size = ARRAY_SIZE(imx_rproc_att_imx8mn), 1199 .method = IMX_RPROC_MMIO, 1200 .ops = &imx_rproc_ops_mmio, 1201 }; 1202 1203 static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mn = { 1204 .att = imx_rproc_att_imx8mn, 1205 .att_size = ARRAY_SIZE(imx_rproc_att_imx8mn), 1206 .method = IMX_RPROC_SMC, 1207 .ops = &imx_rproc_ops_arm_smc, 1208 }; 1209 1210 static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mq = { 1211 .src_reg = IMX7D_SRC_SCR, 1212 .src_mask = IMX7D_M4_RST_MASK, 1213 .src_start = IMX7D_M4_START, 1214 .src_stop = IMX7D_M4_STOP, 1215 .att = imx_rproc_att_imx8mq, 1216 .att_size = ARRAY_SIZE(imx_rproc_att_imx8mq), 1217 .method = IMX_RPROC_MMIO, 1218 .ops = &imx_rproc_ops_mmio, 1219 }; 1220 1221 static const struct imx_rproc_dcfg imx_rproc_cfg_imx8qm = { 1222 .att = imx_rproc_att_imx8qm, 1223 .att_size = ARRAY_SIZE(imx_rproc_att_imx8qm), 1224 .method = IMX_RPROC_SCU_API, 1225 .ops = &imx_rproc_ops_scu_api, 1226 }; 1227 1228 static const struct imx_rproc_dcfg imx_rproc_cfg_imx8qxp = { 1229 .att = imx_rproc_att_imx8qxp, 1230 .att_size = ARRAY_SIZE(imx_rproc_att_imx8qxp), 1231 .method = IMX_RPROC_SCU_API, 1232 .ops = &imx_rproc_ops_scu_api, 1233 }; 1234 1235 static const struct imx_rproc_dcfg imx_rproc_cfg_imx8ulp = { 1236 .att = imx_rproc_att_imx8ulp, 1237 .att_size = ARRAY_SIZE(imx_rproc_att_imx8ulp), 1238 .method = IMX_RPROC_NONE, 1239 }; 1240 1241 static const struct imx_rproc_dcfg imx_rproc_cfg_imx7ulp = { 1242 .att = imx_rproc_att_imx7ulp, 1243 .att_size = ARRAY_SIZE(imx_rproc_att_imx7ulp), 1244 .method = IMX_RPROC_NONE, 1245 .flags = IMX_RPROC_NEED_SYSTEM_OFF, 1246 }; 1247 1248 static const struct imx_rproc_dcfg imx_rproc_cfg_imx7d = { 1249 .src_reg = IMX7D_SRC_SCR, 1250 .src_mask = IMX7D_M4_RST_MASK, 1251 .src_start = IMX7D_M4_START, 1252 .src_stop = IMX7D_M4_STOP, 1253 .att = imx_rproc_att_imx7d, 1254 .att_size = ARRAY_SIZE(imx_rproc_att_imx7d), 1255 .method = IMX_RPROC_MMIO, 1256 .ops = &imx_rproc_ops_mmio, 1257 }; 1258 1259 static const struct imx_rproc_dcfg imx_rproc_cfg_imx6sx = { 1260 .src_reg = IMX6SX_SRC_SCR, 1261 .src_mask = IMX6SX_M4_RST_MASK, 1262 .src_start = IMX6SX_M4_START, 1263 .src_stop = IMX6SX_M4_STOP, 1264 .att = imx_rproc_att_imx6sx, 1265 .att_size = ARRAY_SIZE(imx_rproc_att_imx6sx), 1266 .method = IMX_RPROC_MMIO, 1267 .ops = &imx_rproc_ops_mmio, 1268 }; 1269 1270 static const struct imx_rproc_dcfg imx_rproc_cfg_imx93 = { 1271 .att = imx_rproc_att_imx93, 1272 .att_size = ARRAY_SIZE(imx_rproc_att_imx93), 1273 .method = IMX_RPROC_SMC, 1274 .ops = &imx_rproc_ops_arm_smc, 1275 }; 1276 1277 static const struct of_device_id imx_rproc_of_match[] = { 1278 { .compatible = "fsl,imx7ulp-cm4", .data = &imx_rproc_cfg_imx7ulp }, 1279 { .compatible = "fsl,imx7d-cm4", .data = &imx_rproc_cfg_imx7d }, 1280 { .compatible = "fsl,imx6sx-cm4", .data = &imx_rproc_cfg_imx6sx }, 1281 { .compatible = "fsl,imx8mq-cm4", .data = &imx_rproc_cfg_imx8mq }, 1282 { .compatible = "fsl,imx8mm-cm4", .data = &imx_rproc_cfg_imx8mq }, 1283 { .compatible = "fsl,imx8mn-cm7", .data = &imx_rproc_cfg_imx8mn }, 1284 { .compatible = "fsl,imx8mp-cm7", .data = &imx_rproc_cfg_imx8mn }, 1285 { .compatible = "fsl,imx8mn-cm7-mmio", .data = &imx_rproc_cfg_imx8mn_mmio }, 1286 { .compatible = "fsl,imx8mp-cm7-mmio", .data = &imx_rproc_cfg_imx8mn_mmio }, 1287 { .compatible = "fsl,imx8qxp-cm4", .data = &imx_rproc_cfg_imx8qxp }, 1288 { .compatible = "fsl,imx8qm-cm4", .data = &imx_rproc_cfg_imx8qm }, 1289 { .compatible = "fsl,imx8ulp-cm33", .data = &imx_rproc_cfg_imx8ulp }, 1290 { .compatible = "fsl,imx93-cm33", .data = &imx_rproc_cfg_imx93 }, 1291 {}, 1292 }; 1293 MODULE_DEVICE_TABLE(of, imx_rproc_of_match); 1294 1295 static struct platform_driver imx_rproc_driver = { 1296 .probe = imx_rproc_probe, 1297 .remove = imx_rproc_remove, 1298 .driver = { 1299 .name = "imx-rproc", 1300 .of_match_table = imx_rproc_of_match, 1301 }, 1302 }; 1303 1304 module_platform_driver(imx_rproc_driver); 1305 1306 MODULE_LICENSE("GPL v2"); 1307 MODULE_DESCRIPTION("i.MX remote processor control driver"); 1308 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>"); 1309