1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright 2021 NXP */ 3 4 #include <dt-bindings/firmware/imx/rsrc.h> 5 #include <linux/arm-smccc.h> 6 #include <linux/clk.h> 7 #include <linux/err.h> 8 #include <linux/firmware.h> 9 #include <linux/firmware/imx/sci.h> 10 #include <linux/interrupt.h> 11 #include <linux/kernel.h> 12 #include <linux/mailbox_client.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_reserved_mem.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_domain.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/remoteproc.h> 23 #include <linux/slab.h> 24 25 #include "imx_rproc.h" 26 #include "remoteproc_elf_helpers.h" 27 #include "remoteproc_internal.h" 28 29 #define DSP_RPROC_CLK_MAX 5 30 31 /* 32 * Module parameters 33 */ 34 static unsigned int no_mailboxes; 35 module_param_named(no_mailboxes, no_mailboxes, int, 0644); 36 MODULE_PARM_DESC(no_mailboxes, 37 "There is no mailbox between cores, so ignore remote proc reply after start, default is 0 (off)."); 38 39 #define REMOTE_IS_READY BIT(0) 40 #define REMOTE_READY_WAIT_MAX_RETRIES 500 41 42 /* att flags */ 43 /* DSP own area */ 44 #define ATT_OWN BIT(31) 45 /* DSP instruction area */ 46 #define ATT_IRAM BIT(30) 47 48 /* Definitions for i.MX8MP */ 49 /* DAP registers */ 50 #define IMX8M_DAP_DEBUG 0x28800000 51 #define IMX8M_DAP_DEBUG_SIZE (64 * 1024) 52 #define IMX8M_DAP_PWRCTL (0x4000 + 0x3020) 53 #define IMX8M_PWRCTL_CORERESET BIT(16) 54 55 /* DSP audio mix registers */ 56 #define IMX8M_AudioDSP_REG0 0x100 57 #define IMX8M_AudioDSP_REG1 0x104 58 #define IMX8M_AudioDSP_REG2 0x108 59 #define IMX8M_AudioDSP_REG3 0x10c 60 61 #define IMX8M_AudioDSP_REG2_RUNSTALL BIT(5) 62 #define IMX8M_AudioDSP_REG2_PWAITMODE BIT(1) 63 64 /* Definitions for i.MX8ULP */ 65 #define IMX8ULP_SIM_LPAV_REG_SYSCTRL0 0x8 66 #define IMX8ULP_SYSCTRL0_DSP_DBG_RST BIT(25) 67 #define IMX8ULP_SYSCTRL0_DSP_PLAT_CLK_EN BIT(19) 68 #define IMX8ULP_SYSCTRL0_DSP_PBCLK_EN BIT(18) 69 #define IMX8ULP_SYSCTRL0_DSP_CLK_EN BIT(17) 70 #define IMX8ULP_SYSCTRL0_DSP_RST BIT(16) 71 #define IMX8ULP_SYSCTRL0_DSP_OCD_HALT BIT(14) 72 #define IMX8ULP_SYSCTRL0_DSP_STALL BIT(13) 73 74 #define IMX8ULP_SIP_HIFI_XRDC 0xc200000e 75 76 /* 77 * enum - Predefined Mailbox Messages 78 * 79 * @RP_MBOX_SUSPEND_SYSTEM: system suspend request for the remote processor 80 * 81 * @RP_MBOX_SUSPEND_ACK: successful response from remote processor for a 82 * suspend request 83 * 84 * @RP_MBOX_RESUME_SYSTEM: system resume request for the remote processor 85 * 86 * @RP_MBOX_RESUME_ACK: successful response from remote processor for a 87 * resume request 88 */ 89 enum imx_dsp_rp_mbox_messages { 90 RP_MBOX_SUSPEND_SYSTEM = 0xFF11, 91 RP_MBOX_SUSPEND_ACK = 0xFF12, 92 RP_MBOX_RESUME_SYSTEM = 0xFF13, 93 RP_MBOX_RESUME_ACK = 0xFF14, 94 }; 95 96 /** 97 * struct imx_dsp_rproc - DSP remote processor state 98 * @regmap: regmap handler 99 * @rproc: rproc handler 100 * @dsp_dcfg: device configuration pointer 101 * @clks: clocks needed by this device 102 * @cl: mailbox client to request the mailbox channel 103 * @cl_rxdb: mailbox client to request the mailbox channel for doorbell 104 * @tx_ch: mailbox tx channel handle 105 * @rx_ch: mailbox rx channel handle 106 * @rxdb_ch: mailbox rx doorbell channel handle 107 * @pd_dev: power domain device 108 * @pd_dev_link: power domain device link 109 * @ipc_handle: System Control Unit ipc handle 110 * @rproc_work: work for processing virtio interrupts 111 * @pm_comp: completion primitive to sync for suspend response 112 * @num_domains: power domain number 113 * @flags: control flags 114 */ 115 struct imx_dsp_rproc { 116 struct regmap *regmap; 117 struct rproc *rproc; 118 const struct imx_dsp_rproc_dcfg *dsp_dcfg; 119 struct clk_bulk_data clks[DSP_RPROC_CLK_MAX]; 120 struct mbox_client cl; 121 struct mbox_client cl_rxdb; 122 struct mbox_chan *tx_ch; 123 struct mbox_chan *rx_ch; 124 struct mbox_chan *rxdb_ch; 125 struct device **pd_dev; 126 struct device_link **pd_dev_link; 127 struct imx_sc_ipc *ipc_handle; 128 struct work_struct rproc_work; 129 struct completion pm_comp; 130 int num_domains; 131 u32 flags; 132 }; 133 134 /** 135 * struct imx_dsp_rproc_dcfg - DSP remote processor configuration 136 * @dcfg: imx_rproc_dcfg handler 137 * @reset: reset callback function 138 */ 139 struct imx_dsp_rproc_dcfg { 140 const struct imx_rproc_dcfg *dcfg; 141 int (*reset)(struct imx_dsp_rproc *priv); 142 }; 143 144 static const struct imx_rproc_att imx_dsp_rproc_att_imx8qm[] = { 145 /* dev addr , sys addr , size , flags */ 146 { 0x596e8000, 0x556e8000, 0x00008000, ATT_OWN }, 147 { 0x596f0000, 0x556f0000, 0x00008000, ATT_OWN }, 148 { 0x596f8000, 0x556f8000, 0x00000800, ATT_OWN | ATT_IRAM}, 149 { 0x55700000, 0x55700000, 0x00070000, ATT_OWN }, 150 /* DDR (Data) */ 151 { 0x80000000, 0x80000000, 0x60000000, 0}, 152 }; 153 154 static const struct imx_rproc_att imx_dsp_rproc_att_imx8qxp[] = { 155 /* dev addr , sys addr , size , flags */ 156 { 0x596e8000, 0x596e8000, 0x00008000, ATT_OWN }, 157 { 0x596f0000, 0x596f0000, 0x00008000, ATT_OWN }, 158 { 0x596f8000, 0x596f8000, 0x00000800, ATT_OWN | ATT_IRAM}, 159 { 0x59700000, 0x59700000, 0x00070000, ATT_OWN }, 160 /* DDR (Data) */ 161 { 0x80000000, 0x80000000, 0x60000000, 0}, 162 }; 163 164 static const struct imx_rproc_att imx_dsp_rproc_att_imx8mp[] = { 165 /* dev addr , sys addr , size , flags */ 166 { 0x3b6e8000, 0x3b6e8000, 0x00008000, ATT_OWN }, 167 { 0x3b6f0000, 0x3b6f0000, 0x00008000, ATT_OWN }, 168 { 0x3b6f8000, 0x3b6f8000, 0x00000800, ATT_OWN | ATT_IRAM}, 169 { 0x3b700000, 0x3b700000, 0x00040000, ATT_OWN }, 170 /* DDR (Data) */ 171 { 0x40000000, 0x40000000, 0x80000000, 0}, 172 }; 173 174 static const struct imx_rproc_att imx_dsp_rproc_att_imx8ulp[] = { 175 /* dev addr , sys addr , size , flags */ 176 { 0x21170000, 0x21170000, 0x00010000, ATT_OWN | ATT_IRAM}, 177 { 0x21180000, 0x21180000, 0x00010000, ATT_OWN }, 178 /* DDR (Data) */ 179 { 0x0c000000, 0x80000000, 0x10000000, 0}, 180 { 0x30000000, 0x90000000, 0x10000000, 0}, 181 }; 182 183 /* Initialize the mailboxes between cores, if exists */ 184 static int (*imx_dsp_rproc_mbox_init)(struct imx_dsp_rproc *priv); 185 186 /* Reset function for DSP on i.MX8MP */ 187 static int imx8mp_dsp_reset(struct imx_dsp_rproc *priv) 188 { 189 void __iomem *dap = ioremap_wc(IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE); 190 int pwrctl; 191 192 /* Put DSP into reset and stall */ 193 pwrctl = readl(dap + IMX8M_DAP_PWRCTL); 194 pwrctl |= IMX8M_PWRCTL_CORERESET; 195 writel(pwrctl, dap + IMX8M_DAP_PWRCTL); 196 197 /* Keep reset asserted for 10 cycles */ 198 usleep_range(1, 2); 199 200 regmap_update_bits(priv->regmap, IMX8M_AudioDSP_REG2, 201 IMX8M_AudioDSP_REG2_RUNSTALL, 202 IMX8M_AudioDSP_REG2_RUNSTALL); 203 204 /* Take the DSP out of reset and keep stalled for FW loading */ 205 pwrctl = readl(dap + IMX8M_DAP_PWRCTL); 206 pwrctl &= ~IMX8M_PWRCTL_CORERESET; 207 writel(pwrctl, dap + IMX8M_DAP_PWRCTL); 208 209 iounmap(dap); 210 return 0; 211 } 212 213 /* Reset function for DSP on i.MX8ULP */ 214 static int imx8ulp_dsp_reset(struct imx_dsp_rproc *priv) 215 { 216 struct arm_smccc_res res; 217 218 /* Put DSP into reset and stall */ 219 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 220 IMX8ULP_SYSCTRL0_DSP_RST, IMX8ULP_SYSCTRL0_DSP_RST); 221 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 222 IMX8ULP_SYSCTRL0_DSP_STALL, 223 IMX8ULP_SYSCTRL0_DSP_STALL); 224 225 /* Configure resources of DSP through TFA */ 226 arm_smccc_smc(IMX8ULP_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &res); 227 228 /* Take the DSP out of reset and keep stalled for FW loading */ 229 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 230 IMX8ULP_SYSCTRL0_DSP_RST, 0); 231 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 232 IMX8ULP_SYSCTRL0_DSP_DBG_RST, 0); 233 234 return 0; 235 } 236 237 /* Specific configuration for i.MX8MP */ 238 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8mp = { 239 .src_reg = IMX8M_AudioDSP_REG2, 240 .src_mask = IMX8M_AudioDSP_REG2_RUNSTALL, 241 .src_start = 0, 242 .src_stop = IMX8M_AudioDSP_REG2_RUNSTALL, 243 .att = imx_dsp_rproc_att_imx8mp, 244 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8mp), 245 .method = IMX_RPROC_MMIO, 246 }; 247 248 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8mp = { 249 .dcfg = &dsp_rproc_cfg_imx8mp, 250 .reset = imx8mp_dsp_reset, 251 }; 252 253 /* Specific configuration for i.MX8ULP */ 254 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8ulp = { 255 .src_reg = IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 256 .src_mask = IMX8ULP_SYSCTRL0_DSP_STALL, 257 .src_start = 0, 258 .src_stop = IMX8ULP_SYSCTRL0_DSP_STALL, 259 .att = imx_dsp_rproc_att_imx8ulp, 260 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8ulp), 261 .method = IMX_RPROC_MMIO, 262 }; 263 264 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8ulp = { 265 .dcfg = &dsp_rproc_cfg_imx8ulp, 266 .reset = imx8ulp_dsp_reset, 267 }; 268 269 /* Specific configuration for i.MX8QXP */ 270 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qxp = { 271 .att = imx_dsp_rproc_att_imx8qxp, 272 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qxp), 273 .method = IMX_RPROC_SCU_API, 274 }; 275 276 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qxp = { 277 .dcfg = &dsp_rproc_cfg_imx8qxp, 278 }; 279 280 /* Specific configuration for i.MX8QM */ 281 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qm = { 282 .att = imx_dsp_rproc_att_imx8qm, 283 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qm), 284 .method = IMX_RPROC_SCU_API, 285 }; 286 287 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qm = { 288 .dcfg = &dsp_rproc_cfg_imx8qm, 289 }; 290 291 static int imx_dsp_rproc_ready(struct rproc *rproc) 292 { 293 struct imx_dsp_rproc *priv = rproc->priv; 294 int i; 295 296 if (!priv->rxdb_ch) 297 return 0; 298 299 for (i = 0; i < REMOTE_READY_WAIT_MAX_RETRIES; i++) { 300 if (priv->flags & REMOTE_IS_READY) 301 return 0; 302 usleep_range(100, 200); 303 } 304 305 return -ETIMEDOUT; 306 } 307 308 /* 309 * Start function for rproc_ops 310 * 311 * There is a handshake for start procedure: when DSP starts, it 312 * will send a doorbell message to this driver, then the 313 * REMOTE_IS_READY flags is set, then driver will kick 314 * a message to DSP. 315 */ 316 static int imx_dsp_rproc_start(struct rproc *rproc) 317 { 318 struct imx_dsp_rproc *priv = rproc->priv; 319 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 320 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 321 struct device *dev = rproc->dev.parent; 322 int ret; 323 324 switch (dcfg->method) { 325 case IMX_RPROC_MMIO: 326 ret = regmap_update_bits(priv->regmap, 327 dcfg->src_reg, 328 dcfg->src_mask, 329 dcfg->src_start); 330 break; 331 case IMX_RPROC_SCU_API: 332 ret = imx_sc_pm_cpu_start(priv->ipc_handle, 333 IMX_SC_R_DSP, 334 true, 335 rproc->bootaddr); 336 break; 337 default: 338 return -EOPNOTSUPP; 339 } 340 341 if (ret) 342 dev_err(dev, "Failed to enable remote core!\n"); 343 else 344 ret = imx_dsp_rproc_ready(rproc); 345 346 return ret; 347 } 348 349 /* 350 * Stop function for rproc_ops 351 * It clears the REMOTE_IS_READY flags 352 */ 353 static int imx_dsp_rproc_stop(struct rproc *rproc) 354 { 355 struct imx_dsp_rproc *priv = rproc->priv; 356 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 357 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 358 struct device *dev = rproc->dev.parent; 359 int ret = 0; 360 361 if (rproc->state == RPROC_CRASHED) { 362 priv->flags &= ~REMOTE_IS_READY; 363 return 0; 364 } 365 366 switch (dcfg->method) { 367 case IMX_RPROC_MMIO: 368 ret = regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, 369 dcfg->src_stop); 370 break; 371 case IMX_RPROC_SCU_API: 372 ret = imx_sc_pm_cpu_start(priv->ipc_handle, 373 IMX_SC_R_DSP, 374 false, 375 rproc->bootaddr); 376 break; 377 default: 378 return -EOPNOTSUPP; 379 } 380 381 if (ret) 382 dev_err(dev, "Failed to stop remote core\n"); 383 else 384 priv->flags &= ~REMOTE_IS_READY; 385 386 return ret; 387 } 388 389 /** 390 * imx_dsp_rproc_sys_to_da() - internal memory translation helper 391 * @priv: private data pointer 392 * @sys: system address (DDR address) 393 * @len: length of the memory buffer 394 * @da: device address to translate 395 * 396 * Convert system address (DDR address) to device address (DSP) 397 * for there may be memory remap for device. 398 */ 399 static int imx_dsp_rproc_sys_to_da(struct imx_dsp_rproc *priv, u64 sys, 400 size_t len, u64 *da) 401 { 402 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 403 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 404 int i; 405 406 /* Parse address translation table */ 407 for (i = 0; i < dcfg->att_size; i++) { 408 const struct imx_rproc_att *att = &dcfg->att[i]; 409 410 if (sys >= att->sa && sys + len <= att->sa + att->size) { 411 unsigned int offset = sys - att->sa; 412 413 *da = att->da + offset; 414 return 0; 415 } 416 } 417 418 return -ENOENT; 419 } 420 421 /* Main virtqueue message work function 422 * 423 * This function is executed upon scheduling of the i.MX DSP remoteproc 424 * driver's workqueue. The workqueue is scheduled by the mailbox rx 425 * handler. 426 * 427 * This work function processes both the Tx and Rx virtqueue indices on 428 * every invocation. The rproc_vq_interrupt function can detect if there 429 * are new unprocessed messages or not (returns IRQ_NONE vs IRQ_HANDLED), 430 * but there is no need to check for these return values. The index 0 431 * triggering will process all pending Rx buffers, and the index 1 triggering 432 * will process all newly available Tx buffers and will wakeup any potentially 433 * blocked senders. 434 * 435 * NOTE: 436 * The current logic is based on an inherent design assumption of supporting 437 * only 2 vrings, but this can be changed if needed. 438 */ 439 static void imx_dsp_rproc_vq_work(struct work_struct *work) 440 { 441 struct imx_dsp_rproc *priv = container_of(work, struct imx_dsp_rproc, 442 rproc_work); 443 struct rproc *rproc = priv->rproc; 444 445 mutex_lock(&rproc->lock); 446 447 if (rproc->state != RPROC_RUNNING) 448 goto unlock_mutex; 449 450 rproc_vq_interrupt(priv->rproc, 0); 451 rproc_vq_interrupt(priv->rproc, 1); 452 453 unlock_mutex: 454 mutex_unlock(&rproc->lock); 455 } 456 457 /** 458 * imx_dsp_rproc_rx_tx_callback() - inbound mailbox message handler 459 * @cl: mailbox client pointer used for requesting the mailbox channel 460 * @data: mailbox payload 461 * 462 * This handler is invoked by mailbox driver whenever a mailbox 463 * message is received. Usually, the SUSPEND and RESUME related messages 464 * are handled in this function, other messages are handled by remoteproc core 465 */ 466 static void imx_dsp_rproc_rx_tx_callback(struct mbox_client *cl, void *data) 467 { 468 struct rproc *rproc = dev_get_drvdata(cl->dev); 469 struct imx_dsp_rproc *priv = rproc->priv; 470 struct device *dev = rproc->dev.parent; 471 u32 message = (u32)(*(u32 *)data); 472 473 dev_dbg(dev, "mbox msg: 0x%x\n", message); 474 475 switch (message) { 476 case RP_MBOX_SUSPEND_ACK: 477 complete(&priv->pm_comp); 478 break; 479 case RP_MBOX_RESUME_ACK: 480 complete(&priv->pm_comp); 481 break; 482 default: 483 schedule_work(&priv->rproc_work); 484 break; 485 } 486 } 487 488 /** 489 * imx_dsp_rproc_rxdb_callback() - inbound mailbox message handler 490 * @cl: mailbox client pointer used for requesting the mailbox channel 491 * @data: mailbox payload 492 * 493 * For doorbell, there is no message specified, just set REMOTE_IS_READY 494 * flag. 495 */ 496 static void imx_dsp_rproc_rxdb_callback(struct mbox_client *cl, void *data) 497 { 498 struct rproc *rproc = dev_get_drvdata(cl->dev); 499 struct imx_dsp_rproc *priv = rproc->priv; 500 501 /* Remote is ready after firmware is loaded and running */ 502 priv->flags |= REMOTE_IS_READY; 503 } 504 505 /** 506 * imx_dsp_rproc_mbox_alloc() - request mailbox channels 507 * @priv: private data pointer 508 * 509 * Request three mailbox channels (tx, rx, rxdb). 510 */ 511 static int imx_dsp_rproc_mbox_alloc(struct imx_dsp_rproc *priv) 512 { 513 struct device *dev = priv->rproc->dev.parent; 514 struct mbox_client *cl; 515 int ret; 516 517 if (!of_get_property(dev->of_node, "mbox-names", NULL)) 518 return 0; 519 520 cl = &priv->cl; 521 cl->dev = dev; 522 cl->tx_block = true; 523 cl->tx_tout = 100; 524 cl->knows_txdone = false; 525 cl->rx_callback = imx_dsp_rproc_rx_tx_callback; 526 527 /* Channel for sending message */ 528 priv->tx_ch = mbox_request_channel_byname(cl, "tx"); 529 if (IS_ERR(priv->tx_ch)) { 530 ret = PTR_ERR(priv->tx_ch); 531 dev_dbg(cl->dev, "failed to request tx mailbox channel: %d\n", 532 ret); 533 return ret; 534 } 535 536 /* Channel for receiving message */ 537 priv->rx_ch = mbox_request_channel_byname(cl, "rx"); 538 if (IS_ERR(priv->rx_ch)) { 539 ret = PTR_ERR(priv->rx_ch); 540 dev_dbg(cl->dev, "failed to request rx mailbox channel: %d\n", 541 ret); 542 goto free_channel_tx; 543 } 544 545 cl = &priv->cl_rxdb; 546 cl->dev = dev; 547 cl->rx_callback = imx_dsp_rproc_rxdb_callback; 548 549 /* 550 * RX door bell is used to receive the ready signal from remote 551 * after firmware loaded. 552 */ 553 priv->rxdb_ch = mbox_request_channel_byname(cl, "rxdb"); 554 if (IS_ERR(priv->rxdb_ch)) { 555 ret = PTR_ERR(priv->rxdb_ch); 556 dev_dbg(cl->dev, "failed to request mbox chan rxdb, ret %d\n", 557 ret); 558 goto free_channel_rx; 559 } 560 561 return 0; 562 563 free_channel_rx: 564 mbox_free_channel(priv->rx_ch); 565 free_channel_tx: 566 mbox_free_channel(priv->tx_ch); 567 return ret; 568 } 569 570 /* 571 * imx_dsp_rproc_mbox_no_alloc() 572 * 573 * Empty function for no mailbox between cores 574 * 575 * Always return 0 576 */ 577 static int imx_dsp_rproc_mbox_no_alloc(struct imx_dsp_rproc *priv) 578 { 579 return 0; 580 } 581 582 static void imx_dsp_rproc_free_mbox(struct imx_dsp_rproc *priv) 583 { 584 mbox_free_channel(priv->tx_ch); 585 mbox_free_channel(priv->rx_ch); 586 mbox_free_channel(priv->rxdb_ch); 587 } 588 589 /** 590 * imx_dsp_rproc_add_carveout() - request mailbox channels 591 * @priv: private data pointer 592 * 593 * This function registers specified memory entry in @rproc carveouts list 594 * The carveouts can help to mapping the memory address for DSP. 595 */ 596 static int imx_dsp_rproc_add_carveout(struct imx_dsp_rproc *priv) 597 { 598 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 599 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 600 struct rproc *rproc = priv->rproc; 601 struct device *dev = rproc->dev.parent; 602 struct device_node *np = dev->of_node; 603 struct of_phandle_iterator it; 604 struct rproc_mem_entry *mem; 605 struct reserved_mem *rmem; 606 void __iomem *cpu_addr; 607 int a; 608 u64 da; 609 610 /* Remap required addresses */ 611 for (a = 0; a < dcfg->att_size; a++) { 612 const struct imx_rproc_att *att = &dcfg->att[a]; 613 614 if (!(att->flags & ATT_OWN)) 615 continue; 616 617 if (imx_dsp_rproc_sys_to_da(priv, att->sa, att->size, &da)) 618 return -EINVAL; 619 620 cpu_addr = devm_ioremap_wc(dev, att->sa, att->size); 621 if (!cpu_addr) { 622 dev_err(dev, "failed to map memory %p\n", &att->sa); 623 return -ENOMEM; 624 } 625 626 /* Register memory region */ 627 mem = rproc_mem_entry_init(dev, (void __force *)cpu_addr, (dma_addr_t)att->sa, 628 att->size, da, NULL, NULL, "dsp_mem"); 629 630 if (mem) 631 rproc_coredump_add_segment(rproc, da, att->size); 632 else 633 return -ENOMEM; 634 635 rproc_add_carveout(rproc, mem); 636 } 637 638 of_phandle_iterator_init(&it, np, "memory-region", NULL, 0); 639 while (of_phandle_iterator_next(&it) == 0) { 640 /* 641 * Ignore the first memory region which will be used vdev buffer. 642 * No need to do extra handlings, rproc_add_virtio_dev will handle it. 643 */ 644 if (!strcmp(it.node->name, "vdev0buffer")) 645 continue; 646 647 rmem = of_reserved_mem_lookup(it.node); 648 if (!rmem) { 649 of_node_put(it.node); 650 dev_err(dev, "unable to acquire memory-region\n"); 651 return -EINVAL; 652 } 653 654 if (imx_dsp_rproc_sys_to_da(priv, rmem->base, rmem->size, &da)) { 655 of_node_put(it.node); 656 return -EINVAL; 657 } 658 659 cpu_addr = devm_ioremap_wc(dev, rmem->base, rmem->size); 660 if (!cpu_addr) { 661 of_node_put(it.node); 662 dev_err(dev, "failed to map memory %p\n", &rmem->base); 663 return -ENOMEM; 664 } 665 666 /* Register memory region */ 667 mem = rproc_mem_entry_init(dev, (void __force *)cpu_addr, (dma_addr_t)rmem->base, 668 rmem->size, da, NULL, NULL, it.node->name); 669 670 if (mem) { 671 rproc_coredump_add_segment(rproc, da, rmem->size); 672 } else { 673 of_node_put(it.node); 674 return -ENOMEM; 675 } 676 677 rproc_add_carveout(rproc, mem); 678 } 679 680 return 0; 681 } 682 683 /* Prepare function for rproc_ops */ 684 static int imx_dsp_rproc_prepare(struct rproc *rproc) 685 { 686 struct imx_dsp_rproc *priv = rproc->priv; 687 struct device *dev = rproc->dev.parent; 688 struct rproc_mem_entry *carveout; 689 int ret; 690 691 ret = imx_dsp_rproc_add_carveout(priv); 692 if (ret) { 693 dev_err(dev, "failed on imx_dsp_rproc_add_carveout\n"); 694 return ret; 695 } 696 697 pm_runtime_get_sync(dev); 698 699 /* 700 * Clear buffers after pm rumtime for internal ocram is not 701 * accessible if power and clock are not enabled. 702 */ 703 list_for_each_entry(carveout, &rproc->carveouts, node) { 704 if (carveout->va) 705 memset(carveout->va, 0, carveout->len); 706 } 707 708 return 0; 709 } 710 711 /* Unprepare function for rproc_ops */ 712 static int imx_dsp_rproc_unprepare(struct rproc *rproc) 713 { 714 pm_runtime_put_sync(rproc->dev.parent); 715 716 return 0; 717 } 718 719 /* Kick function for rproc_ops */ 720 static void imx_dsp_rproc_kick(struct rproc *rproc, int vqid) 721 { 722 struct imx_dsp_rproc *priv = rproc->priv; 723 struct device *dev = rproc->dev.parent; 724 int err; 725 __u32 mmsg; 726 727 if (!priv->tx_ch) { 728 dev_err(dev, "No initialized mbox tx channel\n"); 729 return; 730 } 731 732 /* 733 * Send the index of the triggered virtqueue as the mu payload. 734 * Let remote processor know which virtqueue is used. 735 */ 736 mmsg = vqid; 737 738 err = mbox_send_message(priv->tx_ch, (void *)&mmsg); 739 if (err < 0) 740 dev_err(dev, "%s: failed (%d, err:%d)\n", __func__, vqid, err); 741 } 742 743 /* 744 * Custom memory copy implementation for i.MX DSP Cores 745 * 746 * The IRAM is part of the HiFi DSP. 747 * According to hw specs only 32-bits writes are allowed. 748 */ 749 static int imx_dsp_rproc_memcpy(void *dst, const void *src, size_t size) 750 { 751 void __iomem *dest = (void __iomem *)dst; 752 const u8 *src_byte = src; 753 const u32 *source = src; 754 u32 affected_mask; 755 int i, q, r; 756 u32 tmp; 757 758 /* destination must be 32bit aligned */ 759 if (!IS_ALIGNED((uintptr_t)dest, 4)) 760 return -EINVAL; 761 762 q = size / 4; 763 r = size % 4; 764 765 /* copy data in units of 32 bits at a time */ 766 for (i = 0; i < q; i++) 767 writel(source[i], dest + i * 4); 768 769 if (r) { 770 affected_mask = GENMASK(8 * r, 0); 771 772 /* 773 * first read the 32bit data of dest, then change affected 774 * bytes, and write back to dest. 775 * For unaffected bytes, it should not be changed 776 */ 777 tmp = readl(dest + q * 4); 778 tmp &= ~affected_mask; 779 780 /* avoid reading after end of source */ 781 for (i = 0; i < r; i++) 782 tmp |= (src_byte[q * 4 + i] << (8 * i)); 783 784 writel(tmp, dest + q * 4); 785 } 786 787 return 0; 788 } 789 790 /* 791 * Custom memset implementation for i.MX DSP Cores 792 * 793 * The IRAM is part of the HiFi DSP. 794 * According to hw specs only 32-bits writes are allowed. 795 */ 796 static int imx_dsp_rproc_memset(void *addr, u8 value, size_t size) 797 { 798 void __iomem *tmp_dst = (void __iomem *)addr; 799 u32 tmp_val = value; 800 u32 affected_mask; 801 int q, r; 802 u32 tmp; 803 804 /* destination must be 32bit aligned */ 805 if (!IS_ALIGNED((uintptr_t)addr, 4)) 806 return -EINVAL; 807 808 tmp_val |= tmp_val << 8; 809 tmp_val |= tmp_val << 16; 810 811 q = size / 4; 812 r = size % 4; 813 814 while (q--) 815 writel(tmp_val, tmp_dst++); 816 817 if (r) { 818 affected_mask = GENMASK(8 * r, 0); 819 820 /* 821 * first read the 32bit data of addr, then change affected 822 * bytes, and write back to addr. 823 * For unaffected bytes, it should not be changed 824 */ 825 tmp = readl(tmp_dst); 826 tmp &= ~affected_mask; 827 828 tmp |= (tmp_val & affected_mask); 829 writel(tmp, tmp_dst); 830 } 831 832 return 0; 833 } 834 835 /* 836 * imx_dsp_rproc_elf_load_segments() - load firmware segments to memory 837 * @rproc: remote processor which will be booted using these fw segments 838 * @fw: the ELF firmware image 839 * 840 * This function loads the firmware segments to memory, where the remote 841 * processor expects them. 842 * 843 * Return: 0 on success and an appropriate error code otherwise 844 */ 845 static int imx_dsp_rproc_elf_load_segments(struct rproc *rproc, const struct firmware *fw) 846 { 847 struct device *dev = &rproc->dev; 848 const void *ehdr, *phdr; 849 int i, ret = 0; 850 u16 phnum; 851 const u8 *elf_data = fw->data; 852 u8 class = fw_elf_get_class(fw); 853 u32 elf_phdr_get_size = elf_size_of_phdr(class); 854 855 ehdr = elf_data; 856 phnum = elf_hdr_get_e_phnum(class, ehdr); 857 phdr = elf_data + elf_hdr_get_e_phoff(class, ehdr); 858 859 /* go through the available ELF segments */ 860 for (i = 0; i < phnum; i++, phdr += elf_phdr_get_size) { 861 u64 da = elf_phdr_get_p_paddr(class, phdr); 862 u64 memsz = elf_phdr_get_p_memsz(class, phdr); 863 u64 filesz = elf_phdr_get_p_filesz(class, phdr); 864 u64 offset = elf_phdr_get_p_offset(class, phdr); 865 u32 type = elf_phdr_get_p_type(class, phdr); 866 void *ptr; 867 868 if (type != PT_LOAD || !memsz) 869 continue; 870 871 dev_dbg(dev, "phdr: type %d da 0x%llx memsz 0x%llx filesz 0x%llx\n", 872 type, da, memsz, filesz); 873 874 if (filesz > memsz) { 875 dev_err(dev, "bad phdr filesz 0x%llx memsz 0x%llx\n", 876 filesz, memsz); 877 ret = -EINVAL; 878 break; 879 } 880 881 if (offset + filesz > fw->size) { 882 dev_err(dev, "truncated fw: need 0x%llx avail 0x%zx\n", 883 offset + filesz, fw->size); 884 ret = -EINVAL; 885 break; 886 } 887 888 if (!rproc_u64_fit_in_size_t(memsz)) { 889 dev_err(dev, "size (%llx) does not fit in size_t type\n", 890 memsz); 891 ret = -EOVERFLOW; 892 break; 893 } 894 895 /* grab the kernel address for this device address */ 896 ptr = rproc_da_to_va(rproc, da, memsz, NULL); 897 if (!ptr) { 898 dev_err(dev, "bad phdr da 0x%llx mem 0x%llx\n", da, 899 memsz); 900 ret = -EINVAL; 901 break; 902 } 903 904 /* put the segment where the remote processor expects it */ 905 if (filesz) { 906 ret = imx_dsp_rproc_memcpy(ptr, elf_data + offset, filesz); 907 if (ret) { 908 dev_err(dev, "memory copy failed for da 0x%llx memsz 0x%llx\n", 909 da, memsz); 910 break; 911 } 912 } 913 914 /* zero out remaining memory for this segment */ 915 if (memsz > filesz) { 916 ret = imx_dsp_rproc_memset(ptr + filesz, 0, memsz - filesz); 917 if (ret) { 918 dev_err(dev, "memset failed for da 0x%llx memsz 0x%llx\n", 919 da, memsz); 920 break; 921 } 922 } 923 } 924 925 return ret; 926 } 927 928 static int imx_dsp_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) 929 { 930 if (rproc_elf_load_rsc_table(rproc, fw)) 931 dev_warn(&rproc->dev, "no resource table found for this firmware\n"); 932 933 return 0; 934 } 935 936 static const struct rproc_ops imx_dsp_rproc_ops = { 937 .prepare = imx_dsp_rproc_prepare, 938 .unprepare = imx_dsp_rproc_unprepare, 939 .start = imx_dsp_rproc_start, 940 .stop = imx_dsp_rproc_stop, 941 .kick = imx_dsp_rproc_kick, 942 .load = imx_dsp_rproc_elf_load_segments, 943 .parse_fw = imx_dsp_rproc_parse_fw, 944 .sanity_check = rproc_elf_sanity_check, 945 .get_boot_addr = rproc_elf_get_boot_addr, 946 }; 947 948 /** 949 * imx_dsp_attach_pm_domains() - attach the power domains 950 * @priv: private data pointer 951 * 952 * On i.MX8QM and i.MX8QXP there is multiple power domains 953 * required, so need to link them. 954 */ 955 static int imx_dsp_attach_pm_domains(struct imx_dsp_rproc *priv) 956 { 957 struct device *dev = priv->rproc->dev.parent; 958 int ret, i; 959 960 priv->num_domains = of_count_phandle_with_args(dev->of_node, 961 "power-domains", 962 "#power-domain-cells"); 963 964 /* If only one domain, then no need to link the device */ 965 if (priv->num_domains <= 1) 966 return 0; 967 968 priv->pd_dev = devm_kmalloc_array(dev, priv->num_domains, 969 sizeof(*priv->pd_dev), 970 GFP_KERNEL); 971 if (!priv->pd_dev) 972 return -ENOMEM; 973 974 priv->pd_dev_link = devm_kmalloc_array(dev, priv->num_domains, 975 sizeof(*priv->pd_dev_link), 976 GFP_KERNEL); 977 if (!priv->pd_dev_link) 978 return -ENOMEM; 979 980 for (i = 0; i < priv->num_domains; i++) { 981 priv->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i); 982 if (IS_ERR(priv->pd_dev[i])) { 983 ret = PTR_ERR(priv->pd_dev[i]); 984 goto detach_pm; 985 } 986 987 /* 988 * device_link_add will check priv->pd_dev[i], if it is 989 * NULL, then will break. 990 */ 991 priv->pd_dev_link[i] = device_link_add(dev, 992 priv->pd_dev[i], 993 DL_FLAG_STATELESS | 994 DL_FLAG_PM_RUNTIME); 995 if (!priv->pd_dev_link[i]) { 996 dev_pm_domain_detach(priv->pd_dev[i], false); 997 ret = -EINVAL; 998 goto detach_pm; 999 } 1000 } 1001 1002 return 0; 1003 1004 detach_pm: 1005 while (--i >= 0) { 1006 device_link_del(priv->pd_dev_link[i]); 1007 dev_pm_domain_detach(priv->pd_dev[i], false); 1008 } 1009 1010 return ret; 1011 } 1012 1013 static int imx_dsp_detach_pm_domains(struct imx_dsp_rproc *priv) 1014 { 1015 int i; 1016 1017 if (priv->num_domains <= 1) 1018 return 0; 1019 1020 for (i = 0; i < priv->num_domains; i++) { 1021 device_link_del(priv->pd_dev_link[i]); 1022 dev_pm_domain_detach(priv->pd_dev[i], false); 1023 } 1024 1025 return 0; 1026 } 1027 1028 /** 1029 * imx_dsp_rproc_detect_mode() - detect DSP control mode 1030 * @priv: private data pointer 1031 * 1032 * Different platform has different control method for DSP, which depends 1033 * on how the DSP is integrated in platform. 1034 * 1035 * For i.MX8QXP and i.MX8QM, DSP should be started and stopped by System 1036 * Control Unit. 1037 * For i.MX8MP and i.MX8ULP, DSP should be started and stopped by system 1038 * integration module. 1039 */ 1040 static int imx_dsp_rproc_detect_mode(struct imx_dsp_rproc *priv) 1041 { 1042 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 1043 struct device *dev = priv->rproc->dev.parent; 1044 struct regmap *regmap; 1045 int ret = 0; 1046 1047 switch (dsp_dcfg->dcfg->method) { 1048 case IMX_RPROC_SCU_API: 1049 ret = imx_scu_get_handle(&priv->ipc_handle); 1050 if (ret) 1051 return ret; 1052 break; 1053 case IMX_RPROC_MMIO: 1054 regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,dsp-ctrl"); 1055 if (IS_ERR(regmap)) { 1056 dev_err(dev, "failed to find syscon\n"); 1057 return PTR_ERR(regmap); 1058 } 1059 1060 priv->regmap = regmap; 1061 break; 1062 default: 1063 ret = -EOPNOTSUPP; 1064 break; 1065 } 1066 1067 return ret; 1068 } 1069 1070 static const char *imx_dsp_clks_names[DSP_RPROC_CLK_MAX] = { 1071 /* DSP clocks */ 1072 "core", "ocram", "debug", "ipg", "mu", 1073 }; 1074 1075 static int imx_dsp_rproc_clk_get(struct imx_dsp_rproc *priv) 1076 { 1077 struct device *dev = priv->rproc->dev.parent; 1078 struct clk_bulk_data *clks = priv->clks; 1079 int i; 1080 1081 for (i = 0; i < DSP_RPROC_CLK_MAX; i++) 1082 clks[i].id = imx_dsp_clks_names[i]; 1083 1084 return devm_clk_bulk_get_optional(dev, DSP_RPROC_CLK_MAX, clks); 1085 } 1086 1087 static int imx_dsp_rproc_probe(struct platform_device *pdev) 1088 { 1089 const struct imx_dsp_rproc_dcfg *dsp_dcfg; 1090 struct device *dev = &pdev->dev; 1091 struct imx_dsp_rproc *priv; 1092 struct rproc *rproc; 1093 const char *fw_name; 1094 int ret; 1095 1096 dsp_dcfg = of_device_get_match_data(dev); 1097 if (!dsp_dcfg) 1098 return -ENODEV; 1099 1100 ret = rproc_of_parse_firmware(dev, 0, &fw_name); 1101 if (ret) { 1102 dev_err(dev, "failed to parse firmware-name property, ret = %d\n", 1103 ret); 1104 return ret; 1105 } 1106 1107 rproc = rproc_alloc(dev, "imx-dsp-rproc", &imx_dsp_rproc_ops, fw_name, 1108 sizeof(*priv)); 1109 if (!rproc) 1110 return -ENOMEM; 1111 1112 priv = rproc->priv; 1113 priv->rproc = rproc; 1114 priv->dsp_dcfg = dsp_dcfg; 1115 1116 if (no_mailboxes) 1117 imx_dsp_rproc_mbox_init = imx_dsp_rproc_mbox_no_alloc; 1118 else 1119 imx_dsp_rproc_mbox_init = imx_dsp_rproc_mbox_alloc; 1120 1121 dev_set_drvdata(dev, rproc); 1122 1123 INIT_WORK(&priv->rproc_work, imx_dsp_rproc_vq_work); 1124 1125 ret = imx_dsp_rproc_detect_mode(priv); 1126 if (ret) { 1127 dev_err(dev, "failed on imx_dsp_rproc_detect_mode\n"); 1128 goto err_put_rproc; 1129 } 1130 1131 /* There are multiple power domains required by DSP on some platform */ 1132 ret = imx_dsp_attach_pm_domains(priv); 1133 if (ret) { 1134 dev_err(dev, "failed on imx_dsp_attach_pm_domains\n"); 1135 goto err_put_rproc; 1136 } 1137 /* Get clocks */ 1138 ret = imx_dsp_rproc_clk_get(priv); 1139 if (ret) { 1140 dev_err(dev, "failed on imx_dsp_rproc_clk_get\n"); 1141 goto err_detach_domains; 1142 } 1143 1144 init_completion(&priv->pm_comp); 1145 rproc->auto_boot = false; 1146 ret = rproc_add(rproc); 1147 if (ret) { 1148 dev_err(dev, "rproc_add failed\n"); 1149 goto err_detach_domains; 1150 } 1151 1152 pm_runtime_enable(dev); 1153 1154 return 0; 1155 1156 err_detach_domains: 1157 imx_dsp_detach_pm_domains(priv); 1158 err_put_rproc: 1159 rproc_free(rproc); 1160 1161 return ret; 1162 } 1163 1164 static void imx_dsp_rproc_remove(struct platform_device *pdev) 1165 { 1166 struct rproc *rproc = platform_get_drvdata(pdev); 1167 struct imx_dsp_rproc *priv = rproc->priv; 1168 1169 pm_runtime_disable(&pdev->dev); 1170 rproc_del(rproc); 1171 imx_dsp_detach_pm_domains(priv); 1172 rproc_free(rproc); 1173 } 1174 1175 /* pm runtime functions */ 1176 static int imx_dsp_runtime_resume(struct device *dev) 1177 { 1178 struct rproc *rproc = dev_get_drvdata(dev); 1179 struct imx_dsp_rproc *priv = rproc->priv; 1180 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 1181 int ret; 1182 1183 /* 1184 * There is power domain attached with mailbox, if setup mailbox 1185 * in probe(), then the power of mailbox is always enabled, 1186 * the power can't be saved. 1187 * So move setup of mailbox to runtime resume. 1188 */ 1189 ret = imx_dsp_rproc_mbox_init(priv); 1190 if (ret) { 1191 dev_err(dev, "failed on imx_dsp_rproc_mbox_init\n"); 1192 return ret; 1193 } 1194 1195 ret = clk_bulk_prepare_enable(DSP_RPROC_CLK_MAX, priv->clks); 1196 if (ret) { 1197 dev_err(dev, "failed on clk_bulk_prepare_enable\n"); 1198 return ret; 1199 } 1200 1201 /* Reset DSP if needed */ 1202 if (dsp_dcfg->reset) 1203 dsp_dcfg->reset(priv); 1204 1205 return 0; 1206 } 1207 1208 static int imx_dsp_runtime_suspend(struct device *dev) 1209 { 1210 struct rproc *rproc = dev_get_drvdata(dev); 1211 struct imx_dsp_rproc *priv = rproc->priv; 1212 1213 clk_bulk_disable_unprepare(DSP_RPROC_CLK_MAX, priv->clks); 1214 1215 imx_dsp_rproc_free_mbox(priv); 1216 1217 return 0; 1218 } 1219 1220 static void imx_dsp_load_firmware(const struct firmware *fw, void *context) 1221 { 1222 struct rproc *rproc = context; 1223 int ret; 1224 1225 /* 1226 * Same flow as start procedure. 1227 * Load the ELF segments to memory firstly. 1228 */ 1229 ret = rproc_load_segments(rproc, fw); 1230 if (ret) 1231 goto out; 1232 1233 /* Start the remote processor */ 1234 ret = rproc->ops->start(rproc); 1235 if (ret) 1236 goto out; 1237 1238 rproc->ops->kick(rproc, 0); 1239 1240 out: 1241 release_firmware(fw); 1242 } 1243 1244 static int imx_dsp_suspend(struct device *dev) 1245 { 1246 struct rproc *rproc = dev_get_drvdata(dev); 1247 struct imx_dsp_rproc *priv = rproc->priv; 1248 __u32 mmsg = RP_MBOX_SUSPEND_SYSTEM; 1249 int ret; 1250 1251 if (rproc->state != RPROC_RUNNING) 1252 goto out; 1253 1254 reinit_completion(&priv->pm_comp); 1255 1256 /* Tell DSP that suspend is happening */ 1257 ret = mbox_send_message(priv->tx_ch, (void *)&mmsg); 1258 if (ret < 0) { 1259 dev_err(dev, "PM mbox_send_message failed: %d\n", ret); 1260 return ret; 1261 } 1262 1263 /* 1264 * DSP need to save the context at suspend. 1265 * Here waiting the response for DSP, then power can be disabled. 1266 */ 1267 if (!wait_for_completion_timeout(&priv->pm_comp, msecs_to_jiffies(100))) 1268 return -EBUSY; 1269 1270 out: 1271 /* 1272 * The power of DSP is disabled in suspend, so force pm runtime 1273 * to be suspend, then we can reenable the power and clocks at 1274 * resume stage. 1275 */ 1276 return pm_runtime_force_suspend(dev); 1277 } 1278 1279 static int imx_dsp_resume(struct device *dev) 1280 { 1281 struct rproc *rproc = dev_get_drvdata(dev); 1282 int ret = 0; 1283 1284 ret = pm_runtime_force_resume(dev); 1285 if (ret) 1286 return ret; 1287 1288 if (rproc->state != RPROC_RUNNING) 1289 return 0; 1290 1291 /* 1292 * The power of DSP is disabled at suspend, the memory of dsp 1293 * is reset, the image segments are lost. So need to reload 1294 * firmware and restart the DSP if it is in running state. 1295 */ 1296 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT, 1297 rproc->firmware, dev, GFP_KERNEL, 1298 rproc, imx_dsp_load_firmware); 1299 if (ret < 0) { 1300 dev_err(dev, "load firmware failed: %d\n", ret); 1301 goto err; 1302 } 1303 1304 return 0; 1305 1306 err: 1307 pm_runtime_force_suspend(dev); 1308 1309 return ret; 1310 } 1311 1312 static const struct dev_pm_ops imx_dsp_rproc_pm_ops = { 1313 SYSTEM_SLEEP_PM_OPS(imx_dsp_suspend, imx_dsp_resume) 1314 RUNTIME_PM_OPS(imx_dsp_runtime_suspend, imx_dsp_runtime_resume, NULL) 1315 }; 1316 1317 static const struct of_device_id imx_dsp_rproc_of_match[] = { 1318 { .compatible = "fsl,imx8qxp-hifi4", .data = &imx_dsp_rproc_cfg_imx8qxp }, 1319 { .compatible = "fsl,imx8qm-hifi4", .data = &imx_dsp_rproc_cfg_imx8qm }, 1320 { .compatible = "fsl,imx8mp-hifi4", .data = &imx_dsp_rproc_cfg_imx8mp }, 1321 { .compatible = "fsl,imx8ulp-hifi4", .data = &imx_dsp_rproc_cfg_imx8ulp }, 1322 {}, 1323 }; 1324 MODULE_DEVICE_TABLE(of, imx_dsp_rproc_of_match); 1325 1326 static struct platform_driver imx_dsp_rproc_driver = { 1327 .probe = imx_dsp_rproc_probe, 1328 .remove_new = imx_dsp_rproc_remove, 1329 .driver = { 1330 .name = "imx-dsp-rproc", 1331 .of_match_table = imx_dsp_rproc_of_match, 1332 .pm = pm_ptr(&imx_dsp_rproc_pm_ops), 1333 }, 1334 }; 1335 module_platform_driver(imx_dsp_rproc_driver); 1336 1337 MODULE_LICENSE("GPL v2"); 1338 MODULE_DESCRIPTION("i.MX HiFi Core Remote Processor Control Driver"); 1339 MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>"); 1340