1 /* 2 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/err.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/regulator/of_regulator.h> 25 #include <linux/platform_device.h> 26 #include <linux/regulator/driver.h> 27 #include <linux/regulator/machine.h> 28 #include <linux/regulator/pfuze100.h> 29 #include <linux/i2c.h> 30 #include <linux/slab.h> 31 #include <linux/regmap.h> 32 33 #define PFUZE_NUMREGS 128 34 #define PFUZE100_VOL_OFFSET 0 35 #define PFUZE100_STANDBY_OFFSET 1 36 #define PFUZE100_MODE_OFFSET 3 37 #define PFUZE100_CONF_OFFSET 4 38 39 #define PFUZE100_DEVICEID 0x0 40 #define PFUZE100_REVID 0x3 41 #define PFUZE100_FABID 0x4 42 43 #define PFUZE100_COINVOL 0x1a 44 #define PFUZE100_SW1ABVOL 0x20 45 #define PFUZE100_SW1CVOL 0x2e 46 #define PFUZE100_SW2VOL 0x35 47 #define PFUZE100_SW3AVOL 0x3c 48 #define PFUZE100_SW3BVOL 0x43 49 #define PFUZE100_SW4VOL 0x4a 50 #define PFUZE100_SWBSTCON1 0x66 51 #define PFUZE100_VREFDDRCON 0x6a 52 #define PFUZE100_VSNVSVOL 0x6b 53 #define PFUZE100_VGEN1VOL 0x6c 54 #define PFUZE100_VGEN2VOL 0x6d 55 #define PFUZE100_VGEN3VOL 0x6e 56 #define PFUZE100_VGEN4VOL 0x6f 57 #define PFUZE100_VGEN5VOL 0x70 58 #define PFUZE100_VGEN6VOL 0x71 59 60 enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3 }; 61 62 struct pfuze_regulator { 63 struct regulator_desc desc; 64 unsigned char stby_reg; 65 unsigned char stby_mask; 66 }; 67 68 struct pfuze_chip { 69 int chip_id; 70 struct regmap *regmap; 71 struct device *dev; 72 struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR]; 73 struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR]; 74 struct pfuze_regulator *pfuze_regulators; 75 }; 76 77 static const int pfuze100_swbst[] = { 78 5000000, 5050000, 5100000, 5150000, 79 }; 80 81 static const int pfuze100_vsnvs[] = { 82 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000, 83 }; 84 85 static const int pfuze100_coin[] = { 86 2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000, 87 }; 88 89 static const int pfuze3000_sw2lo[] = { 90 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000, 91 }; 92 93 static const int pfuze3000_sw2hi[] = { 94 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000, 95 }; 96 97 static const struct i2c_device_id pfuze_device_id[] = { 98 {.name = "pfuze100", .driver_data = PFUZE100}, 99 {.name = "pfuze200", .driver_data = PFUZE200}, 100 {.name = "pfuze3000", .driver_data = PFUZE3000}, 101 { } 102 }; 103 MODULE_DEVICE_TABLE(i2c, pfuze_device_id); 104 105 static const struct of_device_id pfuze_dt_ids[] = { 106 { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100}, 107 { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200}, 108 { .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000}, 109 { } 110 }; 111 MODULE_DEVICE_TABLE(of, pfuze_dt_ids); 112 113 static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay) 114 { 115 struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev); 116 int id = rdev_get_id(rdev); 117 unsigned int ramp_bits; 118 int ret; 119 120 if (id < PFUZE100_SWBST) { 121 ramp_delay = 12500 / ramp_delay; 122 ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3); 123 ret = regmap_update_bits(pfuze100->regmap, 124 rdev->desc->vsel_reg + 4, 125 0xc0, ramp_bits << 6); 126 if (ret < 0) 127 dev_err(pfuze100->dev, "ramp failed, err %d\n", ret); 128 } else 129 ret = -EACCES; 130 131 return ret; 132 } 133 134 static const struct regulator_ops pfuze100_ldo_regulator_ops = { 135 .enable = regulator_enable_regmap, 136 .disable = regulator_disable_regmap, 137 .is_enabled = regulator_is_enabled_regmap, 138 .list_voltage = regulator_list_voltage_linear, 139 .set_voltage_sel = regulator_set_voltage_sel_regmap, 140 .get_voltage_sel = regulator_get_voltage_sel_regmap, 141 }; 142 143 static const struct regulator_ops pfuze100_fixed_regulator_ops = { 144 .enable = regulator_enable_regmap, 145 .disable = regulator_disable_regmap, 146 .is_enabled = regulator_is_enabled_regmap, 147 .list_voltage = regulator_list_voltage_linear, 148 }; 149 150 static const struct regulator_ops pfuze100_sw_regulator_ops = { 151 .list_voltage = regulator_list_voltage_linear, 152 .set_voltage_sel = regulator_set_voltage_sel_regmap, 153 .get_voltage_sel = regulator_get_voltage_sel_regmap, 154 .set_voltage_time_sel = regulator_set_voltage_time_sel, 155 .set_ramp_delay = pfuze100_set_ramp_delay, 156 }; 157 158 static const struct regulator_ops pfuze100_swb_regulator_ops = { 159 .enable = regulator_enable_regmap, 160 .disable = regulator_disable_regmap, 161 .list_voltage = regulator_list_voltage_table, 162 .map_voltage = regulator_map_voltage_ascend, 163 .set_voltage_sel = regulator_set_voltage_sel_regmap, 164 .get_voltage_sel = regulator_get_voltage_sel_regmap, 165 166 }; 167 168 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \ 169 [_chip ## _ ## _name] = { \ 170 .desc = { \ 171 .name = #_name, \ 172 .n_voltages = 1, \ 173 .ops = &pfuze100_fixed_regulator_ops, \ 174 .type = REGULATOR_VOLTAGE, \ 175 .id = _chip ## _ ## _name, \ 176 .owner = THIS_MODULE, \ 177 .min_uV = (voltage), \ 178 .enable_reg = (base), \ 179 .enable_mask = 0x10, \ 180 }, \ 181 } 182 183 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \ 184 [_chip ## _ ## _name] = { \ 185 .desc = { \ 186 .name = #_name,\ 187 .n_voltages = ((max) - (min)) / (step) + 1, \ 188 .ops = &pfuze100_sw_regulator_ops, \ 189 .type = REGULATOR_VOLTAGE, \ 190 .id = _chip ## _ ## _name, \ 191 .owner = THIS_MODULE, \ 192 .min_uV = (min), \ 193 .uV_step = (step), \ 194 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ 195 .vsel_mask = 0x3f, \ 196 }, \ 197 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \ 198 .stby_mask = 0x3f, \ 199 } 200 201 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \ 202 [_chip ## _ ## _name] = { \ 203 .desc = { \ 204 .name = #_name, \ 205 .n_voltages = ARRAY_SIZE(voltages), \ 206 .ops = &pfuze100_swb_regulator_ops, \ 207 .type = REGULATOR_VOLTAGE, \ 208 .id = _chip ## _ ## _name, \ 209 .owner = THIS_MODULE, \ 210 .volt_table = voltages, \ 211 .vsel_reg = (base), \ 212 .vsel_mask = (mask), \ 213 .enable_reg = (base), \ 214 .enable_mask = 0x48, \ 215 }, \ 216 } 217 218 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \ 219 [_chip ## _ ## _name] = { \ 220 .desc = { \ 221 .name = #_name, \ 222 .n_voltages = ((max) - (min)) / (step) + 1, \ 223 .ops = &pfuze100_ldo_regulator_ops, \ 224 .type = REGULATOR_VOLTAGE, \ 225 .id = _chip ## _ ## _name, \ 226 .owner = THIS_MODULE, \ 227 .min_uV = (min), \ 228 .uV_step = (step), \ 229 .vsel_reg = (base), \ 230 .vsel_mask = 0xf, \ 231 .enable_reg = (base), \ 232 .enable_mask = 0x10, \ 233 }, \ 234 .stby_reg = (base), \ 235 .stby_mask = 0x20, \ 236 } 237 238 #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \ 239 [_chip ## _ ## _name] = { \ 240 .desc = { \ 241 .name = #_name, \ 242 .n_voltages = ARRAY_SIZE(voltages), \ 243 .ops = &pfuze100_swb_regulator_ops, \ 244 .type = REGULATOR_VOLTAGE, \ 245 .id = _chip ## _ ## _name, \ 246 .owner = THIS_MODULE, \ 247 .volt_table = voltages, \ 248 .vsel_reg = (base), \ 249 .vsel_mask = (mask), \ 250 .enable_reg = (base), \ 251 .enable_mask = 0x8, \ 252 }, \ 253 } 254 255 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \ 256 .desc = { \ 257 .name = #_name, \ 258 .n_voltages = ((max) - (min)) / (step) + 1, \ 259 .ops = &pfuze100_ldo_regulator_ops, \ 260 .type = REGULATOR_VOLTAGE, \ 261 .id = _chip ## _ ## _name, \ 262 .owner = THIS_MODULE, \ 263 .min_uV = (min), \ 264 .uV_step = (step), \ 265 .vsel_reg = (base), \ 266 .vsel_mask = 0x3, \ 267 .enable_reg = (base), \ 268 .enable_mask = 0x10, \ 269 }, \ 270 .stby_reg = (base), \ 271 .stby_mask = 0x20, \ 272 } 273 274 275 #define PFUZE3000_SW2_REG(_chip, _name, base, min, max, step) { \ 276 .desc = { \ 277 .name = #_name,\ 278 .n_voltages = ((max) - (min)) / (step) + 1, \ 279 .ops = &pfuze100_sw_regulator_ops, \ 280 .type = REGULATOR_VOLTAGE, \ 281 .id = _chip ## _ ## _name, \ 282 .owner = THIS_MODULE, \ 283 .min_uV = (min), \ 284 .uV_step = (step), \ 285 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ 286 .vsel_mask = 0x7, \ 287 }, \ 288 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \ 289 .stby_mask = 0x7, \ 290 } 291 292 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \ 293 .desc = { \ 294 .name = #_name,\ 295 .n_voltages = ((max) - (min)) / (step) + 1, \ 296 .ops = &pfuze100_sw_regulator_ops, \ 297 .type = REGULATOR_VOLTAGE, \ 298 .id = _chip ## _ ## _name, \ 299 .owner = THIS_MODULE, \ 300 .min_uV = (min), \ 301 .uV_step = (step), \ 302 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ 303 .vsel_mask = 0xf, \ 304 }, \ 305 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \ 306 .stby_mask = 0xf, \ 307 } 308 309 /* PFUZE100 */ 310 static struct pfuze_regulator pfuze100_regulators[] = { 311 PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000), 312 PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000), 313 PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000), 314 PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000), 315 PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000), 316 PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000), 317 PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst), 318 PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), 319 PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000), 320 PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000), 321 PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000), 322 PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000), 323 PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000), 324 PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000), 325 PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000), 326 }; 327 328 static struct pfuze_regulator pfuze200_regulators[] = { 329 PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000), 330 PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000), 331 PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000), 332 PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000), 333 PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst), 334 PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), 335 PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000), 336 PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000), 337 PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000), 338 PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000), 339 PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000), 340 PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000), 341 PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000), 342 PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin), 343 }; 344 345 static struct pfuze_regulator pfuze3000_regulators[] = { 346 PFUZE100_SW_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 700000, 1475000, 25000), 347 PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000), 348 PFUZE100_SWB_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo), 349 PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000), 350 PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst), 351 PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), 352 PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000), 353 PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000), 354 PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000), 355 PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000), 356 PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000), 357 PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000), 358 PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000), 359 }; 360 361 #ifdef CONFIG_OF 362 /* PFUZE100 */ 363 static struct of_regulator_match pfuze100_matches[] = { 364 { .name = "sw1ab", }, 365 { .name = "sw1c", }, 366 { .name = "sw2", }, 367 { .name = "sw3a", }, 368 { .name = "sw3b", }, 369 { .name = "sw4", }, 370 { .name = "swbst", }, 371 { .name = "vsnvs", }, 372 { .name = "vrefddr", }, 373 { .name = "vgen1", }, 374 { .name = "vgen2", }, 375 { .name = "vgen3", }, 376 { .name = "vgen4", }, 377 { .name = "vgen5", }, 378 { .name = "vgen6", }, 379 }; 380 381 /* PFUZE200 */ 382 static struct of_regulator_match pfuze200_matches[] = { 383 384 { .name = "sw1ab", }, 385 { .name = "sw2", }, 386 { .name = "sw3a", }, 387 { .name = "sw3b", }, 388 { .name = "swbst", }, 389 { .name = "vsnvs", }, 390 { .name = "vrefddr", }, 391 { .name = "vgen1", }, 392 { .name = "vgen2", }, 393 { .name = "vgen3", }, 394 { .name = "vgen4", }, 395 { .name = "vgen5", }, 396 { .name = "vgen6", }, 397 { .name = "coin", }, 398 }; 399 400 /* PFUZE3000 */ 401 static struct of_regulator_match pfuze3000_matches[] = { 402 403 { .name = "sw1a", }, 404 { .name = "sw1b", }, 405 { .name = "sw2", }, 406 { .name = "sw3", }, 407 { .name = "swbst", }, 408 { .name = "vsnvs", }, 409 { .name = "vrefddr", }, 410 { .name = "vldo1", }, 411 { .name = "vldo2", }, 412 { .name = "vccsd", }, 413 { .name = "v33", }, 414 { .name = "vldo3", }, 415 { .name = "vldo4", }, 416 }; 417 418 static struct of_regulator_match *pfuze_matches; 419 420 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip) 421 { 422 struct device *dev = chip->dev; 423 struct device_node *np, *parent; 424 int ret; 425 426 np = of_node_get(dev->of_node); 427 if (!np) 428 return -EINVAL; 429 430 parent = of_get_child_by_name(np, "regulators"); 431 if (!parent) { 432 dev_err(dev, "regulators node not found\n"); 433 return -EINVAL; 434 } 435 436 switch (chip->chip_id) { 437 case PFUZE3000: 438 pfuze_matches = pfuze3000_matches; 439 ret = of_regulator_match(dev, parent, pfuze3000_matches, 440 ARRAY_SIZE(pfuze3000_matches)); 441 break; 442 case PFUZE200: 443 pfuze_matches = pfuze200_matches; 444 ret = of_regulator_match(dev, parent, pfuze200_matches, 445 ARRAY_SIZE(pfuze200_matches)); 446 break; 447 448 case PFUZE100: 449 default: 450 pfuze_matches = pfuze100_matches; 451 ret = of_regulator_match(dev, parent, pfuze100_matches, 452 ARRAY_SIZE(pfuze100_matches)); 453 break; 454 } 455 456 of_node_put(parent); 457 if (ret < 0) { 458 dev_err(dev, "Error parsing regulator init data: %d\n", 459 ret); 460 return ret; 461 } 462 463 return 0; 464 } 465 466 static inline struct regulator_init_data *match_init_data(int index) 467 { 468 return pfuze_matches[index].init_data; 469 } 470 471 static inline struct device_node *match_of_node(int index) 472 { 473 return pfuze_matches[index].of_node; 474 } 475 #else 476 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip) 477 { 478 return 0; 479 } 480 481 static inline struct regulator_init_data *match_init_data(int index) 482 { 483 return NULL; 484 } 485 486 static inline struct device_node *match_of_node(int index) 487 { 488 return NULL; 489 } 490 #endif 491 492 static int pfuze_identify(struct pfuze_chip *pfuze_chip) 493 { 494 unsigned int value; 495 int ret; 496 497 ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value); 498 if (ret) 499 return ret; 500 501 if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) { 502 /* 503 * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013 504 * as ID=8 in PFUZE100 505 */ 506 dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8"); 507 } else if ((value & 0x0f) != pfuze_chip->chip_id && 508 (value & 0xf0) >> 4 != pfuze_chip->chip_id) { 509 /* device id NOT match with your setting */ 510 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value); 511 return -ENODEV; 512 } 513 514 ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value); 515 if (ret) 516 return ret; 517 dev_info(pfuze_chip->dev, 518 "Full layer: %x, Metal layer: %x\n", 519 (value & 0xf0) >> 4, value & 0x0f); 520 521 ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value); 522 if (ret) 523 return ret; 524 dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n", 525 (value & 0xc) >> 2, value & 0x3); 526 527 return 0; 528 } 529 530 static const struct regmap_config pfuze_regmap_config = { 531 .reg_bits = 8, 532 .val_bits = 8, 533 .max_register = PFUZE_NUMREGS - 1, 534 .cache_type = REGCACHE_RBTREE, 535 }; 536 537 static int pfuze100_regulator_probe(struct i2c_client *client, 538 const struct i2c_device_id *id) 539 { 540 struct pfuze_chip *pfuze_chip; 541 struct pfuze_regulator_platform_data *pdata = 542 dev_get_platdata(&client->dev); 543 struct regulator_config config = { }; 544 int i, ret; 545 const struct of_device_id *match; 546 u32 regulator_num; 547 u32 sw_check_start, sw_check_end, sw_hi = 0x40; 548 549 pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip), 550 GFP_KERNEL); 551 if (!pfuze_chip) 552 return -ENOMEM; 553 554 if (client->dev.of_node) { 555 match = of_match_device(of_match_ptr(pfuze_dt_ids), 556 &client->dev); 557 if (!match) { 558 dev_err(&client->dev, "Error: No device match found\n"); 559 return -ENODEV; 560 } 561 pfuze_chip->chip_id = (int)(long)match->data; 562 } else if (id) { 563 pfuze_chip->chip_id = id->driver_data; 564 } else { 565 dev_err(&client->dev, "No dts match or id table match found\n"); 566 return -ENODEV; 567 } 568 569 i2c_set_clientdata(client, pfuze_chip); 570 pfuze_chip->dev = &client->dev; 571 572 pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config); 573 if (IS_ERR(pfuze_chip->regmap)) { 574 ret = PTR_ERR(pfuze_chip->regmap); 575 dev_err(&client->dev, 576 "regmap allocation failed with err %d\n", ret); 577 return ret; 578 } 579 580 ret = pfuze_identify(pfuze_chip); 581 if (ret) { 582 dev_err(&client->dev, "unrecognized pfuze chip ID!\n"); 583 return ret; 584 } 585 586 /* use the right regulators after identify the right device */ 587 switch (pfuze_chip->chip_id) { 588 case PFUZE3000: 589 pfuze_chip->pfuze_regulators = pfuze3000_regulators; 590 regulator_num = ARRAY_SIZE(pfuze3000_regulators); 591 sw_check_start = PFUZE3000_SW2; 592 sw_check_end = PFUZE3000_SW2; 593 sw_hi = 1 << 3; 594 break; 595 case PFUZE200: 596 pfuze_chip->pfuze_regulators = pfuze200_regulators; 597 regulator_num = ARRAY_SIZE(pfuze200_regulators); 598 sw_check_start = PFUZE200_SW2; 599 sw_check_end = PFUZE200_SW3B; 600 break; 601 case PFUZE100: 602 default: 603 pfuze_chip->pfuze_regulators = pfuze100_regulators; 604 regulator_num = ARRAY_SIZE(pfuze100_regulators); 605 sw_check_start = PFUZE100_SW2; 606 sw_check_end = PFUZE100_SW4; 607 break; 608 } 609 dev_info(&client->dev, "pfuze%s found.\n", 610 (pfuze_chip->chip_id == PFUZE100) ? "100" : 611 ((pfuze_chip->chip_id == PFUZE200) ? "200" : "3000")); 612 613 memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators, 614 sizeof(pfuze_chip->regulator_descs)); 615 616 ret = pfuze_parse_regulators_dt(pfuze_chip); 617 if (ret) 618 return ret; 619 620 for (i = 0; i < regulator_num; i++) { 621 struct regulator_init_data *init_data; 622 struct regulator_desc *desc; 623 int val; 624 625 desc = &pfuze_chip->regulator_descs[i].desc; 626 627 if (pdata) 628 init_data = pdata->init_data[i]; 629 else 630 init_data = match_init_data(i); 631 632 /* SW2~SW4 high bit check and modify the voltage value table */ 633 if (i >= sw_check_start && i <= sw_check_end) { 634 regmap_read(pfuze_chip->regmap, desc->vsel_reg, &val); 635 if (val & sw_hi) { 636 if (pfuze_chip->chip_id == PFUZE3000) { 637 desc->volt_table = pfuze3000_sw2hi; 638 desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi); 639 } else { 640 desc->min_uV = 800000; 641 desc->uV_step = 50000; 642 desc->n_voltages = 51; 643 } 644 } 645 } 646 647 config.dev = &client->dev; 648 config.init_data = init_data; 649 config.driver_data = pfuze_chip; 650 config.of_node = match_of_node(i); 651 config.ena_gpio = -EINVAL; 652 653 pfuze_chip->regulators[i] = 654 devm_regulator_register(&client->dev, desc, &config); 655 if (IS_ERR(pfuze_chip->regulators[i])) { 656 dev_err(&client->dev, "register regulator%s failed\n", 657 pfuze_chip->pfuze_regulators[i].desc.name); 658 return PTR_ERR(pfuze_chip->regulators[i]); 659 } 660 } 661 662 return 0; 663 } 664 665 static struct i2c_driver pfuze_driver = { 666 .id_table = pfuze_device_id, 667 .driver = { 668 .name = "pfuze100-regulator", 669 .of_match_table = pfuze_dt_ids, 670 }, 671 .probe = pfuze100_regulator_probe, 672 }; 673 module_i2c_driver(pfuze_driver); 674 675 MODULE_AUTHOR("Robin Gong <b38343@freescale.com>"); 676 MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000 PMIC"); 677 MODULE_LICENSE("GPL v2"); 678