xref: /linux/drivers/regulator/pfuze100-regulator.c (revision bab2c80e5a6c855657482eac9e97f5f3eedb509a)
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
4 
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/err.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/regulator/of_regulator.h>
12 #include <linux/platform_device.h>
13 #include <linux/regulator/driver.h>
14 #include <linux/regulator/machine.h>
15 #include <linux/regulator/pfuze100.h>
16 #include <linux/i2c.h>
17 #include <linux/slab.h>
18 #include <linux/regmap.h>
19 
20 #define PFUZE_NUMREGS		128
21 #define PFUZE100_VOL_OFFSET	0
22 #define PFUZE100_STANDBY_OFFSET	1
23 #define PFUZE100_MODE_OFFSET	3
24 #define PFUZE100_CONF_OFFSET	4
25 
26 #define PFUZE100_DEVICEID	0x0
27 #define PFUZE100_REVID		0x3
28 #define PFUZE100_FABID		0x4
29 
30 #define PFUZE100_COINVOL	0x1a
31 #define PFUZE100_SW1ABVOL	0x20
32 #define PFUZE100_SW1CVOL	0x2e
33 #define PFUZE100_SW2VOL		0x35
34 #define PFUZE100_SW3AVOL	0x3c
35 #define PFUZE100_SW3BVOL	0x43
36 #define PFUZE100_SW4VOL		0x4a
37 #define PFUZE100_SWBSTCON1	0x66
38 #define PFUZE100_VREFDDRCON	0x6a
39 #define PFUZE100_VSNVSVOL	0x6b
40 #define PFUZE100_VGEN1VOL	0x6c
41 #define PFUZE100_VGEN2VOL	0x6d
42 #define PFUZE100_VGEN3VOL	0x6e
43 #define PFUZE100_VGEN4VOL	0x6f
44 #define PFUZE100_VGEN5VOL	0x70
45 #define PFUZE100_VGEN6VOL	0x71
46 
47 enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3 };
48 
49 struct pfuze_regulator {
50 	struct regulator_desc desc;
51 	unsigned char stby_reg;
52 	unsigned char stby_mask;
53 };
54 
55 struct pfuze_chip {
56 	int	chip_id;
57 	struct regmap *regmap;
58 	struct device *dev;
59 	struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
60 	struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
61 	struct pfuze_regulator *pfuze_regulators;
62 };
63 
64 static const int pfuze100_swbst[] = {
65 	5000000, 5050000, 5100000, 5150000,
66 };
67 
68 static const int pfuze100_vsnvs[] = {
69 	1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
70 };
71 
72 static const int pfuze100_coin[] = {
73 	2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
74 };
75 
76 static const int pfuze3000_sw1a[] = {
77 	700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000,
78 	900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000,
79 	1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000,
80 	1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1800000, 3300000,
81 };
82 
83 static const int pfuze3000_sw2lo[] = {
84 	1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000,
85 };
86 
87 static const int pfuze3000_sw2hi[] = {
88 	2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000,
89 };
90 
91 static const struct i2c_device_id pfuze_device_id[] = {
92 	{.name = "pfuze100", .driver_data = PFUZE100},
93 	{.name = "pfuze200", .driver_data = PFUZE200},
94 	{.name = "pfuze3000", .driver_data = PFUZE3000},
95 	{ }
96 };
97 MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
98 
99 static const struct of_device_id pfuze_dt_ids[] = {
100 	{ .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
101 	{ .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
102 	{ .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000},
103 	{ }
104 };
105 MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
106 
107 static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
108 {
109 	struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
110 	int id = rdev_get_id(rdev);
111 	unsigned int ramp_bits;
112 	int ret;
113 
114 	if (id < PFUZE100_SWBST) {
115 		ramp_delay = 12500 / ramp_delay;
116 		ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
117 		ret = regmap_update_bits(pfuze100->regmap,
118 					 rdev->desc->vsel_reg + 4,
119 					 0xc0, ramp_bits << 6);
120 		if (ret < 0)
121 			dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
122 	} else
123 		ret = -EACCES;
124 
125 	return ret;
126 }
127 
128 static const struct regulator_ops pfuze100_ldo_regulator_ops = {
129 	.enable = regulator_enable_regmap,
130 	.disable = regulator_disable_regmap,
131 	.is_enabled = regulator_is_enabled_regmap,
132 	.list_voltage = regulator_list_voltage_linear,
133 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
134 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
135 };
136 
137 static const struct regulator_ops pfuze100_fixed_regulator_ops = {
138 	.enable = regulator_enable_regmap,
139 	.disable = regulator_disable_regmap,
140 	.is_enabled = regulator_is_enabled_regmap,
141 	.list_voltage = regulator_list_voltage_linear,
142 };
143 
144 static const struct regulator_ops pfuze100_sw_regulator_ops = {
145 	.enable = regulator_enable_regmap,
146 	.disable = regulator_disable_regmap,
147 	.is_enabled = regulator_is_enabled_regmap,
148 	.list_voltage = regulator_list_voltage_linear,
149 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
150 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
151 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
152 	.set_ramp_delay = pfuze100_set_ramp_delay,
153 };
154 
155 static const struct regulator_ops pfuze100_swb_regulator_ops = {
156 	.enable = regulator_enable_regmap,
157 	.disable = regulator_disable_regmap,
158 	.is_enabled = regulator_is_enabled_regmap,
159 	.list_voltage = regulator_list_voltage_table,
160 	.map_voltage = regulator_map_voltage_ascend,
161 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
162 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
163 
164 };
165 
166 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage)	\
167 	[_chip ## _ ## _name] = {	\
168 		.desc = {	\
169 			.name = #_name,	\
170 			.n_voltages = 1,	\
171 			.ops = &pfuze100_fixed_regulator_ops,	\
172 			.type = REGULATOR_VOLTAGE,	\
173 			.id = _chip ## _ ## _name,	\
174 			.owner = THIS_MODULE,	\
175 			.min_uV = (voltage),	\
176 			.enable_reg = (base),	\
177 			.enable_mask = 0x10,	\
178 		},	\
179 	}
180 
181 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step)	\
182 	[_chip ## _ ## _name] = {	\
183 		.desc = {	\
184 			.name = #_name,\
185 			.n_voltages = ((max) - (min)) / (step) + 1,	\
186 			.ops = &pfuze100_sw_regulator_ops,	\
187 			.type = REGULATOR_VOLTAGE,	\
188 			.id = _chip ## _ ## _name,	\
189 			.owner = THIS_MODULE,	\
190 			.min_uV = (min),	\
191 			.uV_step = (step),	\
192 			.vsel_reg = (base) + PFUZE100_VOL_OFFSET,	\
193 			.vsel_mask = 0x3f,	\
194 			.enable_reg = (base) + PFUZE100_MODE_OFFSET,	\
195 			.enable_val = 0xc,	\
196 			.disable_val = 0x0,	\
197 			.enable_mask = 0xf,	\
198 			.enable_time = 500,	\
199 		},	\
200 		.stby_reg = (base) + PFUZE100_STANDBY_OFFSET,	\
201 		.stby_mask = 0x3f,	\
202 	}
203 
204 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages)	\
205 	[_chip ## _ ##  _name] = {	\
206 		.desc = {	\
207 			.name = #_name,	\
208 			.n_voltages = ARRAY_SIZE(voltages),	\
209 			.ops = &pfuze100_swb_regulator_ops,	\
210 			.type = REGULATOR_VOLTAGE,	\
211 			.id = _chip ## _ ## _name,	\
212 			.owner = THIS_MODULE,	\
213 			.volt_table = voltages,	\
214 			.vsel_reg = (base),	\
215 			.vsel_mask = (mask),	\
216 			.enable_reg = (base),	\
217 			.enable_mask = 0x48,	\
218 		},	\
219 	}
220 
221 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step)	\
222 	[_chip ## _ ## _name] = {	\
223 		.desc = {	\
224 			.name = #_name,	\
225 			.n_voltages = ((max) - (min)) / (step) + 1,	\
226 			.ops = &pfuze100_ldo_regulator_ops,	\
227 			.type = REGULATOR_VOLTAGE,	\
228 			.id = _chip ## _ ## _name,	\
229 			.owner = THIS_MODULE,	\
230 			.min_uV = (min),	\
231 			.uV_step = (step),	\
232 			.vsel_reg = (base),	\
233 			.vsel_mask = 0xf,	\
234 			.enable_reg = (base),	\
235 			.enable_mask = 0x10,	\
236 		},	\
237 		.stby_reg = (base),	\
238 		.stby_mask = 0x20,	\
239 	}
240 
241 #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages)	\
242 	[_chip ## _ ##  _name] = {	\
243 		.desc = {	\
244 			.name = #_name,	\
245 			.n_voltages = ARRAY_SIZE(voltages),	\
246 			.ops = &pfuze100_swb_regulator_ops,	\
247 			.type = REGULATOR_VOLTAGE,	\
248 			.id = _chip ## _ ## _name,	\
249 			.owner = THIS_MODULE,	\
250 			.volt_table = voltages,	\
251 			.vsel_reg = (base),	\
252 			.vsel_mask = (mask),	\
253 			.enable_reg = (base),	\
254 			.enable_mask = 0x8,	\
255 		},	\
256 	}
257 
258 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step)	{	\
259 	.desc = {	\
260 		.name = #_name,	\
261 		.n_voltages = ((max) - (min)) / (step) + 1,	\
262 		.ops = &pfuze100_ldo_regulator_ops,	\
263 		.type = REGULATOR_VOLTAGE,	\
264 		.id = _chip ## _ ## _name,	\
265 		.owner = THIS_MODULE,	\
266 		.min_uV = (min),	\
267 		.uV_step = (step),	\
268 		.vsel_reg = (base),	\
269 		.vsel_mask = 0x3,	\
270 		.enable_reg = (base),	\
271 		.enable_mask = 0x10,	\
272 	},	\
273 	.stby_reg = (base),	\
274 	.stby_mask = 0x20,	\
275 }
276 
277 
278 #define PFUZE3000_SW2_REG(_chip, _name, base, min, max, step)	{	\
279 	.desc = {	\
280 		.name = #_name,\
281 		.n_voltages = ((max) - (min)) / (step) + 1,	\
282 		.ops = &pfuze100_sw_regulator_ops,	\
283 		.type = REGULATOR_VOLTAGE,	\
284 		.id = _chip ## _ ## _name,	\
285 		.owner = THIS_MODULE,	\
286 		.min_uV = (min),	\
287 		.uV_step = (step),	\
288 		.vsel_reg = (base) + PFUZE100_VOL_OFFSET,	\
289 		.vsel_mask = 0x7,	\
290 	},	\
291 	.stby_reg = (base) + PFUZE100_STANDBY_OFFSET,	\
292 	.stby_mask = 0x7,	\
293 }
294 
295 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step)	{	\
296 	.desc = {	\
297 		.name = #_name,\
298 		.n_voltages = ((max) - (min)) / (step) + 1,	\
299 		.ops = &pfuze100_sw_regulator_ops,	\
300 		.type = REGULATOR_VOLTAGE,	\
301 		.id = _chip ## _ ## _name,	\
302 		.owner = THIS_MODULE,	\
303 		.min_uV = (min),	\
304 		.uV_step = (step),	\
305 		.vsel_reg = (base) + PFUZE100_VOL_OFFSET,	\
306 		.vsel_mask = 0xf,	\
307 	},	\
308 	.stby_reg = (base) + PFUZE100_STANDBY_OFFSET,	\
309 	.stby_mask = 0xf,	\
310 }
311 
312 /* PFUZE100 */
313 static struct pfuze_regulator pfuze100_regulators[] = {
314 	PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
315 	PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
316 	PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
317 	PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
318 	PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
319 	PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
320 	PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
321 	PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
322 	PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
323 	PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
324 	PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
325 	PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
326 	PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
327 	PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
328 	PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
329 };
330 
331 static struct pfuze_regulator pfuze200_regulators[] = {
332 	PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
333 	PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
334 	PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
335 	PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
336 	PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
337 	PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
338 	PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
339 	PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
340 	PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
341 	PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
342 	PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
343 	PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
344 	PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
345 	PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
346 };
347 
348 static struct pfuze_regulator pfuze3000_regulators[] = {
349 	PFUZE100_SWB_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
350 	PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),
351 	PFUZE100_SWB_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
352 	PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
353 	PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),
354 	PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
355 	PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000),
356 	PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
357 	PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
358 	PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
359 	PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
360 	PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
361 	PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
362 };
363 
364 #ifdef CONFIG_OF
365 /* PFUZE100 */
366 static struct of_regulator_match pfuze100_matches[] = {
367 	{ .name = "sw1ab",	},
368 	{ .name = "sw1c",	},
369 	{ .name = "sw2",	},
370 	{ .name = "sw3a",	},
371 	{ .name = "sw3b",	},
372 	{ .name = "sw4",	},
373 	{ .name = "swbst",	},
374 	{ .name = "vsnvs",	},
375 	{ .name = "vrefddr",	},
376 	{ .name = "vgen1",	},
377 	{ .name = "vgen2",	},
378 	{ .name = "vgen3",	},
379 	{ .name = "vgen4",	},
380 	{ .name = "vgen5",	},
381 	{ .name = "vgen6",	},
382 };
383 
384 /* PFUZE200 */
385 static struct of_regulator_match pfuze200_matches[] = {
386 
387 	{ .name = "sw1ab",	},
388 	{ .name = "sw2",	},
389 	{ .name = "sw3a",	},
390 	{ .name = "sw3b",	},
391 	{ .name = "swbst",	},
392 	{ .name = "vsnvs",	},
393 	{ .name = "vrefddr",	},
394 	{ .name = "vgen1",	},
395 	{ .name = "vgen2",	},
396 	{ .name = "vgen3",	},
397 	{ .name = "vgen4",	},
398 	{ .name = "vgen5",	},
399 	{ .name = "vgen6",	},
400 	{ .name = "coin",	},
401 };
402 
403 /* PFUZE3000 */
404 static struct of_regulator_match pfuze3000_matches[] = {
405 
406 	{ .name = "sw1a",	},
407 	{ .name = "sw1b",	},
408 	{ .name = "sw2",	},
409 	{ .name = "sw3",	},
410 	{ .name = "swbst",	},
411 	{ .name = "vsnvs",	},
412 	{ .name = "vrefddr",	},
413 	{ .name = "vldo1",	},
414 	{ .name = "vldo2",	},
415 	{ .name = "vccsd",	},
416 	{ .name = "v33",	},
417 	{ .name = "vldo3",	},
418 	{ .name = "vldo4",	},
419 };
420 
421 static struct of_regulator_match *pfuze_matches;
422 
423 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
424 {
425 	struct device *dev = chip->dev;
426 	struct device_node *np, *parent;
427 	int ret;
428 
429 	np = of_node_get(dev->of_node);
430 	if (!np)
431 		return -EINVAL;
432 
433 	parent = of_get_child_by_name(np, "regulators");
434 	if (!parent) {
435 		dev_err(dev, "regulators node not found\n");
436 		return -EINVAL;
437 	}
438 
439 	switch (chip->chip_id) {
440 	case PFUZE3000:
441 		pfuze_matches = pfuze3000_matches;
442 		ret = of_regulator_match(dev, parent, pfuze3000_matches,
443 					 ARRAY_SIZE(pfuze3000_matches));
444 		break;
445 	case PFUZE200:
446 		pfuze_matches = pfuze200_matches;
447 		ret = of_regulator_match(dev, parent, pfuze200_matches,
448 					 ARRAY_SIZE(pfuze200_matches));
449 		break;
450 
451 	case PFUZE100:
452 	default:
453 		pfuze_matches = pfuze100_matches;
454 		ret = of_regulator_match(dev, parent, pfuze100_matches,
455 					 ARRAY_SIZE(pfuze100_matches));
456 		break;
457 	}
458 
459 	of_node_put(parent);
460 	if (ret < 0) {
461 		dev_err(dev, "Error parsing regulator init data: %d\n",
462 			ret);
463 		return ret;
464 	}
465 
466 	return 0;
467 }
468 
469 static inline struct regulator_init_data *match_init_data(int index)
470 {
471 	return pfuze_matches[index].init_data;
472 }
473 
474 static inline struct device_node *match_of_node(int index)
475 {
476 	return pfuze_matches[index].of_node;
477 }
478 #else
479 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
480 {
481 	return 0;
482 }
483 
484 static inline struct regulator_init_data *match_init_data(int index)
485 {
486 	return NULL;
487 }
488 
489 static inline struct device_node *match_of_node(int index)
490 {
491 	return NULL;
492 }
493 #endif
494 
495 static int pfuze_identify(struct pfuze_chip *pfuze_chip)
496 {
497 	unsigned int value;
498 	int ret;
499 
500 	ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
501 	if (ret)
502 		return ret;
503 
504 	if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
505 		/*
506 		 * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
507 		 * as ID=8 in PFUZE100
508 		 */
509 		dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
510 	} else if ((value & 0x0f) != pfuze_chip->chip_id &&
511 		   (value & 0xf0) >> 4 != pfuze_chip->chip_id) {
512 		/* device id NOT match with your setting */
513 		dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
514 		return -ENODEV;
515 	}
516 
517 	ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
518 	if (ret)
519 		return ret;
520 	dev_info(pfuze_chip->dev,
521 		 "Full layer: %x, Metal layer: %x\n",
522 		 (value & 0xf0) >> 4, value & 0x0f);
523 
524 	ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
525 	if (ret)
526 		return ret;
527 	dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
528 		 (value & 0xc) >> 2, value & 0x3);
529 
530 	return 0;
531 }
532 
533 static const struct regmap_config pfuze_regmap_config = {
534 	.reg_bits = 8,
535 	.val_bits = 8,
536 	.max_register = PFUZE_NUMREGS - 1,
537 	.cache_type = REGCACHE_RBTREE,
538 };
539 
540 static int pfuze100_regulator_probe(struct i2c_client *client,
541 				    const struct i2c_device_id *id)
542 {
543 	struct pfuze_chip *pfuze_chip;
544 	struct pfuze_regulator_platform_data *pdata =
545 	    dev_get_platdata(&client->dev);
546 	struct regulator_config config = { };
547 	int i, ret;
548 	const struct of_device_id *match;
549 	u32 regulator_num;
550 	u32 sw_check_start, sw_check_end, sw_hi = 0x40;
551 
552 	pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
553 			GFP_KERNEL);
554 	if (!pfuze_chip)
555 		return -ENOMEM;
556 
557 	if (client->dev.of_node) {
558 		match = of_match_device(of_match_ptr(pfuze_dt_ids),
559 				&client->dev);
560 		if (!match) {
561 			dev_err(&client->dev, "Error: No device match found\n");
562 			return -ENODEV;
563 		}
564 		pfuze_chip->chip_id = (int)(long)match->data;
565 	} else if (id) {
566 		pfuze_chip->chip_id = id->driver_data;
567 	} else {
568 		dev_err(&client->dev, "No dts match or id table match found\n");
569 		return -ENODEV;
570 	}
571 
572 	i2c_set_clientdata(client, pfuze_chip);
573 	pfuze_chip->dev = &client->dev;
574 
575 	pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
576 	if (IS_ERR(pfuze_chip->regmap)) {
577 		ret = PTR_ERR(pfuze_chip->regmap);
578 		dev_err(&client->dev,
579 			"regmap allocation failed with err %d\n", ret);
580 		return ret;
581 	}
582 
583 	ret = pfuze_identify(pfuze_chip);
584 	if (ret) {
585 		dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
586 		return ret;
587 	}
588 
589 	/* use the right regulators after identify the right device */
590 	switch (pfuze_chip->chip_id) {
591 	case PFUZE3000:
592 		pfuze_chip->pfuze_regulators = pfuze3000_regulators;
593 		regulator_num = ARRAY_SIZE(pfuze3000_regulators);
594 		sw_check_start = PFUZE3000_SW2;
595 		sw_check_end = PFUZE3000_SW2;
596 		sw_hi = 1 << 3;
597 		break;
598 	case PFUZE200:
599 		pfuze_chip->pfuze_regulators = pfuze200_regulators;
600 		regulator_num = ARRAY_SIZE(pfuze200_regulators);
601 		sw_check_start = PFUZE200_SW2;
602 		sw_check_end = PFUZE200_SW3B;
603 		break;
604 	case PFUZE100:
605 	default:
606 		pfuze_chip->pfuze_regulators = pfuze100_regulators;
607 		regulator_num = ARRAY_SIZE(pfuze100_regulators);
608 		sw_check_start = PFUZE100_SW2;
609 		sw_check_end = PFUZE100_SW4;
610 		break;
611 	}
612 	dev_info(&client->dev, "pfuze%s found.\n",
613 		(pfuze_chip->chip_id == PFUZE100) ? "100" :
614 		((pfuze_chip->chip_id == PFUZE200) ? "200" : "3000"));
615 
616 	memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators,
617 		sizeof(pfuze_chip->regulator_descs));
618 
619 	ret = pfuze_parse_regulators_dt(pfuze_chip);
620 	if (ret)
621 		return ret;
622 
623 	for (i = 0; i < regulator_num; i++) {
624 		struct regulator_init_data *init_data;
625 		struct regulator_desc *desc;
626 		int val;
627 
628 		desc = &pfuze_chip->regulator_descs[i].desc;
629 
630 		if (pdata)
631 			init_data = pdata->init_data[i];
632 		else
633 			init_data = match_init_data(i);
634 
635 		/* SW2~SW4 high bit check and modify the voltage value table */
636 		if (i >= sw_check_start && i <= sw_check_end) {
637 			regmap_read(pfuze_chip->regmap, desc->vsel_reg, &val);
638 			if (val & sw_hi) {
639 				if (pfuze_chip->chip_id == PFUZE3000) {
640 					desc->volt_table = pfuze3000_sw2hi;
641 					desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi);
642 				} else {
643 					desc->min_uV = 800000;
644 					desc->uV_step = 50000;
645 					desc->n_voltages = 51;
646 				}
647 			}
648 		}
649 
650 		config.dev = &client->dev;
651 		config.init_data = init_data;
652 		config.driver_data = pfuze_chip;
653 		config.of_node = match_of_node(i);
654 
655 		pfuze_chip->regulators[i] =
656 			devm_regulator_register(&client->dev, desc, &config);
657 		if (IS_ERR(pfuze_chip->regulators[i])) {
658 			dev_err(&client->dev, "register regulator%s failed\n",
659 				pfuze_chip->pfuze_regulators[i].desc.name);
660 			return PTR_ERR(pfuze_chip->regulators[i]);
661 		}
662 	}
663 
664 	return 0;
665 }
666 
667 static struct i2c_driver pfuze_driver = {
668 	.id_table = pfuze_device_id,
669 	.driver = {
670 		.name = "pfuze100-regulator",
671 		.of_match_table = pfuze_dt_ids,
672 	},
673 	.probe = pfuze100_regulator_probe,
674 };
675 module_i2c_driver(pfuze_driver);
676 
677 MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
678 MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000 PMIC");
679 MODULE_LICENSE("GPL v2");
680