1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2025 Analog Devices, Inc. 4 * ADI regulator driver for MAX77675. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/cleanup.h> 9 #include <linux/slab.h> 10 #include <linux/of.h> 11 #include <linux/i2c.h> 12 #include <linux/regmap.h> 13 #include <linux/platform_device.h> 14 #include <linux/regulator/driver.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/regulator/of_regulator.h> 17 #include <linux/bitfield.h> 18 #include <linux/bitops.h> 19 20 /* Register Addresses */ 21 #define MAX77675_REG_CNFG_GLBL_A 0x00 22 #define MAX77675_REG_CNFG_GLBL_B 0x01 23 #define MAX77675_REG_INT_GLBL 0x02 24 #define MAX77675_REG_INTM_GLBL 0x03 25 #define MAX77675_REG_STAT_GLBL 0x04 26 #define MAX77675_REG_ERCF_GLBL 0x05 27 #define MAX77675_REG_CID 0x06 28 #define MAX77675_REG_CNFG_SBB_TOP_A 0x07 29 #define MAX77675_REG_CNFG_SBB0_A 0x08 30 #define MAX77675_REG_CNFG_SBB0_B 0x09 31 #define MAX77675_REG_CNFG_SBB1_A 0x0A 32 #define MAX77675_REG_CNFG_SBB1_B 0x0B 33 #define MAX77675_REG_CNFG_SBB2_A 0x0C 34 #define MAX77675_REG_CNFG_SBB2_B 0x0D 35 #define MAX77675_REG_CNFG_SBB3_A 0x0E 36 #define MAX77675_REG_CNFG_SBB3_B 0x0F 37 #define MAX77675_REG_CNFG_SBB_TOP_B 0x10 38 39 /* CNFG_GLBL_A (0x00) bit masks and shifts */ 40 #define MAX77675_MRT_MASK GENMASK(7, 6) /* Manual Reset Time (bits 7:6) */ 41 #define MAX77675_MRT_SHIFT 6 42 #define MAX77675_PU_DIS_BIT BIT(5) /* Pullup Disable (bit 5) */ 43 #define MAX77675_PU_DIS_SHIFT 5 44 #define MAX77675_BIAS_LPM_BIT BIT(4) /* Bias Low Power Mode (bit 4) */ 45 #define MAX77675_BIAS_LPM_SHIFT 4 46 #define MAX77675_SIMO_CH_DIS_BIT BIT(3) /* SIMO Internal Channel Disable (bit 3) */ 47 #define MAX77675_SIMO_CH_DIS_SHIFT 3 48 #define MAX77675_EN_MODE_MASK GENMASK(2, 1) /* nEN Mode (bits 2:1) */ 49 #define MAX77675_EN_MODE_SHIFT 1 50 #define MAX77675_DBEN_EN_BIT BIT(0) /* Debounce Enable (bit 0) */ 51 #define MAX77675_DBEN_EN_SHIFT 0 52 53 /* CNFG_GLBL_B (0x01) */ 54 #define MAX77675_SFT_CTRL_MASK GENMASK(2, 0) /* Soft Start Control */ 55 #define MAX77675_SFT_CTRL_SHIFT 0 56 57 /* INT_GLBL (0x02) bit bits and shifts */ 58 #define MAX77675_INT_SBB3_F_BIT BIT(7) 59 #define MAX77675_INT_SBB3_F_SHIFT 7 60 #define MAX77675_INT_SBB2_F_BIT BIT(6) 61 #define MAX77675_INT_SBB2_F_SHIFT 6 62 #define MAX77675_INT_SBB1_F_BIT BIT(5) 63 #define MAX77675_INT_SBB1_F_SHIFT 5 64 #define MAX77675_INT_SBB0_F_BIT BIT(4) 65 #define MAX77675_INT_SBB0_F_SHIFT 4 66 #define MAX77675_INT_TJAL2_R_BIT BIT(3) 67 #define MAX77675_INT_TJAL2_R_SHIFT 3 68 #define MAX77675_INT_TJAL1_R_BIT BIT(2) 69 #define MAX77675_INT_TJAL1_R_SHIFT 2 70 #define MAX77675_INT_EN_R_BIT BIT(1) 71 #define MAX77675_INT_EN_R_SHIFT 1 72 #define MAX77675_INT_EN_F_BIT BIT(0) 73 #define MAX77675_INT_EN_F_SHIFT 0 74 75 /* INTM_GLBL (0x03) bits and shifts */ 76 #define MAX77675_INTM_SBB3_F_BIT BIT(7) 77 #define MAX77675_INTM_SBB3_F_SHIFT 7 78 #define MAX77675_INTM_SBB2_F_BIT BIT(6) 79 #define MAX77675_INTM_SBB2_F_SHIFT 6 80 #define MAX77675_INTM_SBB1_F_BIT BIT(5) 81 #define MAX77675_INTM_SBB1_F_SHIFT 5 82 #define MAX77675_INTM_SBB0_F_BIT BIT(4) 83 #define MAX77675_INTM_SBB0_F_SHIFT 4 84 #define MAX77675_INTM_TJAL2_R_BIT BIT(3) 85 #define MAX77675_INTM_TJAL2_R_SHIFT 3 86 #define MAX77675_INTM_TJAL1_R_BIT BIT(2) 87 #define MAX77675_INTM_TJAL1_R_SHIFT 2 88 #define MAX77675_INTM_EN_R_BIT BIT(1) 89 #define MAX77675_INTM_EN_R_SHIFT 1 90 #define MAX77675_INTM_EN_F_BIT BIT(0) 91 #define MAX77675_INTM_EN_F_SHIFT 0 92 93 /* STAT_GLBL (0x04) bits and shifts */ 94 #define MAX77675_STAT_SBB3_S_BIT BIT(7) 95 #define MAX77675_STAT_SBB3_S_SHIFT 7 96 #define MAX77675_STAT_SBB2_S_BIT BIT(6) 97 #define MAX77675_STAT_SBB2_S_SHIFT 6 98 #define MAX77675_STAT_SBB1_S_BIT BIT(5) 99 #define MAX77675_STAT_SBB1_S_SHIFT 5 100 #define MAX77675_STAT_SBB0_S_BIT BIT(4) 101 #define MAX77675_STAT_SBB0_S_SHIFT 4 102 #define MAX77675_STAT_TJAL2_S_BIT BIT(2) 103 #define MAX77675_STAT_TJAL2_S_SHIFT 2 104 #define MAX77675_STAT_TJAL1_S_BIT BIT(1) 105 #define MAX77675_STAT_TJAL1_S_SHIFT 1 106 #define MAX77675_STAT_STAT_EN_BIT BIT(0) 107 #define MAX77675_STAT_STAT_EN_SHIFT 0 108 109 #define MAX77675_STAT_STAT_EN_BIT BIT(0) 110 #define MAX77675_STAT_STAT_EN_SHIFT 0 111 112 /* ERCFLAG (0x05) bits and shifts */ 113 #define MAX77675_SFT_CRST_F_BIT BIT(5) /* Software Cold Reset Flag */ 114 #define MAX77675_SFT_CRST_F_SHIFT 5 115 #define MAX77675_SFT_OFF_F_BIT BIT(4) /* Software Off Flag */ 116 #define MAX77675_SFT_OFF_F_SHIFT 4 117 #define MAX77675_MRST_BIT BIT(3) /* Manual Reset Timer Flag */ 118 #define MAX77675_MRST_SHIFT 3 119 #define MAX77675_UVLO_BIT BIT(2) /* Undervoltage Lockout Flag */ 120 #define MAX77675_UVLO_SHIFT 2 121 #define MAX77675_OVLO_BIT BIT(1) /* Overvoltage Lockout Flag */ 122 #define MAX77675_OVLO_SHIFT 1 123 #define MAX77675_TOVLD_BIT BIT(0) /* Thermal Overload Flag */ 124 #define MAX77675_TOVLD_SHIFT 0 125 126 /* CID (0x06) bits and shifts */ 127 #define MAX77675_CID_MASK GENMASK(4, 0) /* Chip Identification Code mask */ 128 #define MAX77675_CID_SHIFT 0 /* Starts at bit 0 */ 129 130 /* CNFG_SBB_TOP_A (0x07) bits and shifts */ 131 #define MAX77675_STEP_SZ_SBB3_BIT BIT(5) 132 #define MAX77675_STEP_SZ_SBB3_SHIFT 5 133 #define MAX77675_STEP_SZ_SBB2_BIT BIT(4) 134 #define MAX77675_STEP_SZ_SBB2_SHIFT 4 135 #define MAX77675_STEP_SZ_SBB1_BIT BIT(3) 136 #define MAX77675_STEP_SZ_SBB1_SHIFT 3 137 #define MAX77675_STEP_SZ_SBB0_BIT BIT(2) 138 #define MAX77675_STEP_SZ_SBB0_SHIFT 2 139 #define MAX77675_DRV_SBB_MASK GENMASK(1, 0) 140 #define MAX77675_DRV_SBB_SHIFT 0 141 142 /* CNFG_SBB0_A (0x08) bits and shifts */ 143 #define MAX77675_TV_SBB0_MASK GENMASK(7, 0) 144 #define MAX77675_TV_SBB0_SHIFT 0 145 146 /* CNFG_SBB0_B (0x09) bits and shifts */ 147 #define MAX77675_ADE_SBB0_BIT BIT(3) 148 #define MAX77675_ADE_SBB0_SHIFT 3 149 #define MAX77675_EN_SBB0_MASK GENMASK(2, 0) 150 #define MAX77675_EN_SBB0_SHIFT 0 151 152 /* CNFG_SBB1_A (0x0A) bits and shifts */ 153 #define MAX77675_TV_SBB1_MASK GENMASK(7, 0) 154 #define MAX77675_TV_SBB1_SHIFT 0 155 156 /* CNFG_SBB1_B (0x0B) bits and shifts */ 157 #define MAX77675_ADE_SBB1_BIT BIT(3) 158 #define MAX77675_ADE_SBB1_SHIFT 3 159 #define MAX77675_EN_SBB1_MASK GENMASK(2, 0) 160 #define MAX77675_EN_SBB1_SHIFT 0 161 162 /* CNFG_SBB2_A (0x0C) bits and shifts */ 163 #define MAX77675_TV_SBB2_MASK GENMASK(7, 0) 164 #define MAX77675_TV_SBB2_SHIFT 0 165 166 /* CNFG_SBB2_B (0x0D) bits and shifts */ 167 #define MAX77675_ADE_SBB2_BIT BIT(3) 168 #define MAX77675_ADE_SBB2_SHIFT 3 169 #define MAX77675_EN_SBB2_MASK GENMASK(2, 0) 170 #define MAX77675_EN_SBB2_SHIFT 0 171 172 /* CNFG_SBB3_A (0x0E) bits and shifts */ 173 #define MAX77675_TV_SBB3_MASK GENMASK(7, 0) 174 #define MAX77675_TV_SBB3_SHIFT 0 175 176 /* CNFG_SBB3_B (0x0F) bits and shifts */ 177 #define MAX77675_ADE_SBB3_BIT BIT(3) 178 #define MAX77675_ADE_SBB3_SHIFT 3 179 #define MAX77675_EN_SBB3_MASK GENMASK(2, 0) 180 #define MAX77675_EN_SBB3_SHIFT 0 181 182 #define MAX77675_EN_SBB_MASK GENMASK(2, 0) 183 184 /* CNFG_SBB_TOP_B (0x10) bits and shifts */ 185 #define MAX77675_DVS_SLEW_BIT BIT(5) 186 #define MAX77675_DVS_SLEW_SHIFT 5 187 #define MAX77675_LAT_MODE_BIT BIT(4) 188 #define MAX77675_LAT_MODE_SHIFT 4 189 #define MAX77675_SR_SBB3_BIT BIT(3) 190 #define MAX77675_SR_SBB3_SHIFT 3 191 #define MAX77675_SR_SBB2_BIT BIT(2) 192 #define MAX77675_SR_SBB2_SHIFT 2 193 #define MAX77675_SR_SBB1_BIT BIT(1) 194 #define MAX77675_SR_SBB1_SHIFT 1 195 #define MAX77675_SR_SBB0_BIT BIT(0) 196 #define MAX77675_SR_SBB0_SHIFT 0 197 198 #define MAX77675_MAX_REGISTER 0x10 199 200 /* Common minimum voltage (in microvolts) */ 201 #define MAX77675_MIN_UV 500000 // 500 mV 202 203 /* Voltage step configuration for 25mV mode */ 204 #define MAX77675_STEP_25MV 25000 // Step size: 25 mV 205 #define MAX77675_MAX_UV_25MV 5500000 // Max voltage: 5.5 V 206 #define MAX77675_NUM_LEVELS_25MV 201 // levels = (5500mV - 500mV) / 25mV + 1 207 208 /* Voltage step configuration for 12.5mV mode */ 209 #define MAX77675_STEP_12_5MV 12500 // Step size: 12.5 mV 210 #define MAX77675_MAX_UV_12_5MV 3687500 // Max voltage: 3.6875 V 211 #define MAX77675_NUM_LEVELS_12_5MV 255 // levels = (3687.5mV - 500mV) / 12.5mV + 1 212 213 #define MAX77675_ENABLE_OFF 0x04 214 #define MAX77675_ENABLE_ON 0x06 215 216 #define MAX77675_REGULATOR_AD_OFF 0x00 217 #define MAX77675_REGULATOR_AD_ON BIT(3) 218 219 /* FPS source */ 220 #define MAX77675_FPS_SLOT_0 0x0 221 #define MAX77675_FPS_SLOT_1 0x1 222 #define MAX77675_FPS_SLOT_2 0x2 223 #define MAX77675_FPS_SLOT_3 0x3 224 #define MAX77675_FPS_DEF 0x4 225 226 /* nEN Manual Reset Time Configuration (MRT) */ 227 #define MAX77675_MRT_4S 0x0 228 #define MAX77675_MRT_8S 0x1 229 #define MAX77675_MRT_12S 0x2 230 #define MAX77675_MRT_16S 0x3 231 232 /* nEN Mode Configuration */ 233 #define MAX77675_EN_PUSH_BUTTON 0x0 234 #define MAX77675_EN_SLIDE_SWITCH 0x1 235 #define MAX77675_EN_LOGIC 0x2 236 237 /* Debounce Timer Enable (DBEN_nEN) */ 238 #define MAX77675_DBEN_100US 0x0 239 #define MAX77675_DBEN_30000US 0x1 240 241 /* Rising slew rate control for SBB0 when ramping up */ 242 #define MAX77675_SR_2MV_PER_US 0x0 // 2 mV/us 243 #define MAX77675_SR_USE_DVS 0x1 // Use DVS slew rate setting (adi,dvs-slew-rate) 244 245 /* Latency Mode */ 246 #define MAX77675_HIGH_LATENCY_MODE 0x0 // High latency, low quiescent current (~100us) 247 #define MAX77675_LOW_LATENCY_MODE 0x1 // Low latency, high quiescent current (~10us) 248 249 /* Dynamic Voltage Scaling (DVS) Slew Rate */ 250 #define MAX77675_DVS_SLEW_5MV_PER_US 0x0 // 5 mV/us 251 #define MAX77675_DVS_SLEW_10MV_PER_US 0x1 // 10 mV/us 252 253 /* SIMO Buck-Boost Drive Strength (All Channels) */ 254 #define MAX77675_DRV_SBB_STRENGTH_MAX 0x0 // Maximum drive strength (~0.6 ns transition time) 255 #define MAX77675_DRV_SBB_STRENGTH_HIGH 0x1 // High drive strength (~1.2 ns transition time) 256 #define MAX77675_DRV_SBB_STRENGTH_LOW 0x2 // Low drive strength (~1.8 ns transition time) 257 #define MAX77675_DRV_SBB_STRENGTH_MIN 0x3 // Minimum drive strength (~8 ns transition time) 258 259 /* Regulator ID enumeration */ 260 enum max77675_regulator_id { 261 MAX77675_ID_SBB0 = 0, 262 MAX77675_ID_SBB1, 263 MAX77675_ID_SBB2, 264 MAX77675_ID_SBB3, 265 MAX77675_ID_NUM_MAX, 266 }; 267 268 struct max77675_regulator_sbb_setting { 269 u8 fps_slot; 270 bool fixed_slew_rate; 271 }; 272 273 struct max77675_config { 274 u8 en_mode; 275 u8 voltage_change_latency; 276 u8 drv_sbb_strength; 277 u8 dvs_slew_rate; 278 u8 debounce_time; 279 u8 manual_reset_time; 280 bool en_pullup_disable; 281 bool bias_low_power_request; 282 bool simo_ldo_always_on; 283 }; 284 285 struct max77675_regulator { 286 struct device *dev; 287 struct regmap *regmap; 288 struct max77675_config config; 289 struct max77675_regulator_sbb_setting sbb_setting[MAX77675_ID_NUM_MAX]; 290 }; 291 292 static int max77675_regulator_get_fps_src(struct max77675_regulator *maxreg, int id) 293 { 294 unsigned int reg_addr; 295 unsigned int val; 296 int ret; 297 298 switch (id) { 299 case MAX77675_ID_SBB0: 300 reg_addr = MAX77675_REG_CNFG_SBB0_B; 301 break; 302 case MAX77675_ID_SBB1: 303 reg_addr = MAX77675_REG_CNFG_SBB1_B; 304 break; 305 case MAX77675_ID_SBB2: 306 reg_addr = MAX77675_REG_CNFG_SBB2_B; 307 break; 308 case MAX77675_ID_SBB3: 309 reg_addr = MAX77675_REG_CNFG_SBB3_B; 310 break; 311 default: 312 dev_err(maxreg->dev, "Invalid regulator id: %d\n", id); 313 return -EINVAL; 314 } 315 316 ret = regmap_read(maxreg->regmap, reg_addr, &val); 317 if (ret < 0) { 318 dev_err(maxreg->dev, "Failed to read FPS source (reg 0x%02x): %d\n", 319 reg_addr, ret); 320 return ret; 321 } 322 323 return FIELD_GET(MAX77675_EN_SBB_MASK, val); 324 } 325 326 static int max77675_regulator_set_fps_src(struct max77675_regulator *maxreg, int id, u8 fps_src) 327 { 328 unsigned int reg_addr; 329 330 switch (id) { 331 case MAX77675_ID_SBB0: 332 reg_addr = MAX77675_REG_CNFG_SBB0_B; 333 break; 334 case MAX77675_ID_SBB1: 335 reg_addr = MAX77675_REG_CNFG_SBB1_B; 336 break; 337 case MAX77675_ID_SBB2: 338 reg_addr = MAX77675_REG_CNFG_SBB2_B; 339 break; 340 case MAX77675_ID_SBB3: 341 reg_addr = MAX77675_REG_CNFG_SBB3_B; 342 break; 343 default: 344 dev_err(maxreg->dev, "Invalid regulator id: %d\n", id); 345 return -EINVAL; 346 } 347 348 return regmap_update_bits(maxreg->regmap, reg_addr, MAX77675_EN_SBB_MASK, fps_src); 349 } 350 351 static int max77675_set_sbb_slew_rate_fixed(struct max77675_regulator *maxreg, int id, bool fixed) 352 { 353 u8 mask, value; 354 u8 slew_src_ctrl_bit = fixed ? 0 : 1; 355 356 switch (id) { 357 case MAX77675_ID_SBB0: 358 mask = MAX77675_SR_SBB0_BIT; 359 value = FIELD_PREP(MAX77675_SR_SBB0_BIT, slew_src_ctrl_bit); 360 break; 361 362 case MAX77675_ID_SBB1: 363 mask = MAX77675_SR_SBB1_BIT; 364 value = FIELD_PREP(MAX77675_SR_SBB1_BIT, slew_src_ctrl_bit); 365 break; 366 367 case MAX77675_ID_SBB2: 368 mask = MAX77675_SR_SBB2_BIT; 369 value = FIELD_PREP(MAX77675_SR_SBB2_BIT, slew_src_ctrl_bit); 370 break; 371 372 case MAX77675_ID_SBB3: 373 mask = MAX77675_SR_SBB3_BIT; 374 value = FIELD_PREP(MAX77675_SR_SBB3_BIT, slew_src_ctrl_bit); 375 break; 376 377 default: 378 return -EINVAL; 379 } 380 381 return regmap_update_bits(maxreg->regmap, MAX77675_REG_CNFG_SBB_TOP_B, mask, value); 382 } 383 384 static int max77675_init_regulator(struct max77675_regulator *maxreg, int id) 385 { 386 struct max77675_regulator_sbb_setting *sbb_setting = &maxreg->sbb_setting[id]; 387 int ret; 388 389 if (sbb_setting->fps_slot == MAX77675_FPS_DEF) { 390 ret = max77675_regulator_get_fps_src(maxreg, id); 391 if (ret < 0) 392 return ret; 393 394 sbb_setting->fps_slot = ret; 395 } else { 396 ret = max77675_regulator_set_fps_src(maxreg, id, sbb_setting->fps_slot); 397 if (ret < 0) 398 return ret; 399 } 400 401 ret = max77675_set_sbb_slew_rate_fixed(maxreg, id, sbb_setting->fixed_slew_rate); 402 if (ret < 0) 403 return ret; 404 405 return 0; 406 } 407 408 static int max77675_of_parse_cb(struct device_node *np, 409 const struct regulator_desc *desc, 410 struct regulator_config *config) 411 { 412 struct max77675_regulator *maxreg = config->driver_data; 413 struct max77675_regulator_sbb_setting *sbb_setting = &maxreg->sbb_setting[desc->id]; 414 static const char * const fps_slots[] = { "slot0", "slot1", "slot2", "slot3", "default" }; 415 const char *fps_str; 416 int slot; 417 418 /* Parse FPS slot from DT */ 419 if (of_property_read_string(np, "adi,fps-slot", &fps_str)) { 420 /* Property not set, use default */ 421 sbb_setting->fps_slot = MAX77675_FPS_DEF; 422 } else { 423 /* Match string to index */ 424 slot = match_string(fps_slots, ARRAY_SIZE(fps_slots), fps_str); 425 if (slot < 0) { 426 dev_dbg(maxreg->dev, "Invalid fps-slot '%s', using default\n", fps_str); 427 sbb_setting->fps_slot = MAX77675_FPS_DEF; 428 } else { 429 sbb_setting->fps_slot = slot; 430 } 431 } 432 433 /* Parse slew rate control source */ 434 sbb_setting->fixed_slew_rate = of_property_read_bool(np, "adi,fixed-slew-rate"); 435 436 /* Apply parsed configuration */ 437 return max77675_init_regulator(maxreg, desc->id); 438 } 439 440 static int max77675_get_error_flags(struct regulator_dev *rdev, unsigned int *flags) 441 { 442 struct max77675_regulator *maxreg = rdev_get_drvdata(rdev); 443 unsigned int int_flags; 444 int id = rdev_get_id(rdev); 445 int ret; 446 447 ret = regmap_read(maxreg->regmap, MAX77675_REG_INT_GLBL, &int_flags); 448 if (ret) { 449 dev_err(maxreg->dev, "Failed to read INT_GLBL: %d\n", ret); 450 return ret; 451 } 452 453 *flags = 0; 454 455 switch (id) { 456 case MAX77675_ID_SBB0: 457 if (int_flags & MAX77675_INT_SBB0_F_BIT) 458 *flags |= REGULATOR_ERROR_FAIL; 459 break; 460 case MAX77675_ID_SBB1: 461 if (int_flags & MAX77675_INT_SBB1_F_BIT) 462 *flags |= REGULATOR_ERROR_FAIL; 463 break; 464 case MAX77675_ID_SBB2: 465 if (int_flags & MAX77675_INT_SBB2_F_BIT) 466 *flags |= REGULATOR_ERROR_FAIL; 467 break; 468 case MAX77675_ID_SBB3: 469 if (int_flags & MAX77675_INT_SBB3_F_BIT) 470 *flags |= REGULATOR_ERROR_FAIL; 471 break; 472 default: 473 dev_warn(maxreg->dev, "Unsupported regulator ID: %d\n", id); 474 break; 475 } 476 477 if (int_flags & MAX77675_INT_TJAL2_R_BIT) { 478 /* TJAL2 interrupt: Over-temperature condition (above 120 degree) */ 479 *flags |= REGULATOR_ERROR_OVER_TEMP; 480 } 481 482 return 0; 483 } 484 485 static const struct regulator_ops max77675_regulator_ops = { 486 .list_voltage = regulator_list_voltage_linear, 487 .enable = regulator_enable_regmap, 488 .disable = regulator_disable_regmap, 489 .is_enabled = regulator_is_enabled_regmap, 490 .map_voltage = regulator_map_voltage_linear, 491 .set_voltage_sel = regulator_set_voltage_sel_regmap, 492 .get_voltage_sel = regulator_get_voltage_sel_regmap, 493 .set_active_discharge = regulator_set_active_discharge_regmap, 494 .get_error_flags = max77675_get_error_flags, 495 }; 496 497 static struct regulator_desc max77675_regulators[MAX77675_ID_NUM_MAX] = { 498 { 499 .name = "sbb0", 500 .of_match = of_match_ptr("sbb0"), 501 .regulators_node = of_match_ptr("regulators"), 502 .of_parse_cb = max77675_of_parse_cb, 503 .id = MAX77675_ID_SBB0, 504 .ops = &max77675_regulator_ops, 505 .type = REGULATOR_VOLTAGE, 506 .owner = THIS_MODULE, 507 .n_voltages = MAX77675_NUM_LEVELS_25MV, 508 .min_uV = MAX77675_MIN_UV, 509 .uV_step = MAX77675_STEP_25MV, 510 .vsel_reg = MAX77675_REG_CNFG_SBB0_A, 511 .vsel_mask = MAX77675_TV_SBB0_MASK, 512 .enable_reg = MAX77675_REG_CNFG_SBB0_B, 513 .enable_mask = MAX77675_EN_SBB0_MASK, 514 .enable_val = MAX77675_ENABLE_ON, 515 .disable_val = MAX77675_ENABLE_OFF, 516 .active_discharge_off = MAX77675_REGULATOR_AD_OFF, 517 .active_discharge_on = MAX77675_REGULATOR_AD_ON, 518 .active_discharge_mask = MAX77675_ADE_SBB0_BIT, 519 .active_discharge_reg = MAX77675_REG_CNFG_SBB0_B, 520 }, 521 { 522 .name = "sbb1", 523 .of_match = of_match_ptr("sbb1"), 524 .regulators_node = of_match_ptr("regulators"), 525 .of_parse_cb = max77675_of_parse_cb, 526 .id = MAX77675_ID_SBB1, 527 .ops = &max77675_regulator_ops, 528 .type = REGULATOR_VOLTAGE, 529 .owner = THIS_MODULE, 530 .n_voltages = MAX77675_NUM_LEVELS_25MV, 531 .min_uV = MAX77675_MIN_UV, 532 .uV_step = MAX77675_STEP_25MV, 533 .vsel_reg = MAX77675_REG_CNFG_SBB1_A, 534 .vsel_mask = MAX77675_TV_SBB1_MASK, 535 .enable_reg = MAX77675_REG_CNFG_SBB1_B, 536 .enable_mask = MAX77675_EN_SBB1_MASK, 537 .enable_val = MAX77675_ENABLE_ON, 538 .disable_val = MAX77675_ENABLE_OFF, 539 .active_discharge_off = MAX77675_REGULATOR_AD_OFF, 540 .active_discharge_on = MAX77675_REGULATOR_AD_ON, 541 .active_discharge_mask = MAX77675_ADE_SBB1_BIT, 542 .active_discharge_reg = MAX77675_REG_CNFG_SBB1_B, 543 }, 544 { 545 .name = "sbb2", 546 .of_match = of_match_ptr("sbb2"), 547 .regulators_node = of_match_ptr("regulators"), 548 .of_parse_cb = max77675_of_parse_cb, 549 .id = MAX77675_ID_SBB2, 550 .ops = &max77675_regulator_ops, 551 .type = REGULATOR_VOLTAGE, 552 .owner = THIS_MODULE, 553 .n_voltages = MAX77675_NUM_LEVELS_25MV, 554 .min_uV = MAX77675_MIN_UV, 555 .uV_step = MAX77675_STEP_25MV, 556 .vsel_reg = MAX77675_REG_CNFG_SBB2_A, 557 .vsel_mask = MAX77675_TV_SBB2_MASK, 558 .enable_reg = MAX77675_REG_CNFG_SBB2_B, 559 .enable_mask = MAX77675_EN_SBB2_MASK, 560 .enable_val = MAX77675_ENABLE_ON, 561 .disable_val = MAX77675_ENABLE_OFF, 562 .active_discharge_off = MAX77675_REGULATOR_AD_OFF, 563 .active_discharge_on = MAX77675_REGULATOR_AD_ON, 564 .active_discharge_mask = MAX77675_ADE_SBB2_BIT, 565 .active_discharge_reg = MAX77675_REG_CNFG_SBB2_B, 566 }, 567 { 568 .name = "sbb3", 569 .of_match = of_match_ptr("sbb3"), 570 .regulators_node = of_match_ptr("regulators"), 571 .of_parse_cb = max77675_of_parse_cb, 572 .id = MAX77675_ID_SBB3, 573 .ops = &max77675_regulator_ops, 574 .type = REGULATOR_VOLTAGE, 575 .owner = THIS_MODULE, 576 .n_voltages = MAX77675_NUM_LEVELS_25MV, 577 .min_uV = MAX77675_MIN_UV, 578 .uV_step = MAX77675_STEP_25MV, 579 .vsel_reg = MAX77675_REG_CNFG_SBB3_A, 580 .vsel_mask = MAX77675_TV_SBB3_MASK, 581 .enable_reg = MAX77675_REG_CNFG_SBB3_B, 582 .enable_mask = MAX77675_EN_SBB3_MASK, 583 .enable_val = MAX77675_ENABLE_ON, 584 .disable_val = MAX77675_ENABLE_OFF, 585 .active_discharge_off = MAX77675_REGULATOR_AD_OFF, 586 .active_discharge_on = MAX77675_REGULATOR_AD_ON, 587 .active_discharge_mask = MAX77675_ADE_SBB3_BIT, 588 .active_discharge_reg = MAX77675_REG_CNFG_SBB3_B, 589 }, 590 }; 591 592 static bool max77675_volatile_reg(struct device *dev, unsigned int reg) 593 { 594 switch (reg) { 595 case MAX77675_REG_CNFG_GLBL_B: 596 /* This register can be updated by an internal state machine */ 597 case MAX77675_REG_INT_GLBL: 598 case MAX77675_REG_STAT_GLBL: 599 case MAX77675_REG_ERCF_GLBL: 600 return true; 601 default: 602 return false; 603 } 604 } 605 606 static const struct regmap_config max77675_regmap_config = { 607 .reg_bits = 8, 608 .val_bits = 8, 609 .max_register = MAX77675_MAX_REGISTER, 610 .cache_type = REGCACHE_MAPLE, 611 .volatile_reg = max77675_volatile_reg, 612 }; 613 614 static int max77675_apply_config(struct max77675_regulator *maxreg) 615 { 616 const struct max77675_config *cfg = &maxreg->config; 617 int ret; 618 619 /* Set EN pin mode */ 620 ret = regmap_update_bits(maxreg->regmap, MAX77675_REG_CNFG_GLBL_A, 621 MAX77675_EN_MODE_MASK, 622 FIELD_PREP(MAX77675_EN_MODE_MASK, cfg->en_mode)); 623 if (ret) { 624 dev_err(maxreg->dev, "Failed to set EN mode: %d\n", ret); 625 return ret; 626 } 627 628 /* Set the latency between output voltage change and SBBx voltage ramp start */ 629 ret = regmap_update_bits(maxreg->regmap, MAX77675_REG_CNFG_SBB_TOP_B, 630 MAX77675_LAT_MODE_BIT, 631 FIELD_PREP(MAX77675_LAT_MODE_BIT, cfg->voltage_change_latency)); 632 if (ret) { 633 dev_err(maxreg->dev, "Failed to set latency mode: %d\n", ret); 634 return ret; 635 } 636 637 /* Set drive strength */ 638 ret = regmap_update_bits(maxreg->regmap, MAX77675_REG_CNFG_SBB_TOP_A, 639 MAX77675_DRV_SBB_MASK, 640 FIELD_PREP(MAX77675_DRV_SBB_MASK, cfg->drv_sbb_strength)); 641 if (ret) { 642 dev_err(maxreg->dev, "Failed to set drive strength: %d\n", ret); 643 return ret; 644 } 645 646 /* Set DVS slew rate */ 647 ret = regmap_update_bits(maxreg->regmap, MAX77675_REG_CNFG_SBB_TOP_B, 648 MAX77675_DVS_SLEW_BIT, 649 FIELD_PREP(MAX77675_DVS_SLEW_BIT, cfg->dvs_slew_rate)); 650 if (ret) { 651 dev_err(maxreg->dev, "Failed to set DVS slew rate: %d\n", ret); 652 return ret; 653 } 654 655 /* Set debounce time for EN pin */ 656 ret = regmap_update_bits(maxreg->regmap, MAX77675_REG_CNFG_GLBL_A, 657 MAX77675_DBEN_EN_BIT, 658 FIELD_PREP(MAX77675_DBEN_EN_BIT, cfg->debounce_time)); 659 if (ret) { 660 dev_err(maxreg->dev, "Failed to set EN debounce time: %d\n", ret); 661 return ret; 662 } 663 664 /* Set manual reset time (MRT) for EN pin */ 665 ret = regmap_update_bits(maxreg->regmap, MAX77675_REG_CNFG_GLBL_A, 666 MAX77675_MRT_MASK, 667 FIELD_PREP(MAX77675_MRT_MASK, cfg->manual_reset_time)); 668 if (ret) { 669 dev_err(maxreg->dev, "Failed to set manual reset time: %d\n", ret); 670 return ret; 671 } 672 673 /* Enable or disable internal pull-up resistor on EN pin */ 674 ret = regmap_update_bits(maxreg->regmap, MAX77675_REG_CNFG_GLBL_A, 675 MAX77675_PU_DIS_BIT, 676 FIELD_PREP(MAX77675_PU_DIS_BIT, cfg->en_pullup_disable)); 677 if (ret) { 678 dev_err(maxreg->dev, "Failed to set EN pull-up disable: %d\n", ret); 679 return ret; 680 } 681 682 /* Request main bias to enter low-power mode */ 683 ret = regmap_update_bits(maxreg->regmap, MAX77675_REG_CNFG_GLBL_A, 684 MAX77675_BIAS_LPM_BIT, 685 FIELD_PREP(MAX77675_BIAS_LPM_BIT, cfg->bias_low_power_request)); 686 if (ret) { 687 dev_err(maxreg->dev, "Failed to set bias low-power request: %d\n", ret); 688 return ret; 689 } 690 691 /* Force SIMO internal LDO to always supply 1.8V */ 692 ret = regmap_update_bits(maxreg->regmap, MAX77675_REG_CNFG_GLBL_A, 693 MAX77675_SIMO_CH_DIS_BIT, 694 FIELD_PREP(MAX77675_SIMO_CH_DIS_BIT, cfg->simo_ldo_always_on)); 695 if (ret) { 696 dev_err(maxreg->dev, "Failed to set SIMO internal LDO always-on: %d\n", ret); 697 return ret; 698 } 699 700 return 0; 701 } 702 703 static int max77675_parse_en_mode(struct device *dev, 704 struct device_node *np, 705 u8 *en_mode) 706 { 707 static const char * const en_modes[] = {"push-button", "slide-switch", "logic"}; 708 const char *str; 709 int index; 710 711 *en_mode = MAX77675_EN_SLIDE_SWITCH; 712 713 if (of_property_read_string(np, "adi,en-mode", &str)) 714 return 0; 715 716 index = match_string(en_modes, ARRAY_SIZE(en_modes), str); 717 if (index < 0) { 718 dev_err(dev, "Invalid 'adi,en-mode' value '%s'\n", str); 719 return -EINVAL; 720 } 721 722 *en_mode = index; 723 724 return 0; 725 } 726 727 static int max77675_parse_voltage_change_latency(struct device *dev, 728 struct device_node *np, 729 u8 *latency_mode) 730 { 731 u32 val; 732 733 *latency_mode = MAX77675_HIGH_LATENCY_MODE; 734 735 if (!of_property_read_u32(np, "adi,voltage-change-latency-us", &val)) { 736 switch (val) { 737 case 10: 738 *latency_mode = MAX77675_LOW_LATENCY_MODE; 739 break; 740 case 100: 741 *latency_mode = MAX77675_HIGH_LATENCY_MODE; 742 break; 743 default: 744 dev_err(dev, "Invalid voltage-change-latency-us value: %u\n", val); 745 return -EINVAL; 746 } 747 } 748 749 return 0; 750 } 751 752 static int max77675_parse_manual_reset_time(struct device *dev, 753 struct device_node *np, 754 u8 *reset_time) 755 { 756 u32 val; 757 758 *reset_time = MAX77675_MRT_4S; 759 760 if (!of_property_read_u32(np, "reset-time-sec", &val)) { 761 switch (val) { 762 case 4: 763 *reset_time = MAX77675_MRT_4S; 764 break; 765 case 8: 766 *reset_time = MAX77675_MRT_8S; 767 break; 768 case 12: 769 *reset_time = MAX77675_MRT_12S; 770 break; 771 case 16: 772 *reset_time = MAX77675_MRT_16S; 773 break; 774 default: 775 dev_err(dev, "Invalid reset-time-sec value: %u\n", val); 776 return -EINVAL; 777 } 778 } 779 780 return 0; 781 } 782 783 static int max77675_parse_dvs_slew_rate(struct device *dev, struct device_node *np, u8 *slew_rate) 784 { 785 u32 val; 786 787 /* Set default: 5 mV/us */ 788 *slew_rate = MAX77675_DVS_SLEW_5MV_PER_US; 789 790 if (!of_property_read_u32(np, "adi,dvs-slew-rate-mv-per-us", &val)) { 791 switch (val) { 792 case 5: 793 *slew_rate = MAX77675_DVS_SLEW_5MV_PER_US; 794 break; 795 case 10: 796 *slew_rate = MAX77675_DVS_SLEW_10MV_PER_US; 797 break; 798 default: 799 dev_err(dev, "Invalid dvs-slew-rate-mv-per-us value: %u\n", val); 800 return -EINVAL; 801 } 802 } 803 804 return 0; 805 } 806 807 static int max77675_parse_drv_sbb_strength(struct device *dev, struct device_node *np, u8 *strength) 808 { 809 static const char * const strength_names[] = {"max", "high", "low", "min"}; 810 const char *str; 811 int index; 812 813 /* Set default: maximum drive strength */ 814 *strength = MAX77675_DRV_SBB_STRENGTH_MAX; 815 816 if (of_property_read_string(np, "adi,drv-sbb-strength", &str)) 817 return 0; 818 819 index = match_string(strength_names, ARRAY_SIZE(strength_names), str); 820 if (index < 0) { 821 dev_err(dev, "Invalid 'adi,drv-sbb-strength' value: '%s'\n", str); 822 return -EINVAL; 823 } 824 825 *strength = index; 826 827 return 0; 828 } 829 830 static int max77675_parse_debounce_time_us(struct device *dev, 831 struct device_node *np, 832 u8 *debounce_time) 833 { 834 u32 val; 835 836 *debounce_time = MAX77675_DBEN_100US; 837 838 if (!of_property_read_u32(np, "input-debounce", &val)) { 839 switch (val) { 840 case 100: 841 *debounce_time = MAX77675_DBEN_100US; 842 break; 843 case 30000: 844 *debounce_time = MAX77675_DBEN_30000US; 845 break; 846 default: 847 dev_err(dev, "Invalid input-debounce value: %u\n", val); 848 return -EINVAL; 849 } 850 } 851 852 return 0; 853 } 854 855 static int max77675_parse_config(struct max77675_regulator *maxreg) 856 { 857 struct device_node *np = maxreg->dev->of_node; 858 struct max77675_config *cfg = &maxreg->config; 859 int ret; 860 861 /* EN pin mode */ 862 ret = max77675_parse_en_mode(maxreg->dev, np, &cfg->en_mode); 863 if (ret < 0) 864 return ret; 865 866 /* voltage change latency */ 867 ret = max77675_parse_voltage_change_latency(maxreg->dev, np, &cfg->voltage_change_latency); 868 if (ret < 0) 869 return ret; 870 871 /* drive strength */ 872 ret = max77675_parse_drv_sbb_strength(maxreg->dev, np, &cfg->drv_sbb_strength); 873 if (ret < 0) 874 return ret; 875 876 /* dvs slew rate */ 877 ret = max77675_parse_dvs_slew_rate(maxreg->dev, np, &cfg->dvs_slew_rate); 878 if (ret < 0) 879 return ret; 880 881 /* Debounce time for EN pin */ 882 ret = max77675_parse_debounce_time_us(maxreg->dev, np, &cfg->debounce_time); 883 if (ret < 0) 884 return ret; 885 886 /* Manual reset time for EN pin */ 887 ret = max77675_parse_manual_reset_time(maxreg->dev, np, &cfg->manual_reset_time); 888 if (ret < 0) 889 return ret; 890 891 /* Disable internal pull-up resistor on EN pin */ 892 cfg->en_pullup_disable = of_property_read_bool(np, "bias-disable"); 893 894 /* Request low-power mode for main bias */ 895 cfg->bias_low_power_request = of_property_read_bool(np, "adi,bias-low-power-request"); 896 897 /* Force internal LDO to always supply 1.8V */ 898 cfg->simo_ldo_always_on = of_property_read_bool(np, "adi,simo-ldo-always-on"); 899 900 return ret; 901 } 902 903 static int max77675_init_event(struct max77675_regulator *maxreg) 904 { 905 unsigned int ercflag, int_glbl; 906 int ret; 907 908 ret = regmap_read(maxreg->regmap, MAX77675_REG_ERCF_GLBL, &ercflag); 909 if (ret) { 910 dev_err(maxreg->dev, "Failed to read CID register: %d\n", ret); 911 return ret; 912 } 913 914 ret = regmap_read(maxreg->regmap, MAX77675_REG_INT_GLBL, &int_glbl); 915 if (ret) { 916 dev_err(maxreg->dev, "Failed to read INT_GLBL register: %d\n", ret); 917 return ret; 918 } 919 920 if (ercflag & MAX77675_SFT_CRST_F_BIT) 921 dev_dbg(maxreg->dev, "Software Cold Reset Flag is set\n"); 922 923 if (ercflag & MAX77675_SFT_OFF_F_BIT) 924 dev_dbg(maxreg->dev, "Software Off Flag is set\n"); 925 926 if (ercflag & MAX77675_MRST_BIT) 927 dev_dbg(maxreg->dev, "Manual Reset Timer Flag is set\n"); 928 929 if (ercflag & MAX77675_UVLO_BIT) 930 dev_dbg(maxreg->dev, "Undervoltage Lockout Flag is set\n"); 931 932 if (ercflag & MAX77675_OVLO_BIT) 933 dev_dbg(maxreg->dev, "Overvoltage Lockout Flag is set\n"); 934 935 if (ercflag & MAX77675_TOVLD_BIT) 936 dev_dbg(maxreg->dev, "Thermal Overload Flag is set\n"); 937 938 if (int_glbl & MAX77675_INT_SBB3_F_BIT) 939 dev_dbg(maxreg->dev, "SBB3 Channel Fault Interrupt occurred\n"); 940 941 if (int_glbl & MAX77675_INT_SBB2_F_BIT) 942 dev_dbg(maxreg->dev, "SBB2 Channel Fault Interrupt occurred\n"); 943 944 if (int_glbl & MAX77675_INT_SBB1_F_BIT) 945 dev_dbg(maxreg->dev, "SBB1 Channel Fault Interrupt occurred\n"); 946 947 if (int_glbl & MAX77675_INT_SBB0_F_BIT) 948 dev_dbg(maxreg->dev, "SBB0 Channel Fault Interrupt occurred\n"); 949 950 if (int_glbl & MAX77675_INT_TJAL2_R_BIT) 951 dev_dbg(maxreg->dev, "Thermal Alarm 2 Rising Interrupt occurred\n"); 952 953 if (int_glbl & MAX77675_INT_TJAL1_R_BIT) 954 dev_dbg(maxreg->dev, "Thermal Alarm 1 Rising Interrupt occurred\n"); 955 956 if (int_glbl & MAX77675_INT_EN_R_BIT) 957 dev_dbg(maxreg->dev, "nEN Rising Edge Interrupt occurred\n"); 958 959 if (int_glbl & MAX77675_INT_EN_F_BIT) 960 dev_dbg(maxreg->dev, "nEN Falling Edge Interrupt occurred\n"); 961 962 return 0; 963 } 964 965 static int max77675_regulator_probe(struct i2c_client *client) 966 { 967 struct max77675_regulator *maxreg; 968 struct regulator_config config = {}; 969 int i, ret; 970 971 maxreg = devm_kzalloc(&client->dev, sizeof(*maxreg), GFP_KERNEL); 972 if (!maxreg) 973 return -ENOMEM; 974 975 maxreg->dev = &client->dev; 976 977 maxreg->regmap = devm_regmap_init_i2c(client, &max77675_regmap_config); 978 if (IS_ERR(maxreg->regmap)) 979 return dev_err_probe(maxreg->dev, 980 PTR_ERR(maxreg->regmap), 981 "Failed to init regmap\n"); 982 983 ret = max77675_init_event(maxreg); 984 if (ret < 0) 985 return dev_err_probe(maxreg->dev, ret, "Failed to init event\n"); 986 987 ret = max77675_parse_config(maxreg); 988 if (ret < 0) 989 return dev_err_probe(maxreg->dev, ret, "Failed to parse config\n"); 990 991 ret = max77675_apply_config(maxreg); 992 if (ret < 0) 993 return dev_err_probe(maxreg->dev, ret, "Failed to apply config\n"); 994 995 config.dev = &client->dev; 996 config.regmap = maxreg->regmap; 997 config.driver_data = maxreg; 998 999 struct device_node *regulators_np __free(device_node) = 1000 of_get_child_by_name(client->dev.of_node, "regulators"); 1001 if (!regulators_np) { 1002 dev_err(maxreg->dev, "No 'regulators' subnode found in DT\n"); 1003 return -EINVAL; 1004 } 1005 1006 for (i = 0; i < MAX77675_ID_NUM_MAX; i++) { 1007 const struct regulator_desc *desc = &max77675_regulators[i]; 1008 struct regulator_dev *rdev; 1009 1010 struct device_node *child_np __free(device_node) = 1011 of_get_child_by_name(regulators_np, desc->name); 1012 if (!child_np) { 1013 dev_warn(maxreg->dev, "No DT node for regulator %s\n", desc->name); 1014 continue; 1015 } 1016 1017 config.of_node = child_np; 1018 1019 rdev = devm_regulator_register(&client->dev, desc, &config); 1020 if (IS_ERR(rdev)) { 1021 return dev_err_probe(maxreg->dev, PTR_ERR(rdev), 1022 "Failed to register regulator %d (%s)\n", 1023 i, desc->name); 1024 } 1025 } 1026 1027 return 0; 1028 } 1029 1030 static const struct i2c_device_id max77675_i2c_id[] = { 1031 { "max77675", 0 }, 1032 { } 1033 }; 1034 MODULE_DEVICE_TABLE(i2c, max77675_i2c_id); 1035 1036 static const struct of_device_id __maybe_unused max77675_of_match[] = { 1037 { .compatible = "adi,max77675", }, 1038 { } 1039 }; 1040 MODULE_DEVICE_TABLE(of, max77675_of_match); 1041 1042 static struct i2c_driver max77675_regulator_driver = { 1043 .driver = { 1044 .name = "max77675", 1045 .of_match_table = of_match_ptr(max77675_of_match), 1046 }, 1047 .probe = max77675_regulator_probe, 1048 .id_table = max77675_i2c_id, 1049 }; 1050 1051 module_i2c_driver(max77675_regulator_driver); 1052 1053 MODULE_DESCRIPTION("MAX77675 Regulator Driver"); 1054 MODULE_AUTHOR("Joan Na <joan.na@analog.com>"); 1055 MODULE_LICENSE("GPL"); 1056