1 /* 2 * AXP20x regulators driver. 3 * 4 * Copyright (C) 2013 Carlo Caione <carlo@caione.org> 5 * 6 * This file is subject to the terms and conditions of the GNU General 7 * Public License. See the file "COPYING" in the main directory of this 8 * archive for more details. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/mfd/axp20x.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 #include <linux/regulator/driver.h> 26 #include <linux/regulator/machine.h> 27 #include <linux/regulator/of_regulator.h> 28 29 #define AXP20X_GPIO0_FUNC_MASK GENMASK(3, 0) 30 #define AXP20X_GPIO1_FUNC_MASK GENMASK(3, 0) 31 32 #define AXP20X_IO_ENABLED 0x03 33 #define AXP20X_IO_DISABLED 0x07 34 35 #define AXP20X_WORKMODE_DCDC2_MASK BIT_MASK(2) 36 #define AXP20X_WORKMODE_DCDC3_MASK BIT_MASK(1) 37 38 #define AXP20X_FREQ_DCDC_MASK GENMASK(3, 0) 39 40 #define AXP20X_VBUS_IPSOUT_MGMT_MASK BIT_MASK(2) 41 42 #define AXP20X_DCDC2_V_OUT_MASK GENMASK(5, 0) 43 #define AXP20X_DCDC3_V_OUT_MASK GENMASK(7, 0) 44 #define AXP20X_LDO2_V_OUT_MASK GENMASK(7, 4) 45 #define AXP20X_LDO3_V_OUT_MASK GENMASK(6, 0) 46 #define AXP20X_LDO4_V_OUT_MASK GENMASK(3, 0) 47 #define AXP20X_LDO5_V_OUT_MASK GENMASK(7, 4) 48 49 #define AXP20X_PWR_OUT_EXTEN_MASK BIT_MASK(0) 50 #define AXP20X_PWR_OUT_DCDC3_MASK BIT_MASK(1) 51 #define AXP20X_PWR_OUT_LDO2_MASK BIT_MASK(2) 52 #define AXP20X_PWR_OUT_LDO4_MASK BIT_MASK(3) 53 #define AXP20X_PWR_OUT_DCDC2_MASK BIT_MASK(4) 54 #define AXP20X_PWR_OUT_LDO3_MASK BIT_MASK(6) 55 56 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK BIT_MASK(0) 57 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \ 58 ((x) << 0) 59 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK BIT_MASK(1) 60 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \ 61 ((x) << 1) 62 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK BIT_MASK(2) 63 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN BIT(2) 64 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK BIT_MASK(3) 65 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN BIT(3) 66 67 #define AXP20X_LDO4_V_OUT_1250mV_START 0x0 68 #define AXP20X_LDO4_V_OUT_1250mV_STEPS 0 69 #define AXP20X_LDO4_V_OUT_1250mV_END \ 70 (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS) 71 #define AXP20X_LDO4_V_OUT_1300mV_START 0x1 72 #define AXP20X_LDO4_V_OUT_1300mV_STEPS 7 73 #define AXP20X_LDO4_V_OUT_1300mV_END \ 74 (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS) 75 #define AXP20X_LDO4_V_OUT_2500mV_START 0x9 76 #define AXP20X_LDO4_V_OUT_2500mV_STEPS 0 77 #define AXP20X_LDO4_V_OUT_2500mV_END \ 78 (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS) 79 #define AXP20X_LDO4_V_OUT_2700mV_START 0xa 80 #define AXP20X_LDO4_V_OUT_2700mV_STEPS 1 81 #define AXP20X_LDO4_V_OUT_2700mV_END \ 82 (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS) 83 #define AXP20X_LDO4_V_OUT_3000mV_START 0xc 84 #define AXP20X_LDO4_V_OUT_3000mV_STEPS 3 85 #define AXP20X_LDO4_V_OUT_3000mV_END \ 86 (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS) 87 #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES 16 88 89 #define AXP22X_IO_ENABLED 0x03 90 #define AXP22X_IO_DISABLED 0x04 91 92 #define AXP22X_WORKMODE_DCDCX_MASK(x) BIT_MASK(x) 93 94 #define AXP22X_MISC_N_VBUSEN_FUNC BIT(4) 95 96 #define AXP22X_DCDC1_V_OUT_MASK GENMASK(4, 0) 97 #define AXP22X_DCDC2_V_OUT_MASK GENMASK(5, 0) 98 #define AXP22X_DCDC3_V_OUT_MASK GENMASK(5, 0) 99 #define AXP22X_DCDC4_V_OUT_MASK GENMASK(5, 0) 100 #define AXP22X_DCDC5_V_OUT_MASK GENMASK(4, 0) 101 #define AXP22X_DC5LDO_V_OUT_MASK GENMASK(2, 0) 102 #define AXP22X_ALDO1_V_OUT_MASK GENMASK(4, 0) 103 #define AXP22X_ALDO2_V_OUT_MASK GENMASK(4, 0) 104 #define AXP22X_ALDO3_V_OUT_MASK GENMASK(4, 0) 105 #define AXP22X_DLDO1_V_OUT_MASK GENMASK(4, 0) 106 #define AXP22X_DLDO2_V_OUT_MASK GENMASK(4, 0) 107 #define AXP22X_DLDO3_V_OUT_MASK GENMASK(4, 0) 108 #define AXP22X_DLDO4_V_OUT_MASK GENMASK(4, 0) 109 #define AXP22X_ELDO1_V_OUT_MASK GENMASK(4, 0) 110 #define AXP22X_ELDO2_V_OUT_MASK GENMASK(4, 0) 111 #define AXP22X_ELDO3_V_OUT_MASK GENMASK(4, 0) 112 #define AXP22X_LDO_IO0_V_OUT_MASK GENMASK(4, 0) 113 #define AXP22X_LDO_IO1_V_OUT_MASK GENMASK(4, 0) 114 115 #define AXP22X_PWR_OUT_DC5LDO_MASK BIT_MASK(0) 116 #define AXP22X_PWR_OUT_DCDC1_MASK BIT_MASK(1) 117 #define AXP22X_PWR_OUT_DCDC2_MASK BIT_MASK(2) 118 #define AXP22X_PWR_OUT_DCDC3_MASK BIT_MASK(3) 119 #define AXP22X_PWR_OUT_DCDC4_MASK BIT_MASK(4) 120 #define AXP22X_PWR_OUT_DCDC5_MASK BIT_MASK(5) 121 #define AXP22X_PWR_OUT_ALDO1_MASK BIT_MASK(6) 122 #define AXP22X_PWR_OUT_ALDO2_MASK BIT_MASK(7) 123 124 #define AXP22X_PWR_OUT_SW_MASK BIT_MASK(6) 125 #define AXP22X_PWR_OUT_DC1SW_MASK BIT_MASK(7) 126 127 #define AXP22X_PWR_OUT_ELDO1_MASK BIT_MASK(0) 128 #define AXP22X_PWR_OUT_ELDO2_MASK BIT_MASK(1) 129 #define AXP22X_PWR_OUT_ELDO3_MASK BIT_MASK(2) 130 #define AXP22X_PWR_OUT_DLDO1_MASK BIT_MASK(3) 131 #define AXP22X_PWR_OUT_DLDO2_MASK BIT_MASK(4) 132 #define AXP22X_PWR_OUT_DLDO3_MASK BIT_MASK(5) 133 #define AXP22X_PWR_OUT_DLDO4_MASK BIT_MASK(6) 134 #define AXP22X_PWR_OUT_ALDO3_MASK BIT_MASK(7) 135 136 #define AXP313A_DCDC1_NUM_VOLTAGES 107 137 #define AXP313A_DCDC23_NUM_VOLTAGES 88 138 #define AXP313A_DCDC_V_OUT_MASK GENMASK(6, 0) 139 #define AXP313A_LDO_V_OUT_MASK GENMASK(4, 0) 140 141 #define AXP717_DCDC1_NUM_VOLTAGES 88 142 #define AXP717_DCDC2_NUM_VOLTAGES 107 143 #define AXP717_DCDC3_NUM_VOLTAGES 103 144 #define AXP717_DCDC_V_OUT_MASK GENMASK(6, 0) 145 #define AXP717_LDO_V_OUT_MASK GENMASK(4, 0) 146 #define AXP717_BOOST_V_OUT_MASK GENMASK(7, 4) 147 148 #define AXP803_PWR_OUT_DCDC1_MASK BIT_MASK(0) 149 #define AXP803_PWR_OUT_DCDC2_MASK BIT_MASK(1) 150 #define AXP803_PWR_OUT_DCDC3_MASK BIT_MASK(2) 151 #define AXP803_PWR_OUT_DCDC4_MASK BIT_MASK(3) 152 #define AXP803_PWR_OUT_DCDC5_MASK BIT_MASK(4) 153 #define AXP803_PWR_OUT_DCDC6_MASK BIT_MASK(5) 154 155 #define AXP803_PWR_OUT_FLDO1_MASK BIT_MASK(2) 156 #define AXP803_PWR_OUT_FLDO2_MASK BIT_MASK(3) 157 158 #define AXP803_DCDC1_V_OUT_MASK GENMASK(4, 0) 159 #define AXP803_DCDC2_V_OUT_MASK GENMASK(6, 0) 160 #define AXP803_DCDC3_V_OUT_MASK GENMASK(6, 0) 161 #define AXP803_DCDC4_V_OUT_MASK GENMASK(6, 0) 162 #define AXP803_DCDC5_V_OUT_MASK GENMASK(6, 0) 163 #define AXP803_DCDC6_V_OUT_MASK GENMASK(6, 0) 164 165 #define AXP803_FLDO1_V_OUT_MASK GENMASK(3, 0) 166 #define AXP803_FLDO2_V_OUT_MASK GENMASK(3, 0) 167 168 #define AXP803_DCDC23_POLYPHASE_DUAL BIT(6) 169 #define AXP803_DCDC56_POLYPHASE_DUAL BIT(5) 170 171 #define AXP803_DCDC234_500mV_START 0x00 172 #define AXP803_DCDC234_500mV_STEPS 70 173 #define AXP803_DCDC234_500mV_END \ 174 (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS) 175 #define AXP803_DCDC234_1220mV_START 0x47 176 #define AXP803_DCDC234_1220mV_STEPS 4 177 #define AXP803_DCDC234_1220mV_END \ 178 (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS) 179 #define AXP803_DCDC234_NUM_VOLTAGES 76 180 181 #define AXP803_DCDC5_800mV_START 0x00 182 #define AXP803_DCDC5_800mV_STEPS 32 183 #define AXP803_DCDC5_800mV_END \ 184 (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS) 185 #define AXP803_DCDC5_1140mV_START 0x21 186 #define AXP803_DCDC5_1140mV_STEPS 35 187 #define AXP803_DCDC5_1140mV_END \ 188 (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS) 189 #define AXP803_DCDC5_NUM_VOLTAGES 69 190 191 #define AXP803_DCDC6_600mV_START 0x00 192 #define AXP803_DCDC6_600mV_STEPS 50 193 #define AXP803_DCDC6_600mV_END \ 194 (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS) 195 #define AXP803_DCDC6_1120mV_START 0x33 196 #define AXP803_DCDC6_1120mV_STEPS 20 197 #define AXP803_DCDC6_1120mV_END \ 198 (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS) 199 #define AXP803_DCDC6_NUM_VOLTAGES 72 200 201 #define AXP803_DLDO2_700mV_START 0x00 202 #define AXP803_DLDO2_700mV_STEPS 26 203 #define AXP803_DLDO2_700mV_END \ 204 (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS) 205 #define AXP803_DLDO2_3400mV_START 0x1b 206 #define AXP803_DLDO2_3400mV_STEPS 4 207 #define AXP803_DLDO2_3400mV_END \ 208 (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS) 209 #define AXP803_DLDO2_NUM_VOLTAGES 32 210 211 #define AXP806_DCDCA_V_CTRL_MASK GENMASK(6, 0) 212 #define AXP806_DCDCB_V_CTRL_MASK GENMASK(4, 0) 213 #define AXP806_DCDCC_V_CTRL_MASK GENMASK(6, 0) 214 #define AXP806_DCDCD_V_CTRL_MASK GENMASK(5, 0) 215 #define AXP806_DCDCE_V_CTRL_MASK GENMASK(4, 0) 216 #define AXP806_ALDO1_V_CTRL_MASK GENMASK(4, 0) 217 #define AXP806_ALDO2_V_CTRL_MASK GENMASK(4, 0) 218 #define AXP806_ALDO3_V_CTRL_MASK GENMASK(4, 0) 219 #define AXP806_BLDO1_V_CTRL_MASK GENMASK(3, 0) 220 #define AXP806_BLDO2_V_CTRL_MASK GENMASK(3, 0) 221 #define AXP806_BLDO3_V_CTRL_MASK GENMASK(3, 0) 222 #define AXP806_BLDO4_V_CTRL_MASK GENMASK(3, 0) 223 #define AXP806_CLDO1_V_CTRL_MASK GENMASK(4, 0) 224 #define AXP806_CLDO2_V_CTRL_MASK GENMASK(4, 0) 225 #define AXP806_CLDO3_V_CTRL_MASK GENMASK(4, 0) 226 227 #define AXP806_PWR_OUT_DCDCA_MASK BIT_MASK(0) 228 #define AXP806_PWR_OUT_DCDCB_MASK BIT_MASK(1) 229 #define AXP806_PWR_OUT_DCDCC_MASK BIT_MASK(2) 230 #define AXP806_PWR_OUT_DCDCD_MASK BIT_MASK(3) 231 #define AXP806_PWR_OUT_DCDCE_MASK BIT_MASK(4) 232 #define AXP806_PWR_OUT_ALDO1_MASK BIT_MASK(5) 233 #define AXP806_PWR_OUT_ALDO2_MASK BIT_MASK(6) 234 #define AXP806_PWR_OUT_ALDO3_MASK BIT_MASK(7) 235 #define AXP806_PWR_OUT_BLDO1_MASK BIT_MASK(0) 236 #define AXP806_PWR_OUT_BLDO2_MASK BIT_MASK(1) 237 #define AXP806_PWR_OUT_BLDO3_MASK BIT_MASK(2) 238 #define AXP806_PWR_OUT_BLDO4_MASK BIT_MASK(3) 239 #define AXP806_PWR_OUT_CLDO1_MASK BIT_MASK(4) 240 #define AXP806_PWR_OUT_CLDO2_MASK BIT_MASK(5) 241 #define AXP806_PWR_OUT_CLDO3_MASK BIT_MASK(6) 242 #define AXP806_PWR_OUT_SW_MASK BIT_MASK(7) 243 244 #define AXP806_DCDCAB_POLYPHASE_DUAL 0x40 245 #define AXP806_DCDCABC_POLYPHASE_TRI 0x80 246 #define AXP806_DCDCABC_POLYPHASE_MASK GENMASK(7, 6) 247 248 #define AXP806_DCDCDE_POLYPHASE_DUAL BIT(5) 249 250 #define AXP806_DCDCA_600mV_START 0x00 251 #define AXP806_DCDCA_600mV_STEPS 50 252 #define AXP806_DCDCA_600mV_END \ 253 (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS) 254 #define AXP806_DCDCA_1120mV_START 0x33 255 #define AXP806_DCDCA_1120mV_STEPS 20 256 #define AXP806_DCDCA_1120mV_END \ 257 (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS) 258 #define AXP806_DCDCA_NUM_VOLTAGES 72 259 260 #define AXP806_DCDCD_600mV_START 0x00 261 #define AXP806_DCDCD_600mV_STEPS 45 262 #define AXP806_DCDCD_600mV_END \ 263 (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS) 264 #define AXP806_DCDCD_1600mV_START 0x2e 265 #define AXP806_DCDCD_1600mV_STEPS 17 266 #define AXP806_DCDCD_1600mV_END \ 267 (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS) 268 #define AXP806_DCDCD_NUM_VOLTAGES 64 269 270 #define AXP809_DCDC4_600mV_START 0x00 271 #define AXP809_DCDC4_600mV_STEPS 47 272 #define AXP809_DCDC4_600mV_END \ 273 (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS) 274 #define AXP809_DCDC4_1800mV_START 0x30 275 #define AXP809_DCDC4_1800mV_STEPS 8 276 #define AXP809_DCDC4_1800mV_END \ 277 (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS) 278 #define AXP809_DCDC4_NUM_VOLTAGES 57 279 280 #define AXP813_DCDC7_V_OUT_MASK GENMASK(6, 0) 281 282 #define AXP813_PWR_OUT_DCDC7_MASK BIT_MASK(6) 283 284 #define AXP15060_DCDC1_V_CTRL_MASK GENMASK(4, 0) 285 #define AXP15060_DCDC2_V_CTRL_MASK GENMASK(6, 0) 286 #define AXP15060_DCDC3_V_CTRL_MASK GENMASK(6, 0) 287 #define AXP15060_DCDC4_V_CTRL_MASK GENMASK(6, 0) 288 #define AXP15060_DCDC5_V_CTRL_MASK GENMASK(6, 0) 289 #define AXP15060_DCDC6_V_CTRL_MASK GENMASK(4, 0) 290 #define AXP15060_ALDO1_V_CTRL_MASK GENMASK(4, 0) 291 #define AXP15060_ALDO2_V_CTRL_MASK GENMASK(4, 0) 292 #define AXP15060_ALDO3_V_CTRL_MASK GENMASK(4, 0) 293 #define AXP15060_ALDO4_V_CTRL_MASK GENMASK(4, 0) 294 #define AXP15060_ALDO5_V_CTRL_MASK GENMASK(4, 0) 295 #define AXP15060_BLDO1_V_CTRL_MASK GENMASK(4, 0) 296 #define AXP15060_BLDO2_V_CTRL_MASK GENMASK(4, 0) 297 #define AXP15060_BLDO3_V_CTRL_MASK GENMASK(4, 0) 298 #define AXP15060_BLDO4_V_CTRL_MASK GENMASK(4, 0) 299 #define AXP15060_BLDO5_V_CTRL_MASK GENMASK(4, 0) 300 #define AXP15060_CLDO1_V_CTRL_MASK GENMASK(4, 0) 301 #define AXP15060_CLDO2_V_CTRL_MASK GENMASK(4, 0) 302 #define AXP15060_CLDO3_V_CTRL_MASK GENMASK(4, 0) 303 #define AXP15060_CLDO4_V_CTRL_MASK GENMASK(5, 0) 304 #define AXP15060_CPUSLDO_V_CTRL_MASK GENMASK(3, 0) 305 306 #define AXP15060_PWR_OUT_DCDC1_MASK BIT_MASK(0) 307 #define AXP15060_PWR_OUT_DCDC2_MASK BIT_MASK(1) 308 #define AXP15060_PWR_OUT_DCDC3_MASK BIT_MASK(2) 309 #define AXP15060_PWR_OUT_DCDC4_MASK BIT_MASK(3) 310 #define AXP15060_PWR_OUT_DCDC5_MASK BIT_MASK(4) 311 #define AXP15060_PWR_OUT_DCDC6_MASK BIT_MASK(5) 312 #define AXP15060_PWR_OUT_ALDO1_MASK BIT_MASK(0) 313 #define AXP15060_PWR_OUT_ALDO2_MASK BIT_MASK(1) 314 #define AXP15060_PWR_OUT_ALDO3_MASK BIT_MASK(2) 315 #define AXP15060_PWR_OUT_ALDO4_MASK BIT_MASK(3) 316 #define AXP15060_PWR_OUT_ALDO5_MASK BIT_MASK(4) 317 #define AXP15060_PWR_OUT_BLDO1_MASK BIT_MASK(5) 318 #define AXP15060_PWR_OUT_BLDO2_MASK BIT_MASK(6) 319 #define AXP15060_PWR_OUT_BLDO3_MASK BIT_MASK(7) 320 #define AXP15060_PWR_OUT_BLDO4_MASK BIT_MASK(0) 321 #define AXP15060_PWR_OUT_BLDO5_MASK BIT_MASK(1) 322 #define AXP15060_PWR_OUT_CLDO1_MASK BIT_MASK(2) 323 #define AXP15060_PWR_OUT_CLDO2_MASK BIT_MASK(3) 324 #define AXP15060_PWR_OUT_CLDO3_MASK BIT_MASK(4) 325 #define AXP15060_PWR_OUT_CLDO4_MASK BIT_MASK(5) 326 #define AXP15060_PWR_OUT_CPUSLDO_MASK BIT_MASK(6) 327 #define AXP15060_PWR_OUT_SW_MASK BIT_MASK(7) 328 329 #define AXP15060_DCDC23_POLYPHASE_DUAL_MASK BIT_MASK(6) 330 #define AXP15060_DCDC46_POLYPHASE_DUAL_MASK BIT_MASK(7) 331 332 #define AXP15060_DCDC234_500mV_START 0x00 333 #define AXP15060_DCDC234_500mV_STEPS 70 334 #define AXP15060_DCDC234_500mV_END \ 335 (AXP15060_DCDC234_500mV_START + AXP15060_DCDC234_500mV_STEPS) 336 #define AXP15060_DCDC234_1220mV_START 0x47 337 #define AXP15060_DCDC234_1220mV_STEPS 16 338 #define AXP15060_DCDC234_1220mV_END \ 339 (AXP15060_DCDC234_1220mV_START + AXP15060_DCDC234_1220mV_STEPS) 340 #define AXP15060_DCDC234_NUM_VOLTAGES 88 341 342 #define AXP15060_DCDC5_800mV_START 0x00 343 #define AXP15060_DCDC5_800mV_STEPS 32 344 #define AXP15060_DCDC5_800mV_END \ 345 (AXP15060_DCDC5_800mV_START + AXP15060_DCDC5_800mV_STEPS) 346 #define AXP15060_DCDC5_1140mV_START 0x21 347 #define AXP15060_DCDC5_1140mV_STEPS 35 348 #define AXP15060_DCDC5_1140mV_END \ 349 (AXP15060_DCDC5_1140mV_START + AXP15060_DCDC5_1140mV_STEPS) 350 #define AXP15060_DCDC5_NUM_VOLTAGES 69 351 352 #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ 353 _vmask, _ereg, _emask, _enable_val, _disable_val) \ 354 [_family##_##_id] = { \ 355 .name = (_match), \ 356 .supply_name = (_supply), \ 357 .of_match = of_match_ptr(_match), \ 358 .regulators_node = of_match_ptr("regulators"), \ 359 .type = REGULATOR_VOLTAGE, \ 360 .id = _family##_##_id, \ 361 .n_voltages = (((_max) - (_min)) / (_step) + 1), \ 362 .owner = THIS_MODULE, \ 363 .min_uV = (_min) * 1000, \ 364 .uV_step = (_step) * 1000, \ 365 .vsel_reg = (_vreg), \ 366 .vsel_mask = (_vmask), \ 367 .enable_reg = (_ereg), \ 368 .enable_mask = (_emask), \ 369 .enable_val = (_enable_val), \ 370 .disable_val = (_disable_val), \ 371 .ops = &axp20x_ops, \ 372 } 373 374 #define AXP_DESC_DELAY(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ 375 _vmask, _ereg, _emask, _ramp_delay) \ 376 [_family##_##_id] = { \ 377 .name = (_match), \ 378 .supply_name = (_supply), \ 379 .of_match = of_match_ptr(_match), \ 380 .regulators_node = of_match_ptr("regulators"), \ 381 .type = REGULATOR_VOLTAGE, \ 382 .id = _family##_##_id, \ 383 .n_voltages = (((_max) - (_min)) / (_step) + 1), \ 384 .owner = THIS_MODULE, \ 385 .min_uV = (_min) * 1000, \ 386 .uV_step = (_step) * 1000, \ 387 .vsel_reg = (_vreg), \ 388 .vsel_mask = (_vmask), \ 389 .enable_reg = (_ereg), \ 390 .enable_mask = (_emask), \ 391 .ramp_delay = (_ramp_delay), \ 392 .ops = &axp20x_ops, \ 393 } 394 395 #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ 396 _vmask, _ereg, _emask) \ 397 AXP_DESC_DELAY(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ 398 _vmask, _ereg, _emask, 0) 399 400 #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \ 401 [_family##_##_id] = { \ 402 .name = (_match), \ 403 .supply_name = (_supply), \ 404 .of_match = of_match_ptr(_match), \ 405 .regulators_node = of_match_ptr("regulators"), \ 406 .type = REGULATOR_VOLTAGE, \ 407 .id = _family##_##_id, \ 408 .owner = THIS_MODULE, \ 409 .enable_reg = (_ereg), \ 410 .enable_mask = (_emask), \ 411 .ops = &axp20x_ops_sw, \ 412 } 413 414 #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \ 415 [_family##_##_id] = { \ 416 .name = (_match), \ 417 .supply_name = (_supply), \ 418 .of_match = of_match_ptr(_match), \ 419 .regulators_node = of_match_ptr("regulators"), \ 420 .type = REGULATOR_VOLTAGE, \ 421 .id = _family##_##_id, \ 422 .n_voltages = 1, \ 423 .owner = THIS_MODULE, \ 424 .min_uV = (_volt) * 1000, \ 425 .ops = &axp20x_ops_fixed \ 426 } 427 428 #define AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, _n_voltages, \ 429 _vreg, _vmask, _ereg, _emask, _ramp_delay) \ 430 [_family##_##_id] = { \ 431 .name = (_match), \ 432 .supply_name = (_supply), \ 433 .of_match = of_match_ptr(_match), \ 434 .regulators_node = of_match_ptr("regulators"), \ 435 .type = REGULATOR_VOLTAGE, \ 436 .id = _family##_##_id, \ 437 .n_voltages = (_n_voltages), \ 438 .owner = THIS_MODULE, \ 439 .vsel_reg = (_vreg), \ 440 .vsel_mask = (_vmask), \ 441 .enable_reg = (_ereg), \ 442 .enable_mask = (_emask), \ 443 .linear_ranges = (_ranges), \ 444 .n_linear_ranges = ARRAY_SIZE(_ranges), \ 445 .ramp_delay = (_ramp_delay), \ 446 .ops = &axp20x_ops_range, \ 447 } 448 449 #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \ 450 _vreg, _vmask, _ereg, _emask) \ 451 AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, \ 452 _n_voltages, _vreg, _vmask, _ereg, _emask, 0) 453 454 static const int axp209_dcdc2_ldo3_slew_rates[] = { 455 1600, 456 800, 457 }; 458 459 static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) 460 { 461 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); 462 int id = rdev_get_id(rdev); 463 u8 reg, mask, enable, cfg = 0xff; 464 const int *slew_rates; 465 int rate_count = 0; 466 467 switch (axp20x->variant) { 468 case AXP209_ID: 469 if (id == AXP20X_DCDC2) { 470 slew_rates = axp209_dcdc2_ldo3_slew_rates; 471 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates); 472 reg = AXP20X_DCDC2_LDO3_V_RAMP; 473 mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK | 474 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK; 475 enable = (ramp > 0) ? 476 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 0; 477 break; 478 } 479 480 if (id == AXP20X_LDO3) { 481 slew_rates = axp209_dcdc2_ldo3_slew_rates; 482 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates); 483 reg = AXP20X_DCDC2_LDO3_V_RAMP; 484 mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK | 485 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK; 486 enable = (ramp > 0) ? 487 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 0; 488 break; 489 } 490 491 if (rate_count > 0) 492 break; 493 494 fallthrough; 495 default: 496 /* Not supported for this regulator */ 497 return -ENOTSUPP; 498 } 499 500 if (ramp == 0) { 501 cfg = enable; 502 } else { 503 int i; 504 505 for (i = 0; i < rate_count; i++) { 506 if (ramp > slew_rates[i]) 507 break; 508 509 if (id == AXP20X_DCDC2) 510 cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i); 511 else 512 cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i); 513 } 514 515 if (cfg == 0xff) { 516 dev_err(axp20x->dev, "unsupported ramp value %d", ramp); 517 return -EINVAL; 518 } 519 520 cfg |= enable; 521 } 522 523 return regmap_update_bits(axp20x->regmap, reg, mask, cfg); 524 } 525 526 static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev) 527 { 528 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); 529 int id = rdev_get_id(rdev); 530 531 switch (axp20x->variant) { 532 case AXP209_ID: 533 if ((id == AXP20X_LDO3) && 534 rdev->constraints && rdev->constraints->soft_start) { 535 int v_out; 536 int ret; 537 538 /* 539 * On some boards, the LDO3 can be overloaded when 540 * turning on, causing the entire PMIC to shutdown 541 * without warning. Turning it on at the minimal voltage 542 * and then setting the voltage to the requested value 543 * works reliably. 544 */ 545 if (regulator_is_enabled_regmap(rdev)) 546 break; 547 548 v_out = regulator_get_voltage_sel_regmap(rdev); 549 if (v_out < 0) 550 return v_out; 551 552 if (v_out == 0) 553 break; 554 555 ret = regulator_set_voltage_sel_regmap(rdev, 0x00); 556 /* 557 * A small pause is needed between 558 * setting the voltage and enabling the LDO to give the 559 * internal state machine time to process the request. 560 */ 561 usleep_range(1000, 5000); 562 ret |= regulator_enable_regmap(rdev); 563 ret |= regulator_set_voltage_sel_regmap(rdev, v_out); 564 565 return ret; 566 } 567 break; 568 default: 569 /* No quirks */ 570 break; 571 } 572 573 return regulator_enable_regmap(rdev); 574 }; 575 576 static const struct regulator_ops axp20x_ops_fixed = { 577 .list_voltage = regulator_list_voltage_linear, 578 }; 579 580 static const struct regulator_ops axp20x_ops_range = { 581 .set_voltage_sel = regulator_set_voltage_sel_regmap, 582 .get_voltage_sel = regulator_get_voltage_sel_regmap, 583 .list_voltage = regulator_list_voltage_linear_range, 584 .enable = regulator_enable_regmap, 585 .disable = regulator_disable_regmap, 586 .is_enabled = regulator_is_enabled_regmap, 587 }; 588 589 static const struct regulator_ops axp20x_ops = { 590 .set_voltage_sel = regulator_set_voltage_sel_regmap, 591 .get_voltage_sel = regulator_get_voltage_sel_regmap, 592 .list_voltage = regulator_list_voltage_linear, 593 .enable = axp20x_regulator_enable_regmap, 594 .disable = regulator_disable_regmap, 595 .is_enabled = regulator_is_enabled_regmap, 596 .set_ramp_delay = axp20x_set_ramp_delay, 597 }; 598 599 static const struct regulator_ops axp20x_ops_sw = { 600 .enable = regulator_enable_regmap, 601 .disable = regulator_disable_regmap, 602 .is_enabled = regulator_is_enabled_regmap, 603 }; 604 605 static const struct linear_range axp20x_ldo4_ranges[] = { 606 REGULATOR_LINEAR_RANGE(1250000, 607 AXP20X_LDO4_V_OUT_1250mV_START, 608 AXP20X_LDO4_V_OUT_1250mV_END, 609 0), 610 REGULATOR_LINEAR_RANGE(1300000, 611 AXP20X_LDO4_V_OUT_1300mV_START, 612 AXP20X_LDO4_V_OUT_1300mV_END, 613 100000), 614 REGULATOR_LINEAR_RANGE(2500000, 615 AXP20X_LDO4_V_OUT_2500mV_START, 616 AXP20X_LDO4_V_OUT_2500mV_END, 617 0), 618 REGULATOR_LINEAR_RANGE(2700000, 619 AXP20X_LDO4_V_OUT_2700mV_START, 620 AXP20X_LDO4_V_OUT_2700mV_END, 621 100000), 622 REGULATOR_LINEAR_RANGE(3000000, 623 AXP20X_LDO4_V_OUT_3000mV_START, 624 AXP20X_LDO4_V_OUT_3000mV_END, 625 100000), 626 }; 627 628 static const struct regulator_desc axp20x_regulators[] = { 629 AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25, 630 AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK, 631 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK), 632 AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25, 633 AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK, 634 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK), 635 AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300), 636 AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100, 637 AXP20X_LDO24_V_OUT, AXP20X_LDO2_V_OUT_MASK, 638 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK), 639 AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25, 640 AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK, 641 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK), 642 AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in", 643 axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES, 644 AXP20X_LDO24_V_OUT, AXP20X_LDO4_V_OUT_MASK, 645 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK), 646 AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100, 647 AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK, 648 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 649 AXP20X_IO_ENABLED, AXP20X_IO_DISABLED), 650 }; 651 652 static const struct regulator_desc axp22x_regulators[] = { 653 AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 654 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK, 655 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK), 656 AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20, 657 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK, 658 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK), 659 AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20, 660 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK, 661 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK), 662 AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20, 663 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK, 664 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK), 665 AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, 666 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK, 667 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK), 668 /* secondary switchable output of DCDC1 */ 669 AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL, 670 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 671 /* LDO regulator internally chained to DCDC5 */ 672 AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100, 673 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK, 674 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK), 675 AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 676 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 677 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK), 678 AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 679 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 680 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK), 681 AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 682 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 683 AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK), 684 AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100, 685 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 686 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 687 AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100, 688 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, 689 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 690 AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100, 691 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, 692 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), 693 AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100, 694 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, 695 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), 696 AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100, 697 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 698 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 699 AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100, 700 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 701 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 702 AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100, 703 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 704 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 705 /* Note the datasheet only guarantees reliable operation up to 706 * 3.3V, this needs to be enforced via dts provided constraints */ 707 AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100, 708 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 709 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 710 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 711 /* Note the datasheet only guarantees reliable operation up to 712 * 3.3V, this needs to be enforced via dts provided constraints */ 713 AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100, 714 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 715 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 716 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 717 AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000), 718 }; 719 720 static const struct regulator_desc axp22x_drivevbus_regulator = { 721 .name = "drivevbus", 722 .supply_name = "drivevbus", 723 .of_match = of_match_ptr("drivevbus"), 724 .regulators_node = of_match_ptr("regulators"), 725 .type = REGULATOR_VOLTAGE, 726 .owner = THIS_MODULE, 727 .enable_reg = AXP20X_VBUS_IPSOUT_MGMT, 728 .enable_mask = AXP20X_VBUS_IPSOUT_MGMT_MASK, 729 .ops = &axp20x_ops_sw, 730 }; 731 732 static const struct linear_range axp313a_dcdc1_ranges[] = { 733 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), 734 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000), 735 REGULATOR_LINEAR_RANGE(1600000, 88, 106, 100000), 736 }; 737 738 static const struct linear_range axp313a_dcdc2_ranges[] = { 739 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), 740 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000), 741 }; 742 743 /* 744 * This is deviating from the datasheet. The values here are taken from the 745 * BSP driver and have been confirmed by measurements. 746 */ 747 static const struct linear_range axp313a_dcdc3_ranges[] = { 748 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), 749 REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000), 750 }; 751 752 static const struct regulator_desc axp313a_regulators[] = { 753 AXP_DESC_RANGES(AXP313A, DCDC1, "dcdc1", "vin1", 754 axp313a_dcdc1_ranges, AXP313A_DCDC1_NUM_VOLTAGES, 755 AXP313A_DCDC1_CONTROL, AXP313A_DCDC_V_OUT_MASK, 756 AXP313A_OUTPUT_CONTROL, BIT(0)), 757 AXP_DESC_RANGES(AXP313A, DCDC2, "dcdc2", "vin2", 758 axp313a_dcdc2_ranges, AXP313A_DCDC23_NUM_VOLTAGES, 759 AXP313A_DCDC2_CONTROL, AXP313A_DCDC_V_OUT_MASK, 760 AXP313A_OUTPUT_CONTROL, BIT(1)), 761 AXP_DESC_RANGES(AXP313A, DCDC3, "dcdc3", "vin3", 762 axp313a_dcdc3_ranges, AXP313A_DCDC23_NUM_VOLTAGES, 763 AXP313A_DCDC3_CONTROL, AXP313A_DCDC_V_OUT_MASK, 764 AXP313A_OUTPUT_CONTROL, BIT(2)), 765 AXP_DESC(AXP313A, ALDO1, "aldo1", "vin1", 500, 3500, 100, 766 AXP313A_ALDO1_CONTROL, AXP313A_LDO_V_OUT_MASK, 767 AXP313A_OUTPUT_CONTROL, BIT(3)), 768 AXP_DESC(AXP313A, DLDO1, "dldo1", "vin1", 500, 3500, 100, 769 AXP313A_DLDO1_CONTROL, AXP313A_LDO_V_OUT_MASK, 770 AXP313A_OUTPUT_CONTROL, BIT(4)), 771 AXP_DESC_FIXED(AXP313A, RTC_LDO, "rtc-ldo", "vin1", 1800), 772 }; 773 774 static const struct linear_range axp717_dcdc1_ranges[] = { 775 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), 776 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000), 777 }; 778 779 /* 780 * The manual says that the last voltage is 3.4V, encoded as 0b1101011 (107), 781 * but every other method proves that this is wrong, so it's really 106 that 782 * programs the final 3.4V. 783 */ 784 static const struct linear_range axp717_dcdc2_ranges[] = { 785 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), 786 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000), 787 REGULATOR_LINEAR_RANGE(1600000, 88, 106, 100000), 788 }; 789 790 static const struct linear_range axp717_dcdc3_ranges[] = { 791 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000), 792 REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000), 793 }; 794 795 static const struct regulator_desc axp717_regulators[] = { 796 AXP_DESC_RANGES_DELAY(AXP717, DCDC1, "dcdc1", "vin1", 797 axp717_dcdc1_ranges, AXP717_DCDC1_NUM_VOLTAGES, 798 AXP717_DCDC1_CONTROL, AXP717_DCDC_V_OUT_MASK, 799 AXP717_DCDC_OUTPUT_CONTROL, BIT(0), 640), 800 AXP_DESC_RANGES_DELAY(AXP717, DCDC2, "dcdc2", "vin2", 801 axp717_dcdc2_ranges, AXP717_DCDC2_NUM_VOLTAGES, 802 AXP717_DCDC2_CONTROL, AXP717_DCDC_V_OUT_MASK, 803 AXP717_DCDC_OUTPUT_CONTROL, BIT(1), 640), 804 AXP_DESC_RANGES_DELAY(AXP717, DCDC3, "dcdc3", "vin3", 805 axp717_dcdc3_ranges, AXP717_DCDC3_NUM_VOLTAGES, 806 AXP717_DCDC3_CONTROL, AXP717_DCDC_V_OUT_MASK, 807 AXP717_DCDC_OUTPUT_CONTROL, BIT(2), 640), 808 AXP_DESC_DELAY(AXP717, DCDC4, "dcdc4", "vin4", 1000, 3700, 100, 809 AXP717_DCDC4_CONTROL, AXP717_DCDC_V_OUT_MASK, 810 AXP717_DCDC_OUTPUT_CONTROL, BIT(3), 6400), 811 AXP_DESC(AXP717, ALDO1, "aldo1", "aldoin", 500, 3500, 100, 812 AXP717_ALDO1_CONTROL, AXP717_LDO_V_OUT_MASK, 813 AXP717_LDO0_OUTPUT_CONTROL, BIT(0)), 814 AXP_DESC(AXP717, ALDO2, "aldo2", "aldoin", 500, 3500, 100, 815 AXP717_ALDO2_CONTROL, AXP717_LDO_V_OUT_MASK, 816 AXP717_LDO0_OUTPUT_CONTROL, BIT(1)), 817 AXP_DESC(AXP717, ALDO3, "aldo3", "aldoin", 500, 3500, 100, 818 AXP717_ALDO3_CONTROL, AXP717_LDO_V_OUT_MASK, 819 AXP717_LDO0_OUTPUT_CONTROL, BIT(2)), 820 AXP_DESC(AXP717, ALDO4, "aldo4", "aldoin", 500, 3500, 100, 821 AXP717_ALDO4_CONTROL, AXP717_LDO_V_OUT_MASK, 822 AXP717_LDO0_OUTPUT_CONTROL, BIT(3)), 823 AXP_DESC(AXP717, BLDO1, "bldo1", "bldoin", 500, 3500, 100, 824 AXP717_BLDO1_CONTROL, AXP717_LDO_V_OUT_MASK, 825 AXP717_LDO0_OUTPUT_CONTROL, BIT(4)), 826 AXP_DESC(AXP717, BLDO2, "bldo2", "bldoin", 500, 3500, 100, 827 AXP717_BLDO2_CONTROL, AXP717_LDO_V_OUT_MASK, 828 AXP717_LDO0_OUTPUT_CONTROL, BIT(5)), 829 AXP_DESC(AXP717, BLDO3, "bldo3", "bldoin", 500, 3500, 100, 830 AXP717_BLDO3_CONTROL, AXP717_LDO_V_OUT_MASK, 831 AXP717_LDO0_OUTPUT_CONTROL, BIT(6)), 832 AXP_DESC(AXP717, BLDO4, "bldo4", "bldoin", 500, 3500, 100, 833 AXP717_BLDO4_CONTROL, AXP717_LDO_V_OUT_MASK, 834 AXP717_LDO0_OUTPUT_CONTROL, BIT(7)), 835 AXP_DESC(AXP717, CLDO1, "cldo1", "cldoin", 500, 3500, 100, 836 AXP717_CLDO1_CONTROL, AXP717_LDO_V_OUT_MASK, 837 AXP717_LDO1_OUTPUT_CONTROL, BIT(0)), 838 AXP_DESC(AXP717, CLDO2, "cldo2", "cldoin", 500, 3500, 100, 839 AXP717_CLDO2_CONTROL, AXP717_LDO_V_OUT_MASK, 840 AXP717_LDO1_OUTPUT_CONTROL, BIT(1)), 841 AXP_DESC(AXP717, CLDO3, "cldo3", "cldoin", 500, 3500, 100, 842 AXP717_CLDO3_CONTROL, AXP717_LDO_V_OUT_MASK, 843 AXP717_LDO1_OUTPUT_CONTROL, BIT(2)), 844 AXP_DESC(AXP717, CLDO4, "cldo4", "cldoin", 500, 3500, 100, 845 AXP717_CLDO4_CONTROL, AXP717_LDO_V_OUT_MASK, 846 AXP717_LDO1_OUTPUT_CONTROL, BIT(3)), 847 AXP_DESC(AXP717, CPUSLDO, "cpusldo", "vin1", 500, 1400, 50, 848 AXP717_CPUSLDO_CONTROL, AXP717_LDO_V_OUT_MASK, 849 AXP717_LDO1_OUTPUT_CONTROL, BIT(4)), 850 AXP_DESC(AXP717, BOOST, "boost", "vin1", 4550, 5510, 64, 851 AXP717_BOOST_CONTROL, AXP717_BOOST_V_OUT_MASK, 852 AXP717_MODULE_EN_CONTROL_2, BIT(4)), 853 }; 854 855 /* DCDC ranges shared with AXP813 */ 856 static const struct linear_range axp803_dcdc234_ranges[] = { 857 REGULATOR_LINEAR_RANGE(500000, 858 AXP803_DCDC234_500mV_START, 859 AXP803_DCDC234_500mV_END, 860 10000), 861 REGULATOR_LINEAR_RANGE(1220000, 862 AXP803_DCDC234_1220mV_START, 863 AXP803_DCDC234_1220mV_END, 864 20000), 865 }; 866 867 static const struct linear_range axp803_dcdc5_ranges[] = { 868 REGULATOR_LINEAR_RANGE(800000, 869 AXP803_DCDC5_800mV_START, 870 AXP803_DCDC5_800mV_END, 871 10000), 872 REGULATOR_LINEAR_RANGE(1140000, 873 AXP803_DCDC5_1140mV_START, 874 AXP803_DCDC5_1140mV_END, 875 20000), 876 }; 877 878 static const struct linear_range axp803_dcdc6_ranges[] = { 879 REGULATOR_LINEAR_RANGE(600000, 880 AXP803_DCDC6_600mV_START, 881 AXP803_DCDC6_600mV_END, 882 10000), 883 REGULATOR_LINEAR_RANGE(1120000, 884 AXP803_DCDC6_1120mV_START, 885 AXP803_DCDC6_1120mV_END, 886 20000), 887 }; 888 889 /* AXP806's CLDO2 and AXP809's DLDO1 share the same range */ 890 static const struct linear_range axp803_dldo2_ranges[] = { 891 REGULATOR_LINEAR_RANGE(700000, 892 AXP803_DLDO2_700mV_START, 893 AXP803_DLDO2_700mV_END, 894 100000), 895 REGULATOR_LINEAR_RANGE(3400000, 896 AXP803_DLDO2_3400mV_START, 897 AXP803_DLDO2_3400mV_END, 898 200000), 899 }; 900 901 static const struct regulator_desc axp803_regulators[] = { 902 AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 903 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK, 904 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK), 905 AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2", 906 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 907 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK, 908 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK), 909 AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3", 910 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 911 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK, 912 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK), 913 AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4", 914 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 915 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK, 916 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK), 917 AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5", 918 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES, 919 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK, 920 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK), 921 AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6", 922 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, 923 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK, 924 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK), 925 /* secondary switchable output of DCDC1 */ 926 AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL, 927 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 928 AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 929 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 930 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), 931 AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 932 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 933 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), 934 AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 935 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 936 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK), 937 AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100, 938 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 939 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 940 AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin", 941 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 942 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, 943 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 944 AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100, 945 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, 946 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), 947 AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100, 948 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, 949 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), 950 AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50, 951 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 952 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 953 AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50, 954 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 955 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 956 AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50, 957 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 958 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 959 AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50, 960 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK, 961 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK), 962 AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50, 963 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK, 964 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK), 965 AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100, 966 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 967 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 968 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 969 AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100, 970 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 971 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 972 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 973 AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000), 974 }; 975 976 static const struct linear_range axp806_dcdca_ranges[] = { 977 REGULATOR_LINEAR_RANGE(600000, 978 AXP806_DCDCA_600mV_START, 979 AXP806_DCDCA_600mV_END, 980 10000), 981 REGULATOR_LINEAR_RANGE(1120000, 982 AXP806_DCDCA_1120mV_START, 983 AXP806_DCDCA_1120mV_END, 984 20000), 985 }; 986 987 static const struct linear_range axp806_dcdcd_ranges[] = { 988 REGULATOR_LINEAR_RANGE(600000, 989 AXP806_DCDCD_600mV_START, 990 AXP806_DCDCD_600mV_END, 991 20000), 992 REGULATOR_LINEAR_RANGE(1600000, 993 AXP806_DCDCD_1600mV_START, 994 AXP806_DCDCD_1600mV_END, 995 100000), 996 }; 997 998 static const struct regulator_desc axp806_regulators[] = { 999 AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina", 1000 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES, 1001 AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK, 1002 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK), 1003 AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50, 1004 AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK, 1005 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK), 1006 AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc", 1007 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES, 1008 AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK, 1009 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK), 1010 AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind", 1011 axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES, 1012 AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK, 1013 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK), 1014 AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100, 1015 AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK, 1016 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK), 1017 AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 1018 AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK, 1019 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK), 1020 AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100, 1021 AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK, 1022 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK), 1023 AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 1024 AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK, 1025 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK), 1026 AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100, 1027 AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK, 1028 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK), 1029 AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100, 1030 AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK, 1031 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK), 1032 AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100, 1033 AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK, 1034 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK), 1035 AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100, 1036 AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK, 1037 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK), 1038 AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100, 1039 AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK, 1040 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK), 1041 AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin", 1042 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 1043 AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK, 1044 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK), 1045 AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100, 1046 AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK, 1047 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK), 1048 AXP_DESC_SW(AXP806, SW, "sw", "swin", 1049 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK), 1050 }; 1051 1052 static const struct linear_range axp809_dcdc4_ranges[] = { 1053 REGULATOR_LINEAR_RANGE(600000, 1054 AXP809_DCDC4_600mV_START, 1055 AXP809_DCDC4_600mV_END, 1056 20000), 1057 REGULATOR_LINEAR_RANGE(1800000, 1058 AXP809_DCDC4_1800mV_START, 1059 AXP809_DCDC4_1800mV_END, 1060 100000), 1061 }; 1062 1063 static const struct regulator_desc axp809_regulators[] = { 1064 AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 1065 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK, 1066 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK), 1067 AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20, 1068 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK, 1069 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK), 1070 AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20, 1071 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK, 1072 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK), 1073 AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4", 1074 axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES, 1075 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK, 1076 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK), 1077 AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, 1078 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK, 1079 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK), 1080 /* secondary switchable output of DCDC1 */ 1081 AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL, 1082 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 1083 /* LDO regulator internally chained to DCDC5 */ 1084 AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100, 1085 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK, 1086 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK), 1087 AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 1088 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 1089 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK), 1090 AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 1091 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 1092 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK), 1093 AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 1094 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 1095 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK), 1096 AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin", 1097 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 1098 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 1099 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 1100 AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100, 1101 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, 1102 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 1103 AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100, 1104 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 1105 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 1106 AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100, 1107 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 1108 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 1109 AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100, 1110 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 1111 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 1112 /* 1113 * Note the datasheet only guarantees reliable operation up to 1114 * 3.3V, this needs to be enforced via dts provided constraints 1115 */ 1116 AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100, 1117 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 1118 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 1119 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 1120 /* 1121 * Note the datasheet only guarantees reliable operation up to 1122 * 3.3V, this needs to be enforced via dts provided constraints 1123 */ 1124 AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100, 1125 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 1126 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 1127 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 1128 AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800), 1129 AXP_DESC_SW(AXP809, SW, "sw", "swin", 1130 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK), 1131 }; 1132 1133 static const struct regulator_desc axp813_regulators[] = { 1134 AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 1135 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK, 1136 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK), 1137 AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2", 1138 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 1139 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK, 1140 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK), 1141 AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3", 1142 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 1143 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK, 1144 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK), 1145 AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4", 1146 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES, 1147 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK, 1148 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK), 1149 AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5", 1150 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES, 1151 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK, 1152 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK), 1153 AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6", 1154 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, 1155 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK, 1156 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK), 1157 AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7", 1158 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES, 1159 AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK, 1160 AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK), 1161 AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 1162 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, 1163 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), 1164 AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 1165 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, 1166 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), 1167 AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 1168 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, 1169 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK), 1170 AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100, 1171 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK, 1172 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), 1173 AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin", 1174 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, 1175 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, 1176 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), 1177 AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100, 1178 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, 1179 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK), 1180 AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100, 1181 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK, 1182 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK), 1183 AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50, 1184 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK, 1185 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK), 1186 AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50, 1187 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, 1188 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), 1189 AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50, 1190 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, 1191 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), 1192 /* to do / check ... */ 1193 AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50, 1194 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK, 1195 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK), 1196 AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50, 1197 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK, 1198 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK), 1199 /* 1200 * TODO: FLDO3 = {DCDC5, FLDOIN} / 2 1201 * 1202 * This means FLDO3 effectively switches supplies at runtime, 1203 * something the regulator subsystem does not support. 1204 */ 1205 AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800), 1206 AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100, 1207 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK, 1208 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK, 1209 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 1210 AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100, 1211 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK, 1212 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK, 1213 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 1214 AXP_DESC_SW(AXP813, SW, "sw", "swin", 1215 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK), 1216 }; 1217 1218 static const struct linear_range axp15060_dcdc234_ranges[] = { 1219 REGULATOR_LINEAR_RANGE(500000, 1220 AXP15060_DCDC234_500mV_START, 1221 AXP15060_DCDC234_500mV_END, 1222 10000), 1223 REGULATOR_LINEAR_RANGE(1220000, 1224 AXP15060_DCDC234_1220mV_START, 1225 AXP15060_DCDC234_1220mV_END, 1226 20000), 1227 }; 1228 1229 static const struct linear_range axp15060_dcdc5_ranges[] = { 1230 REGULATOR_LINEAR_RANGE(800000, 1231 AXP15060_DCDC5_800mV_START, 1232 AXP15060_DCDC5_800mV_END, 1233 10000), 1234 REGULATOR_LINEAR_RANGE(1140000, 1235 AXP15060_DCDC5_1140mV_START, 1236 AXP15060_DCDC5_1140mV_END, 1237 20000), 1238 }; 1239 1240 static const struct regulator_desc axp15060_regulators[] = { 1241 AXP_DESC(AXP15060, DCDC1, "dcdc1", "vin1", 1500, 3400, 100, 1242 AXP15060_DCDC1_V_CTRL, AXP15060_DCDC1_V_CTRL_MASK, 1243 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC1_MASK), 1244 AXP_DESC_RANGES(AXP15060, DCDC2, "dcdc2", "vin2", 1245 axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES, 1246 AXP15060_DCDC2_V_CTRL, AXP15060_DCDC2_V_CTRL_MASK, 1247 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC2_MASK), 1248 AXP_DESC_RANGES(AXP15060, DCDC3, "dcdc3", "vin3", 1249 axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES, 1250 AXP15060_DCDC3_V_CTRL, AXP15060_DCDC3_V_CTRL_MASK, 1251 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC3_MASK), 1252 AXP_DESC_RANGES(AXP15060, DCDC4, "dcdc4", "vin4", 1253 axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES, 1254 AXP15060_DCDC4_V_CTRL, AXP15060_DCDC4_V_CTRL_MASK, 1255 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC4_MASK), 1256 AXP_DESC_RANGES(AXP15060, DCDC5, "dcdc5", "vin5", 1257 axp15060_dcdc5_ranges, AXP15060_DCDC5_NUM_VOLTAGES, 1258 AXP15060_DCDC5_V_CTRL, AXP15060_DCDC5_V_CTRL_MASK, 1259 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC5_MASK), 1260 AXP_DESC(AXP15060, DCDC6, "dcdc6", "vin6", 500, 3400, 100, 1261 AXP15060_DCDC6_V_CTRL, AXP15060_DCDC6_V_CTRL_MASK, 1262 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC6_MASK), 1263 AXP_DESC(AXP15060, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 1264 AXP15060_ALDO1_V_CTRL, AXP15060_ALDO1_V_CTRL_MASK, 1265 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO1_MASK), 1266 AXP_DESC(AXP15060, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 1267 AXP15060_ALDO2_V_CTRL, AXP15060_ALDO2_V_CTRL_MASK, 1268 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO2_MASK), 1269 AXP_DESC(AXP15060, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 1270 AXP15060_ALDO3_V_CTRL, AXP15060_ALDO3_V_CTRL_MASK, 1271 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO3_MASK), 1272 AXP_DESC(AXP15060, ALDO4, "aldo4", "aldoin", 700, 3300, 100, 1273 AXP15060_ALDO4_V_CTRL, AXP15060_ALDO4_V_CTRL_MASK, 1274 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO4_MASK), 1275 AXP_DESC(AXP15060, ALDO5, "aldo5", "aldoin", 700, 3300, 100, 1276 AXP15060_ALDO5_V_CTRL, AXP15060_ALDO5_V_CTRL_MASK, 1277 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO5_MASK), 1278 AXP_DESC(AXP15060, BLDO1, "bldo1", "bldoin", 700, 3300, 100, 1279 AXP15060_BLDO1_V_CTRL, AXP15060_BLDO1_V_CTRL_MASK, 1280 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO1_MASK), 1281 AXP_DESC(AXP15060, BLDO2, "bldo2", "bldoin", 700, 3300, 100, 1282 AXP15060_BLDO2_V_CTRL, AXP15060_BLDO2_V_CTRL_MASK, 1283 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO2_MASK), 1284 AXP_DESC(AXP15060, BLDO3, "bldo3", "bldoin", 700, 3300, 100, 1285 AXP15060_BLDO3_V_CTRL, AXP15060_BLDO3_V_CTRL_MASK, 1286 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO3_MASK), 1287 AXP_DESC(AXP15060, BLDO4, "bldo4", "bldoin", 700, 3300, 100, 1288 AXP15060_BLDO4_V_CTRL, AXP15060_BLDO4_V_CTRL_MASK, 1289 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO4_MASK), 1290 AXP_DESC(AXP15060, BLDO5, "bldo5", "bldoin", 700, 3300, 100, 1291 AXP15060_BLDO5_V_CTRL, AXP15060_BLDO5_V_CTRL_MASK, 1292 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO5_MASK), 1293 AXP_DESC(AXP15060, CLDO1, "cldo1", "cldoin", 700, 3300, 100, 1294 AXP15060_CLDO1_V_CTRL, AXP15060_CLDO1_V_CTRL_MASK, 1295 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO1_MASK), 1296 AXP_DESC(AXP15060, CLDO2, "cldo2", "cldoin", 700, 3300, 100, 1297 AXP15060_CLDO2_V_CTRL, AXP15060_CLDO2_V_CTRL_MASK, 1298 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO2_MASK), 1299 AXP_DESC(AXP15060, CLDO3, "cldo3", "cldoin", 700, 3300, 100, 1300 AXP15060_CLDO3_V_CTRL, AXP15060_CLDO3_V_CTRL_MASK, 1301 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO3_MASK), 1302 AXP_DESC(AXP15060, CLDO4, "cldo4", "cldoin", 700, 4200, 100, 1303 AXP15060_CLDO4_V_CTRL, AXP15060_CLDO4_V_CTRL_MASK, 1304 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO4_MASK), 1305 /* Supply comes from DCDC5 */ 1306 AXP_DESC(AXP15060, CPUSLDO, "cpusldo", NULL, 700, 1400, 50, 1307 AXP15060_CPUSLDO_V_CTRL, AXP15060_CPUSLDO_V_CTRL_MASK, 1308 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CPUSLDO_MASK), 1309 /* Supply comes from DCDC1 */ 1310 AXP_DESC_SW(AXP15060, SW, "sw", NULL, 1311 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_SW_MASK), 1312 /* Supply comes from ALDO1 */ 1313 AXP_DESC_FIXED(AXP15060, RTC_LDO, "rtc-ldo", NULL, 1800), 1314 }; 1315 1316 static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq) 1317 { 1318 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); 1319 unsigned int reg = AXP20X_DCDC_FREQ; 1320 u32 min, max, def, step; 1321 1322 switch (axp20x->variant) { 1323 case AXP202_ID: 1324 case AXP209_ID: 1325 min = 750; 1326 max = 1875; 1327 def = 1500; 1328 step = 75; 1329 break; 1330 case AXP803_ID: 1331 case AXP813_ID: 1332 /* 1333 * AXP803/AXP813 DCDC work frequency setting has the same 1334 * range and step as AXP22X, but at a different register. 1335 * (See include/linux/mfd/axp20x.h) 1336 */ 1337 reg = AXP803_DCDC_FREQ_CTRL; 1338 fallthrough; /* to the check below */ 1339 case AXP806_ID: 1340 /* 1341 * AXP806 also have DCDC work frequency setting register at a 1342 * different position. 1343 */ 1344 if (axp20x->variant == AXP806_ID) 1345 reg = AXP806_DCDC_FREQ_CTRL; 1346 fallthrough; 1347 case AXP221_ID: 1348 case AXP223_ID: 1349 case AXP809_ID: 1350 min = 1800; 1351 max = 4050; 1352 def = 3000; 1353 step = 150; 1354 break; 1355 case AXP313A_ID: 1356 case AXP323_ID: 1357 case AXP717_ID: 1358 case AXP15060_ID: 1359 /* The DCDC PWM frequency seems to be fixed to 3 MHz. */ 1360 if (dcdcfreq != 0) { 1361 dev_err(&pdev->dev, 1362 "DCDC frequency on this PMIC is fixed to 3 MHz.\n"); 1363 return -EINVAL; 1364 } 1365 1366 return 0; 1367 default: 1368 dev_err(&pdev->dev, 1369 "Setting DCDC frequency for unsupported AXP variant\n"); 1370 return -EINVAL; 1371 } 1372 1373 if (dcdcfreq == 0) 1374 dcdcfreq = def; 1375 1376 if (dcdcfreq < min) { 1377 dcdcfreq = min; 1378 dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n", 1379 min); 1380 } 1381 1382 if (dcdcfreq > max) { 1383 dcdcfreq = max; 1384 dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n", 1385 max); 1386 } 1387 1388 dcdcfreq = (dcdcfreq - min) / step; 1389 1390 return regmap_update_bits(axp20x->regmap, reg, 1391 AXP20X_FREQ_DCDC_MASK, dcdcfreq); 1392 } 1393 1394 static int axp20x_regulator_parse_dt(struct platform_device *pdev) 1395 { 1396 struct device_node *np, *regulators; 1397 int ret = 0; 1398 u32 dcdcfreq = 0; 1399 1400 np = of_node_get(pdev->dev.parent->of_node); 1401 if (!np) 1402 return 0; 1403 1404 regulators = of_get_child_by_name(np, "regulators"); 1405 if (!regulators) { 1406 dev_warn(&pdev->dev, "regulators node not found\n"); 1407 } else { 1408 of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq); 1409 ret = axp20x_set_dcdc_freq(pdev, dcdcfreq); 1410 if (ret < 0) { 1411 dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret); 1412 } 1413 of_node_put(regulators); 1414 } 1415 1416 of_node_put(np); 1417 return ret; 1418 } 1419 1420 static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode) 1421 { 1422 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); 1423 unsigned int reg = AXP20X_DCDC_MODE; 1424 unsigned int mask; 1425 1426 switch (axp20x->variant) { 1427 case AXP202_ID: 1428 case AXP209_ID: 1429 if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3)) 1430 return -EINVAL; 1431 1432 mask = AXP20X_WORKMODE_DCDC2_MASK; 1433 if (id == AXP20X_DCDC3) 1434 mask = AXP20X_WORKMODE_DCDC3_MASK; 1435 1436 workmode <<= ffs(mask) - 1; 1437 break; 1438 1439 case AXP806_ID: 1440 /* 1441 * AXP806 DCDC regulator IDs have the same range as AXP22X. 1442 * (See include/linux/mfd/axp20x.h) 1443 */ 1444 reg = AXP806_DCDC_MODE_CTRL2; 1445 fallthrough; /* to the check below */ 1446 case AXP221_ID: 1447 case AXP223_ID: 1448 case AXP809_ID: 1449 if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5) 1450 return -EINVAL; 1451 1452 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1); 1453 workmode <<= id - AXP22X_DCDC1; 1454 break; 1455 1456 case AXP803_ID: 1457 if (id < AXP803_DCDC1 || id > AXP803_DCDC6) 1458 return -EINVAL; 1459 1460 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1); 1461 workmode <<= id - AXP803_DCDC1; 1462 break; 1463 1464 case AXP813_ID: 1465 if (id < AXP813_DCDC1 || id > AXP813_DCDC7) 1466 return -EINVAL; 1467 1468 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1); 1469 workmode <<= id - AXP813_DCDC1; 1470 break; 1471 1472 case AXP15060_ID: 1473 reg = AXP15060_DCDC_MODE_CTRL2; 1474 if (id < AXP15060_DCDC1 || id > AXP15060_DCDC6) 1475 return -EINVAL; 1476 1477 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP15060_DCDC1); 1478 workmode <<= id - AXP15060_DCDC1; 1479 break; 1480 1481 default: 1482 /* should not happen */ 1483 WARN_ON(1); 1484 return -EINVAL; 1485 } 1486 1487 return regmap_update_bits(rdev->regmap, reg, mask, workmode); 1488 } 1489 1490 /* 1491 * This function checks whether a regulator is part of a poly-phase 1492 * output setup based on the registers settings. Returns true if it is. 1493 */ 1494 static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id) 1495 { 1496 u32 reg = 0; 1497 1498 /* 1499 * Currently in our supported AXP variants, only AXP803, AXP806, 1500 * AXP813 and AXP15060 have polyphase regulators. 1501 */ 1502 switch (axp20x->variant) { 1503 case AXP803_ID: 1504 case AXP813_ID: 1505 regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, ®); 1506 1507 switch (id) { 1508 case AXP803_DCDC3: 1509 return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL); 1510 case AXP803_DCDC6: 1511 return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL); 1512 } 1513 break; 1514 1515 case AXP806_ID: 1516 regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, ®); 1517 1518 switch (id) { 1519 case AXP806_DCDCB: 1520 return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) == 1521 AXP806_DCDCAB_POLYPHASE_DUAL) || 1522 ((reg & AXP806_DCDCABC_POLYPHASE_MASK) == 1523 AXP806_DCDCABC_POLYPHASE_TRI)); 1524 case AXP806_DCDCC: 1525 return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) == 1526 AXP806_DCDCABC_POLYPHASE_TRI); 1527 case AXP806_DCDCE: 1528 return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL); 1529 } 1530 break; 1531 1532 case AXP15060_ID: 1533 regmap_read(axp20x->regmap, AXP15060_DCDC_MODE_CTRL1, ®); 1534 1535 switch (id) { 1536 case AXP15060_DCDC3: 1537 return !!(reg & AXP15060_DCDC23_POLYPHASE_DUAL_MASK); 1538 case AXP15060_DCDC6: 1539 return !!(reg & AXP15060_DCDC46_POLYPHASE_DUAL_MASK); 1540 } 1541 break; 1542 1543 case AXP323_ID: 1544 regmap_read(axp20x->regmap, AXP323_DCDC_MODE_CTRL2, ®); 1545 1546 switch (id) { 1547 case AXP313A_DCDC2: 1548 return !!(reg & BIT(1)); 1549 } 1550 break; 1551 1552 default: 1553 return false; 1554 } 1555 1556 return false; 1557 } 1558 1559 static int axp20x_regulator_probe(struct platform_device *pdev) 1560 { 1561 struct regulator_dev *rdev; 1562 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); 1563 const struct regulator_desc *regulators; 1564 struct regulator_config config = { 1565 .dev = pdev->dev.parent, 1566 .regmap = axp20x->regmap, 1567 .driver_data = axp20x, 1568 }; 1569 int ret, i, nregulators; 1570 u32 workmode; 1571 const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name; 1572 const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name; 1573 const char *aldo1_name = axp15060_regulators[AXP15060_ALDO1].name; 1574 bool drivevbus = false; 1575 1576 switch (axp20x->variant) { 1577 case AXP202_ID: 1578 case AXP209_ID: 1579 regulators = axp20x_regulators; 1580 nregulators = AXP20X_REG_ID_MAX; 1581 break; 1582 case AXP221_ID: 1583 case AXP223_ID: 1584 regulators = axp22x_regulators; 1585 nregulators = AXP22X_REG_ID_MAX; 1586 drivevbus = of_property_read_bool(pdev->dev.parent->of_node, 1587 "x-powers,drive-vbus-en"); 1588 break; 1589 case AXP313A_ID: 1590 case AXP323_ID: 1591 regulators = axp313a_regulators; 1592 nregulators = AXP313A_REG_ID_MAX; 1593 break; 1594 case AXP717_ID: 1595 regulators = axp717_regulators; 1596 nregulators = AXP717_REG_ID_MAX; 1597 break; 1598 case AXP803_ID: 1599 regulators = axp803_regulators; 1600 nregulators = AXP803_REG_ID_MAX; 1601 drivevbus = of_property_read_bool(pdev->dev.parent->of_node, 1602 "x-powers,drive-vbus-en"); 1603 break; 1604 case AXP806_ID: 1605 regulators = axp806_regulators; 1606 nregulators = AXP806_REG_ID_MAX; 1607 break; 1608 case AXP809_ID: 1609 regulators = axp809_regulators; 1610 nregulators = AXP809_REG_ID_MAX; 1611 break; 1612 case AXP813_ID: 1613 regulators = axp813_regulators; 1614 nregulators = AXP813_REG_ID_MAX; 1615 drivevbus = of_property_read_bool(pdev->dev.parent->of_node, 1616 "x-powers,drive-vbus-en"); 1617 break; 1618 case AXP15060_ID: 1619 regulators = axp15060_regulators; 1620 nregulators = AXP15060_REG_ID_MAX; 1621 break; 1622 default: 1623 dev_err(&pdev->dev, "Unsupported AXP variant: %d\n", 1624 axp20x->variant); 1625 return -EINVAL; 1626 } 1627 1628 /* This only sets the dcdc freq. Ignore any errors */ 1629 axp20x_regulator_parse_dt(pdev); 1630 1631 for (i = 0; i < nregulators; i++) { 1632 const struct regulator_desc *desc = ®ulators[i]; 1633 struct regulator_desc *new_desc; 1634 1635 /* 1636 * If this regulator is a slave in a poly-phase setup, 1637 * skip it, as its controls are bound to the master 1638 * regulator and won't work. 1639 */ 1640 if (axp20x_is_polyphase_slave(axp20x, i)) 1641 continue; 1642 1643 /* Support for AXP813's FLDO3 is not implemented */ 1644 if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3) 1645 continue; 1646 1647 /* 1648 * Regulators DC1SW, DC5LDO and RTCLDO on AXP15060 are 1649 * connected internally, so we have to handle their supply 1650 * names separately. 1651 * 1652 * We always register the regulators in proper sequence, 1653 * so the supply names are correctly read. See the last 1654 * part of this loop to see where we save the DT defined 1655 * name. 1656 */ 1657 if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) || 1658 (regulators == axp803_regulators && i == AXP803_DC1SW) || 1659 (regulators == axp809_regulators && i == AXP809_DC1SW) || 1660 (regulators == axp15060_regulators && i == AXP15060_SW)) { 1661 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), 1662 GFP_KERNEL); 1663 if (!new_desc) 1664 return -ENOMEM; 1665 1666 *new_desc = regulators[i]; 1667 new_desc->supply_name = dcdc1_name; 1668 desc = new_desc; 1669 } 1670 1671 if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) || 1672 (regulators == axp809_regulators && i == AXP809_DC5LDO) || 1673 (regulators == axp15060_regulators && i == AXP15060_CPUSLDO)) { 1674 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), 1675 GFP_KERNEL); 1676 if (!new_desc) 1677 return -ENOMEM; 1678 1679 *new_desc = regulators[i]; 1680 new_desc->supply_name = dcdc5_name; 1681 desc = new_desc; 1682 } 1683 1684 1685 if (regulators == axp15060_regulators && i == AXP15060_RTC_LDO) { 1686 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), 1687 GFP_KERNEL); 1688 if (!new_desc) 1689 return -ENOMEM; 1690 1691 *new_desc = regulators[i]; 1692 new_desc->supply_name = aldo1_name; 1693 desc = new_desc; 1694 } 1695 1696 rdev = devm_regulator_register(&pdev->dev, desc, &config); 1697 if (IS_ERR(rdev)) { 1698 dev_err(&pdev->dev, "Failed to register %s\n", 1699 regulators[i].name); 1700 1701 return PTR_ERR(rdev); 1702 } 1703 1704 ret = of_property_read_u32(rdev->dev.of_node, 1705 "x-powers,dcdc-workmode", 1706 &workmode); 1707 if (!ret) { 1708 if (axp20x_set_dcdc_workmode(rdev, i, workmode)) 1709 dev_err(&pdev->dev, "Failed to set workmode on %s\n", 1710 rdev->desc->name); 1711 } 1712 1713 /* 1714 * Save AXP22X DCDC1 / DCDC5 / AXP15060 ALDO1 regulator names for later. 1715 */ 1716 if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) || 1717 (regulators == axp809_regulators && i == AXP809_DCDC1) || 1718 (regulators == axp15060_regulators && i == AXP15060_DCDC1)) 1719 of_property_read_string(rdev->dev.of_node, 1720 "regulator-name", 1721 &dcdc1_name); 1722 1723 if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) || 1724 (regulators == axp809_regulators && i == AXP809_DCDC5) || 1725 (regulators == axp15060_regulators && i == AXP15060_DCDC5)) 1726 of_property_read_string(rdev->dev.of_node, 1727 "regulator-name", 1728 &dcdc5_name); 1729 1730 if (regulators == axp15060_regulators && i == AXP15060_ALDO1) 1731 of_property_read_string(rdev->dev.of_node, 1732 "regulator-name", 1733 &aldo1_name); 1734 } 1735 1736 if (drivevbus) { 1737 /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */ 1738 regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP, 1739 AXP22X_MISC_N_VBUSEN_FUNC, 0); 1740 rdev = devm_regulator_register(&pdev->dev, 1741 &axp22x_drivevbus_regulator, 1742 &config); 1743 if (IS_ERR(rdev)) { 1744 dev_err(&pdev->dev, "Failed to register drivevbus\n"); 1745 return PTR_ERR(rdev); 1746 } 1747 } 1748 1749 return 0; 1750 } 1751 1752 static struct platform_driver axp20x_regulator_driver = { 1753 .probe = axp20x_regulator_probe, 1754 .driver = { 1755 .name = "axp20x-regulator", 1756 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1757 }, 1758 }; 1759 1760 module_platform_driver(axp20x_regulator_driver); 1761 1762 MODULE_LICENSE("GPL v2"); 1763 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); 1764 MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC"); 1765 MODULE_ALIAS("platform:axp20x-regulator"); 1766