1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) ST-Ericsson SA 2010 4 * 5 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson 6 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson 7 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson 8 * 9 * AB8500 peripheral regulators 10 * 11 * AB8500 supports the following regulators: 12 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA 13 * 14 * AB8505 supports the following regulators: 15 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA 16 */ 17 #include <linux/init.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/err.h> 21 #include <linux/platform_device.h> 22 #include <linux/mfd/abx500.h> 23 #include <linux/mfd/abx500/ab8500.h> 24 #include <linux/of.h> 25 #include <linux/regulator/of_regulator.h> 26 #include <linux/regulator/driver.h> 27 #include <linux/regulator/machine.h> 28 #include <linux/slab.h> 29 30 /* AB8500 regulators */ 31 enum ab8500_regulator_id { 32 AB8500_LDO_AUX1, 33 AB8500_LDO_AUX2, 34 AB8500_LDO_AUX3, 35 AB8500_LDO_INTCORE, 36 AB8500_LDO_TVOUT, 37 AB8500_LDO_AUDIO, 38 AB8500_LDO_ANAMIC1, 39 AB8500_LDO_ANAMIC2, 40 AB8500_LDO_DMIC, 41 AB8500_LDO_ANA, 42 AB8500_NUM_REGULATORS, 43 }; 44 45 /* AB8505 regulators */ 46 enum ab8505_regulator_id { 47 AB8505_LDO_AUX1, 48 AB8505_LDO_AUX2, 49 AB8505_LDO_AUX3, 50 AB8505_LDO_AUX4, 51 AB8505_LDO_AUX5, 52 AB8505_LDO_AUX6, 53 AB8505_LDO_INTCORE, 54 AB8505_LDO_ADC, 55 AB8505_LDO_AUDIO, 56 AB8505_LDO_ANAMIC1, 57 AB8505_LDO_ANAMIC2, 58 AB8505_LDO_AUX8, 59 AB8505_LDO_ANA, 60 AB8505_NUM_REGULATORS, 61 }; 62 63 /* AB8500 registers */ 64 enum ab8500_regulator_reg { 65 AB8500_REGUREQUESTCTRL2, 66 AB8500_REGUREQUESTCTRL3, 67 AB8500_REGUREQUESTCTRL4, 68 AB8500_REGUSYSCLKREQ1HPVALID1, 69 AB8500_REGUSYSCLKREQ1HPVALID2, 70 AB8500_REGUHWHPREQ1VALID1, 71 AB8500_REGUHWHPREQ1VALID2, 72 AB8500_REGUHWHPREQ2VALID1, 73 AB8500_REGUHWHPREQ2VALID2, 74 AB8500_REGUSWHPREQVALID1, 75 AB8500_REGUSWHPREQVALID2, 76 AB8500_REGUSYSCLKREQVALID1, 77 AB8500_REGUSYSCLKREQVALID2, 78 AB8500_REGUMISC1, 79 AB8500_VAUDIOSUPPLY, 80 AB8500_REGUCTRL1VAMIC, 81 AB8500_VPLLVANAREGU, 82 AB8500_VREFDDR, 83 AB8500_EXTSUPPLYREGU, 84 AB8500_VAUX12REGU, 85 AB8500_VRF1VAUX3REGU, 86 AB8500_VAUX1SEL, 87 AB8500_VAUX2SEL, 88 AB8500_VRF1VAUX3SEL, 89 AB8500_REGUCTRL2SPARE, 90 AB8500_REGUCTRLDISCH, 91 AB8500_REGUCTRLDISCH2, 92 AB8500_NUM_REGULATOR_REGISTERS, 93 }; 94 95 /* AB8505 registers */ 96 enum ab8505_regulator_reg { 97 AB8505_REGUREQUESTCTRL1, 98 AB8505_REGUREQUESTCTRL2, 99 AB8505_REGUREQUESTCTRL3, 100 AB8505_REGUREQUESTCTRL4, 101 AB8505_REGUSYSCLKREQ1HPVALID1, 102 AB8505_REGUSYSCLKREQ1HPVALID2, 103 AB8505_REGUHWHPREQ1VALID1, 104 AB8505_REGUHWHPREQ1VALID2, 105 AB8505_REGUHWHPREQ2VALID1, 106 AB8505_REGUHWHPREQ2VALID2, 107 AB8505_REGUSWHPREQVALID1, 108 AB8505_REGUSWHPREQVALID2, 109 AB8505_REGUSYSCLKREQVALID1, 110 AB8505_REGUSYSCLKREQVALID2, 111 AB8505_REGUVAUX4REQVALID, 112 AB8505_REGUMISC1, 113 AB8505_VAUDIOSUPPLY, 114 AB8505_REGUCTRL1VAMIC, 115 AB8505_VSMPSAREGU, 116 AB8505_VSMPSBREGU, 117 AB8505_VSAFEREGU, /* NOTE! PRCMU register */ 118 AB8505_VPLLVANAREGU, 119 AB8505_EXTSUPPLYREGU, 120 AB8505_VAUX12REGU, 121 AB8505_VRF1VAUX3REGU, 122 AB8505_VSMPSASEL1, 123 AB8505_VSMPSASEL2, 124 AB8505_VSMPSASEL3, 125 AB8505_VSMPSBSEL1, 126 AB8505_VSMPSBSEL2, 127 AB8505_VSMPSBSEL3, 128 AB8505_VSAFESEL1, /* NOTE! PRCMU register */ 129 AB8505_VSAFESEL2, /* NOTE! PRCMU register */ 130 AB8505_VSAFESEL3, /* NOTE! PRCMU register */ 131 AB8505_VAUX1SEL, 132 AB8505_VAUX2SEL, 133 AB8505_VRF1VAUX3SEL, 134 AB8505_VAUX4REQCTRL, 135 AB8505_VAUX4REGU, 136 AB8505_VAUX4SEL, 137 AB8505_REGUCTRLDISCH, 138 AB8505_REGUCTRLDISCH2, 139 AB8505_REGUCTRLDISCH3, 140 AB8505_CTRLVAUX5, 141 AB8505_CTRLVAUX6, 142 AB8505_NUM_REGULATOR_REGISTERS, 143 }; 144 145 /** 146 * struct ab8500_shared_mode - is used when mode is shared between 147 * two regulators. 148 * @shared_regulator: pointer to the other sharing regulator 149 * @lp_mode_req: low power mode requested by this regulator 150 */ 151 struct ab8500_shared_mode { 152 struct ab8500_regulator_info *shared_regulator; 153 bool lp_mode_req; 154 }; 155 156 /** 157 * struct ab8500_regulator_info - ab8500 regulator information 158 * @dev: device pointer 159 * @desc: regulator description 160 * @shared_mode: used when mode is shared between two regulators 161 * @load_lp_uA: maximum load in idle (low power) mode 162 * @update_bank: bank to control on/off 163 * @update_reg: register to control on/off 164 * @update_mask: mask to enable/disable and set mode of regulator 165 * @update_val: bits holding the regulator current mode 166 * @update_val_idle: bits to enable the regulator in idle (low power) mode 167 * @update_val_normal: bits to enable the regulator in normal (high power) mode 168 * @mode_bank: bank with location of mode register 169 * @mode_reg: mode register 170 * @mode_mask: mask for setting mode 171 * @mode_val_idle: mode setting for low power 172 * @mode_val_normal: mode setting for normal power 173 * @voltage_bank: bank to control regulator voltage 174 * @voltage_reg: register to control regulator voltage 175 * @voltage_mask: mask to control regulator voltage 176 */ 177 struct ab8500_regulator_info { 178 struct device *dev; 179 struct regulator_desc desc; 180 struct ab8500_shared_mode *shared_mode; 181 int load_lp_uA; 182 u8 update_bank; 183 u8 update_reg; 184 u8 update_mask; 185 u8 update_val; 186 u8 update_val_idle; 187 u8 update_val_normal; 188 u8 mode_bank; 189 u8 mode_reg; 190 u8 mode_mask; 191 u8 mode_val_idle; 192 u8 mode_val_normal; 193 u8 voltage_bank; 194 u8 voltage_reg; 195 u8 voltage_mask; 196 }; 197 198 /* voltage tables for the vauxn/vintcore supplies */ 199 static const unsigned int ldo_vauxn_voltages[] = { 200 1100000, 201 1200000, 202 1300000, 203 1400000, 204 1500000, 205 1800000, 206 1850000, 207 1900000, 208 2500000, 209 2650000, 210 2700000, 211 2750000, 212 2800000, 213 2900000, 214 3000000, 215 3300000, 216 }; 217 218 static const unsigned int ldo_vaux3_voltages[] = { 219 1200000, 220 1500000, 221 1800000, 222 2100000, 223 2500000, 224 2750000, 225 2790000, 226 2910000, 227 }; 228 229 static const unsigned int ldo_vaux56_voltages[] = { 230 1800000, 231 1050000, 232 1100000, 233 1200000, 234 1500000, 235 2200000, 236 2500000, 237 2790000, 238 }; 239 240 static const unsigned int ldo_vintcore_voltages[] = { 241 1200000, 242 1225000, 243 1250000, 244 1275000, 245 1300000, 246 1325000, 247 1350000, 248 }; 249 250 static const unsigned int fixed_1200000_voltage[] = { 251 1200000, 252 }; 253 254 static const unsigned int fixed_1800000_voltage[] = { 255 1800000, 256 }; 257 258 static const unsigned int fixed_2000000_voltage[] = { 259 2000000, 260 }; 261 262 static const unsigned int fixed_2050000_voltage[] = { 263 2050000, 264 }; 265 266 static const unsigned int ldo_vana_voltages[] = { 267 1050000, 268 1075000, 269 1100000, 270 1125000, 271 1150000, 272 1175000, 273 1200000, 274 1225000, 275 }; 276 277 static const unsigned int ldo_vaudio_voltages[] = { 278 2000000, 279 2100000, 280 2200000, 281 2300000, 282 2400000, 283 2500000, 284 2600000, 285 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */ 286 }; 287 288 static DEFINE_MUTEX(shared_mode_mutex); 289 static struct ab8500_shared_mode ldo_anamic1_shared; 290 static struct ab8500_shared_mode ldo_anamic2_shared; 291 292 static int ab8500_regulator_enable(struct regulator_dev *rdev) 293 { 294 int ret; 295 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 296 297 if (info == NULL) { 298 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 299 return -EINVAL; 300 } 301 302 ret = abx500_mask_and_set_register_interruptible(info->dev, 303 info->update_bank, info->update_reg, 304 info->update_mask, info->update_val); 305 if (ret < 0) { 306 dev_err(rdev_get_dev(rdev), 307 "couldn't set enable bits for regulator\n"); 308 return ret; 309 } 310 311 dev_vdbg(rdev_get_dev(rdev), 312 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", 313 info->desc.name, info->update_bank, info->update_reg, 314 info->update_mask, info->update_val); 315 316 return ret; 317 } 318 319 static int ab8500_regulator_disable(struct regulator_dev *rdev) 320 { 321 int ret; 322 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 323 324 if (info == NULL) { 325 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 326 return -EINVAL; 327 } 328 329 ret = abx500_mask_and_set_register_interruptible(info->dev, 330 info->update_bank, info->update_reg, 331 info->update_mask, 0x0); 332 if (ret < 0) { 333 dev_err(rdev_get_dev(rdev), 334 "couldn't set disable bits for regulator\n"); 335 return ret; 336 } 337 338 dev_vdbg(rdev_get_dev(rdev), 339 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", 340 info->desc.name, info->update_bank, info->update_reg, 341 info->update_mask, 0x0); 342 343 return ret; 344 } 345 346 static int ab8500_regulator_is_enabled(struct regulator_dev *rdev) 347 { 348 int ret; 349 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 350 u8 regval; 351 352 if (info == NULL) { 353 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 354 return -EINVAL; 355 } 356 357 ret = abx500_get_register_interruptible(info->dev, 358 info->update_bank, info->update_reg, ®val); 359 if (ret < 0) { 360 dev_err(rdev_get_dev(rdev), 361 "couldn't read 0x%x register\n", info->update_reg); 362 return ret; 363 } 364 365 dev_vdbg(rdev_get_dev(rdev), 366 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x," 367 " 0x%x\n", 368 info->desc.name, info->update_bank, info->update_reg, 369 info->update_mask, regval); 370 371 if (regval & info->update_mask) 372 return 1; 373 else 374 return 0; 375 } 376 377 static unsigned int ab8500_regulator_get_optimum_mode( 378 struct regulator_dev *rdev, int input_uV, 379 int output_uV, int load_uA) 380 { 381 unsigned int mode; 382 383 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 384 385 if (info == NULL) { 386 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 387 return -EINVAL; 388 } 389 390 if (load_uA <= info->load_lp_uA) 391 mode = REGULATOR_MODE_IDLE; 392 else 393 mode = REGULATOR_MODE_NORMAL; 394 395 return mode; 396 } 397 398 static int ab8500_regulator_set_mode(struct regulator_dev *rdev, 399 unsigned int mode) 400 { 401 int ret = 0; 402 u8 bank, reg, mask, val; 403 bool lp_mode_req = false; 404 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 405 406 if (info == NULL) { 407 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 408 return -EINVAL; 409 } 410 411 if (info->mode_mask) { 412 bank = info->mode_bank; 413 reg = info->mode_reg; 414 mask = info->mode_mask; 415 } else { 416 bank = info->update_bank; 417 reg = info->update_reg; 418 mask = info->update_mask; 419 } 420 421 if (info->shared_mode) 422 mutex_lock(&shared_mode_mutex); 423 424 switch (mode) { 425 case REGULATOR_MODE_NORMAL: 426 if (info->shared_mode) 427 lp_mode_req = false; 428 429 if (info->mode_mask) 430 val = info->mode_val_normal; 431 else 432 val = info->update_val_normal; 433 break; 434 case REGULATOR_MODE_IDLE: 435 if (info->shared_mode) { 436 struct ab8500_regulator_info *shared_regulator; 437 438 shared_regulator = info->shared_mode->shared_regulator; 439 if (!shared_regulator->shared_mode->lp_mode_req) { 440 /* Other regulator prevent LP mode */ 441 info->shared_mode->lp_mode_req = true; 442 goto out_unlock; 443 } 444 445 lp_mode_req = true; 446 } 447 448 if (info->mode_mask) 449 val = info->mode_val_idle; 450 else 451 val = info->update_val_idle; 452 break; 453 default: 454 ret = -EINVAL; 455 goto out_unlock; 456 } 457 458 if (info->mode_mask || ab8500_regulator_is_enabled(rdev)) { 459 ret = abx500_mask_and_set_register_interruptible(info->dev, 460 bank, reg, mask, val); 461 if (ret < 0) { 462 dev_err(rdev_get_dev(rdev), 463 "couldn't set regulator mode\n"); 464 goto out_unlock; 465 } 466 467 dev_vdbg(rdev_get_dev(rdev), 468 "%s-set_mode (bank, reg, mask, value): " 469 "0x%x, 0x%x, 0x%x, 0x%x\n", 470 info->desc.name, bank, reg, 471 mask, val); 472 } 473 474 if (!info->mode_mask) 475 info->update_val = val; 476 477 if (info->shared_mode) 478 info->shared_mode->lp_mode_req = lp_mode_req; 479 480 out_unlock: 481 if (info->shared_mode) 482 mutex_unlock(&shared_mode_mutex); 483 484 return ret; 485 } 486 487 static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev) 488 { 489 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 490 int ret; 491 u8 val; 492 u8 val_normal; 493 u8 val_idle; 494 495 if (info == NULL) { 496 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 497 return -EINVAL; 498 } 499 500 /* Need special handling for shared mode */ 501 if (info->shared_mode) { 502 if (info->shared_mode->lp_mode_req) 503 return REGULATOR_MODE_IDLE; 504 else 505 return REGULATOR_MODE_NORMAL; 506 } 507 508 if (info->mode_mask) { 509 /* Dedicated register for handling mode */ 510 ret = abx500_get_register_interruptible(info->dev, 511 info->mode_bank, info->mode_reg, &val); 512 val = val & info->mode_mask; 513 514 val_normal = info->mode_val_normal; 515 val_idle = info->mode_val_idle; 516 } else { 517 /* Mode register same as enable register */ 518 val = info->update_val; 519 val_normal = info->update_val_normal; 520 val_idle = info->update_val_idle; 521 } 522 523 if (val == val_normal) 524 ret = REGULATOR_MODE_NORMAL; 525 else if (val == val_idle) 526 ret = REGULATOR_MODE_IDLE; 527 else 528 ret = -EINVAL; 529 530 return ret; 531 } 532 533 static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev) 534 { 535 int ret, voltage_shift; 536 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 537 u8 regval; 538 539 if (info == NULL) { 540 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 541 return -EINVAL; 542 } 543 544 voltage_shift = ffs(info->voltage_mask) - 1; 545 546 ret = abx500_get_register_interruptible(info->dev, 547 info->voltage_bank, info->voltage_reg, ®val); 548 if (ret < 0) { 549 dev_err(rdev_get_dev(rdev), 550 "couldn't read voltage reg for regulator\n"); 551 return ret; 552 } 553 554 dev_vdbg(rdev_get_dev(rdev), 555 "%s-get_voltage (bank, reg, mask, shift, value): " 556 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", 557 info->desc.name, info->voltage_bank, 558 info->voltage_reg, info->voltage_mask, 559 voltage_shift, regval); 560 561 return (regval & info->voltage_mask) >> voltage_shift; 562 } 563 564 static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev, 565 unsigned selector) 566 { 567 int ret, voltage_shift; 568 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); 569 u8 regval; 570 571 if (info == NULL) { 572 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); 573 return -EINVAL; 574 } 575 576 voltage_shift = ffs(info->voltage_mask) - 1; 577 578 /* set the registers for the request */ 579 regval = (u8)selector << voltage_shift; 580 ret = abx500_mask_and_set_register_interruptible(info->dev, 581 info->voltage_bank, info->voltage_reg, 582 info->voltage_mask, regval); 583 if (ret < 0) 584 dev_err(rdev_get_dev(rdev), 585 "couldn't set voltage reg for regulator\n"); 586 587 dev_vdbg(rdev_get_dev(rdev), 588 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x," 589 " 0x%x\n", 590 info->desc.name, info->voltage_bank, info->voltage_reg, 591 info->voltage_mask, regval); 592 593 return ret; 594 } 595 596 static const struct regulator_ops ab8500_regulator_volt_mode_ops = { 597 .enable = ab8500_regulator_enable, 598 .disable = ab8500_regulator_disable, 599 .is_enabled = ab8500_regulator_is_enabled, 600 .get_optimum_mode = ab8500_regulator_get_optimum_mode, 601 .set_mode = ab8500_regulator_set_mode, 602 .get_mode = ab8500_regulator_get_mode, 603 .get_voltage_sel = ab8500_regulator_get_voltage_sel, 604 .set_voltage_sel = ab8500_regulator_set_voltage_sel, 605 .list_voltage = regulator_list_voltage_table, 606 }; 607 608 static const struct regulator_ops ab8500_regulator_volt_ops = { 609 .enable = ab8500_regulator_enable, 610 .disable = ab8500_regulator_disable, 611 .is_enabled = ab8500_regulator_is_enabled, 612 .get_voltage_sel = ab8500_regulator_get_voltage_sel, 613 .set_voltage_sel = ab8500_regulator_set_voltage_sel, 614 .list_voltage = regulator_list_voltage_table, 615 }; 616 617 static const struct regulator_ops ab8500_regulator_mode_ops = { 618 .enable = ab8500_regulator_enable, 619 .disable = ab8500_regulator_disable, 620 .is_enabled = ab8500_regulator_is_enabled, 621 .get_optimum_mode = ab8500_regulator_get_optimum_mode, 622 .set_mode = ab8500_regulator_set_mode, 623 .get_mode = ab8500_regulator_get_mode, 624 .list_voltage = regulator_list_voltage_table, 625 }; 626 627 static const struct regulator_ops ab8500_regulator_ops = { 628 .enable = ab8500_regulator_enable, 629 .disable = ab8500_regulator_disable, 630 .is_enabled = ab8500_regulator_is_enabled, 631 .list_voltage = regulator_list_voltage_table, 632 }; 633 634 static const struct regulator_ops ab8500_regulator_anamic_mode_ops = { 635 .enable = ab8500_regulator_enable, 636 .disable = ab8500_regulator_disable, 637 .is_enabled = ab8500_regulator_is_enabled, 638 .set_mode = ab8500_regulator_set_mode, 639 .get_mode = ab8500_regulator_get_mode, 640 .list_voltage = regulator_list_voltage_table, 641 }; 642 643 /* AB8500 regulator information */ 644 static struct ab8500_regulator_info 645 ab8500_regulator_info[AB8500_NUM_REGULATORS] = { 646 /* 647 * Variable Voltage Regulators 648 * name, min mV, max mV, 649 * update bank, reg, mask, enable val 650 * volt bank, reg, mask 651 */ 652 [AB8500_LDO_AUX1] = { 653 .desc = { 654 .name = "LDO-AUX1", 655 .ops = &ab8500_regulator_volt_mode_ops, 656 .type = REGULATOR_VOLTAGE, 657 .id = AB8500_LDO_AUX1, 658 .owner = THIS_MODULE, 659 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 660 .volt_table = ldo_vauxn_voltages, 661 .enable_time = 200, 662 .supply_name = "vin", 663 }, 664 .load_lp_uA = 5000, 665 .update_bank = 0x04, 666 .update_reg = 0x09, 667 .update_mask = 0x03, 668 .update_val = 0x01, 669 .update_val_idle = 0x03, 670 .update_val_normal = 0x01, 671 .voltage_bank = 0x04, 672 .voltage_reg = 0x1f, 673 .voltage_mask = 0x0f, 674 }, 675 [AB8500_LDO_AUX2] = { 676 .desc = { 677 .name = "LDO-AUX2", 678 .ops = &ab8500_regulator_volt_mode_ops, 679 .type = REGULATOR_VOLTAGE, 680 .id = AB8500_LDO_AUX2, 681 .owner = THIS_MODULE, 682 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 683 .volt_table = ldo_vauxn_voltages, 684 .enable_time = 200, 685 .supply_name = "vin", 686 }, 687 .load_lp_uA = 5000, 688 .update_bank = 0x04, 689 .update_reg = 0x09, 690 .update_mask = 0x0c, 691 .update_val = 0x04, 692 .update_val_idle = 0x0c, 693 .update_val_normal = 0x04, 694 .voltage_bank = 0x04, 695 .voltage_reg = 0x20, 696 .voltage_mask = 0x0f, 697 }, 698 [AB8500_LDO_AUX3] = { 699 .desc = { 700 .name = "LDO-AUX3", 701 .ops = &ab8500_regulator_volt_mode_ops, 702 .type = REGULATOR_VOLTAGE, 703 .id = AB8500_LDO_AUX3, 704 .owner = THIS_MODULE, 705 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages), 706 .volt_table = ldo_vaux3_voltages, 707 .enable_time = 450, 708 .supply_name = "vin", 709 }, 710 .load_lp_uA = 5000, 711 .update_bank = 0x04, 712 .update_reg = 0x0a, 713 .update_mask = 0x03, 714 .update_val = 0x01, 715 .update_val_idle = 0x03, 716 .update_val_normal = 0x01, 717 .voltage_bank = 0x04, 718 .voltage_reg = 0x21, 719 .voltage_mask = 0x07, 720 }, 721 [AB8500_LDO_INTCORE] = { 722 .desc = { 723 .name = "LDO-INTCORE", 724 .ops = &ab8500_regulator_volt_mode_ops, 725 .type = REGULATOR_VOLTAGE, 726 .id = AB8500_LDO_INTCORE, 727 .owner = THIS_MODULE, 728 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), 729 .volt_table = ldo_vintcore_voltages, 730 .enable_time = 750, 731 }, 732 .load_lp_uA = 5000, 733 .update_bank = 0x03, 734 .update_reg = 0x80, 735 .update_mask = 0x44, 736 .update_val = 0x44, 737 .update_val_idle = 0x44, 738 .update_val_normal = 0x04, 739 .voltage_bank = 0x03, 740 .voltage_reg = 0x80, 741 .voltage_mask = 0x38, 742 }, 743 744 /* 745 * Fixed Voltage Regulators 746 * name, fixed mV, 747 * update bank, reg, mask, enable val 748 */ 749 [AB8500_LDO_TVOUT] = { 750 .desc = { 751 .name = "LDO-TVOUT", 752 .ops = &ab8500_regulator_mode_ops, 753 .type = REGULATOR_VOLTAGE, 754 .id = AB8500_LDO_TVOUT, 755 .owner = THIS_MODULE, 756 .n_voltages = 1, 757 .volt_table = fixed_2000000_voltage, 758 .enable_time = 500, 759 }, 760 .load_lp_uA = 1000, 761 .update_bank = 0x03, 762 .update_reg = 0x80, 763 .update_mask = 0x82, 764 .update_val = 0x02, 765 .update_val_idle = 0x82, 766 .update_val_normal = 0x02, 767 }, 768 [AB8500_LDO_AUDIO] = { 769 .desc = { 770 .name = "LDO-AUDIO", 771 .ops = &ab8500_regulator_ops, 772 .type = REGULATOR_VOLTAGE, 773 .id = AB8500_LDO_AUDIO, 774 .owner = THIS_MODULE, 775 .n_voltages = 1, 776 .enable_time = 140, 777 .volt_table = fixed_2000000_voltage, 778 }, 779 .update_bank = 0x03, 780 .update_reg = 0x83, 781 .update_mask = 0x02, 782 .update_val = 0x02, 783 }, 784 [AB8500_LDO_ANAMIC1] = { 785 .desc = { 786 .name = "LDO-ANAMIC1", 787 .ops = &ab8500_regulator_ops, 788 .type = REGULATOR_VOLTAGE, 789 .id = AB8500_LDO_ANAMIC1, 790 .owner = THIS_MODULE, 791 .n_voltages = 1, 792 .enable_time = 500, 793 .volt_table = fixed_2050000_voltage, 794 }, 795 .update_bank = 0x03, 796 .update_reg = 0x83, 797 .update_mask = 0x08, 798 .update_val = 0x08, 799 }, 800 [AB8500_LDO_ANAMIC2] = { 801 .desc = { 802 .name = "LDO-ANAMIC2", 803 .ops = &ab8500_regulator_ops, 804 .type = REGULATOR_VOLTAGE, 805 .id = AB8500_LDO_ANAMIC2, 806 .owner = THIS_MODULE, 807 .n_voltages = 1, 808 .enable_time = 500, 809 .volt_table = fixed_2050000_voltage, 810 }, 811 .update_bank = 0x03, 812 .update_reg = 0x83, 813 .update_mask = 0x10, 814 .update_val = 0x10, 815 }, 816 [AB8500_LDO_DMIC] = { 817 .desc = { 818 .name = "LDO-DMIC", 819 .ops = &ab8500_regulator_ops, 820 .type = REGULATOR_VOLTAGE, 821 .id = AB8500_LDO_DMIC, 822 .owner = THIS_MODULE, 823 .n_voltages = 1, 824 .enable_time = 420, 825 .volt_table = fixed_1800000_voltage, 826 }, 827 .update_bank = 0x03, 828 .update_reg = 0x83, 829 .update_mask = 0x04, 830 .update_val = 0x04, 831 }, 832 833 /* 834 * Regulators with fixed voltage and normal/idle modes 835 */ 836 [AB8500_LDO_ANA] = { 837 .desc = { 838 .name = "LDO-ANA", 839 .ops = &ab8500_regulator_mode_ops, 840 .type = REGULATOR_VOLTAGE, 841 .id = AB8500_LDO_ANA, 842 .owner = THIS_MODULE, 843 .n_voltages = 1, 844 .enable_time = 140, 845 .volt_table = fixed_1200000_voltage, 846 }, 847 .load_lp_uA = 1000, 848 .update_bank = 0x04, 849 .update_reg = 0x06, 850 .update_mask = 0x0c, 851 .update_val = 0x04, 852 .update_val_idle = 0x0c, 853 .update_val_normal = 0x04, 854 }, 855 }; 856 857 /* AB8505 regulator information */ 858 static struct ab8500_regulator_info 859 ab8505_regulator_info[AB8505_NUM_REGULATORS] = { 860 /* 861 * Variable Voltage Regulators 862 * name, min mV, max mV, 863 * update bank, reg, mask, enable val 864 * volt bank, reg, mask 865 */ 866 [AB8505_LDO_AUX1] = { 867 .desc = { 868 .name = "LDO-AUX1", 869 .ops = &ab8500_regulator_volt_mode_ops, 870 .type = REGULATOR_VOLTAGE, 871 .id = AB8505_LDO_AUX1, 872 .owner = THIS_MODULE, 873 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 874 .volt_table = ldo_vauxn_voltages, 875 }, 876 .load_lp_uA = 5000, 877 .update_bank = 0x04, 878 .update_reg = 0x09, 879 .update_mask = 0x03, 880 .update_val = 0x01, 881 .update_val_idle = 0x03, 882 .update_val_normal = 0x01, 883 .voltage_bank = 0x04, 884 .voltage_reg = 0x1f, 885 .voltage_mask = 0x0f, 886 }, 887 [AB8505_LDO_AUX2] = { 888 .desc = { 889 .name = "LDO-AUX2", 890 .ops = &ab8500_regulator_volt_mode_ops, 891 .type = REGULATOR_VOLTAGE, 892 .id = AB8505_LDO_AUX2, 893 .owner = THIS_MODULE, 894 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 895 .volt_table = ldo_vauxn_voltages, 896 }, 897 .load_lp_uA = 5000, 898 .update_bank = 0x04, 899 .update_reg = 0x09, 900 .update_mask = 0x0c, 901 .update_val = 0x04, 902 .update_val_idle = 0x0c, 903 .update_val_normal = 0x04, 904 .voltage_bank = 0x04, 905 .voltage_reg = 0x20, 906 .voltage_mask = 0x0f, 907 }, 908 [AB8505_LDO_AUX3] = { 909 .desc = { 910 .name = "LDO-AUX3", 911 .ops = &ab8500_regulator_volt_mode_ops, 912 .type = REGULATOR_VOLTAGE, 913 .id = AB8505_LDO_AUX3, 914 .owner = THIS_MODULE, 915 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages), 916 .volt_table = ldo_vaux3_voltages, 917 }, 918 .load_lp_uA = 5000, 919 .update_bank = 0x04, 920 .update_reg = 0x0a, 921 .update_mask = 0x03, 922 .update_val = 0x01, 923 .update_val_idle = 0x03, 924 .update_val_normal = 0x01, 925 .voltage_bank = 0x04, 926 .voltage_reg = 0x21, 927 .voltage_mask = 0x07, 928 }, 929 [AB8505_LDO_AUX4] = { 930 .desc = { 931 .name = "LDO-AUX4", 932 .ops = &ab8500_regulator_volt_mode_ops, 933 .type = REGULATOR_VOLTAGE, 934 .id = AB8505_LDO_AUX4, 935 .owner = THIS_MODULE, 936 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), 937 .volt_table = ldo_vauxn_voltages, 938 }, 939 .load_lp_uA = 5000, 940 /* values for Vaux4Regu register */ 941 .update_bank = 0x04, 942 .update_reg = 0x2e, 943 .update_mask = 0x03, 944 .update_val = 0x01, 945 .update_val_idle = 0x03, 946 .update_val_normal = 0x01, 947 /* values for Vaux4SEL register */ 948 .voltage_bank = 0x04, 949 .voltage_reg = 0x2f, 950 .voltage_mask = 0x0f, 951 }, 952 [AB8505_LDO_AUX5] = { 953 .desc = { 954 .name = "LDO-AUX5", 955 .ops = &ab8500_regulator_volt_mode_ops, 956 .type = REGULATOR_VOLTAGE, 957 .id = AB8505_LDO_AUX5, 958 .owner = THIS_MODULE, 959 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages), 960 .volt_table = ldo_vaux56_voltages, 961 }, 962 .load_lp_uA = 2000, 963 /* values for CtrlVaux5 register */ 964 .update_bank = 0x01, 965 .update_reg = 0x55, 966 .update_mask = 0x18, 967 .update_val = 0x10, 968 .update_val_idle = 0x18, 969 .update_val_normal = 0x10, 970 .voltage_bank = 0x01, 971 .voltage_reg = 0x55, 972 .voltage_mask = 0x07, 973 }, 974 [AB8505_LDO_AUX6] = { 975 .desc = { 976 .name = "LDO-AUX6", 977 .ops = &ab8500_regulator_volt_mode_ops, 978 .type = REGULATOR_VOLTAGE, 979 .id = AB8505_LDO_AUX6, 980 .owner = THIS_MODULE, 981 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages), 982 .volt_table = ldo_vaux56_voltages, 983 }, 984 .load_lp_uA = 2000, 985 /* values for CtrlVaux6 register */ 986 .update_bank = 0x01, 987 .update_reg = 0x56, 988 .update_mask = 0x18, 989 .update_val = 0x10, 990 .update_val_idle = 0x18, 991 .update_val_normal = 0x10, 992 .voltage_bank = 0x01, 993 .voltage_reg = 0x56, 994 .voltage_mask = 0x07, 995 }, 996 [AB8505_LDO_INTCORE] = { 997 .desc = { 998 .name = "LDO-INTCORE", 999 .ops = &ab8500_regulator_volt_mode_ops, 1000 .type = REGULATOR_VOLTAGE, 1001 .id = AB8505_LDO_INTCORE, 1002 .owner = THIS_MODULE, 1003 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), 1004 .volt_table = ldo_vintcore_voltages, 1005 }, 1006 .load_lp_uA = 5000, 1007 .update_bank = 0x03, 1008 .update_reg = 0x80, 1009 .update_mask = 0x44, 1010 .update_val = 0x04, 1011 .update_val_idle = 0x44, 1012 .update_val_normal = 0x04, 1013 .voltage_bank = 0x03, 1014 .voltage_reg = 0x80, 1015 .voltage_mask = 0x38, 1016 }, 1017 1018 /* 1019 * Fixed Voltage Regulators 1020 * name, fixed mV, 1021 * update bank, reg, mask, enable val 1022 */ 1023 [AB8505_LDO_ADC] = { 1024 .desc = { 1025 .name = "LDO-ADC", 1026 .ops = &ab8500_regulator_mode_ops, 1027 .type = REGULATOR_VOLTAGE, 1028 .id = AB8505_LDO_ADC, 1029 .owner = THIS_MODULE, 1030 .n_voltages = 1, 1031 .volt_table = fixed_2000000_voltage, 1032 .enable_time = 10000, 1033 }, 1034 .load_lp_uA = 1000, 1035 .update_bank = 0x03, 1036 .update_reg = 0x80, 1037 .update_mask = 0x82, 1038 .update_val = 0x02, 1039 .update_val_idle = 0x82, 1040 .update_val_normal = 0x02, 1041 }, 1042 [AB8505_LDO_AUDIO] = { 1043 .desc = { 1044 .name = "LDO-AUDIO", 1045 .ops = &ab8500_regulator_volt_ops, 1046 .type = REGULATOR_VOLTAGE, 1047 .id = AB8505_LDO_AUDIO, 1048 .owner = THIS_MODULE, 1049 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages), 1050 .volt_table = ldo_vaudio_voltages, 1051 }, 1052 .update_bank = 0x03, 1053 .update_reg = 0x83, 1054 .update_mask = 0x02, 1055 .update_val = 0x02, 1056 .voltage_bank = 0x01, 1057 .voltage_reg = 0x57, 1058 .voltage_mask = 0x70, 1059 }, 1060 [AB8505_LDO_ANAMIC1] = { 1061 .desc = { 1062 .name = "LDO-ANAMIC1", 1063 .ops = &ab8500_regulator_anamic_mode_ops, 1064 .type = REGULATOR_VOLTAGE, 1065 .id = AB8505_LDO_ANAMIC1, 1066 .owner = THIS_MODULE, 1067 .n_voltages = 1, 1068 .volt_table = fixed_2050000_voltage, 1069 }, 1070 .shared_mode = &ldo_anamic1_shared, 1071 .update_bank = 0x03, 1072 .update_reg = 0x83, 1073 .update_mask = 0x08, 1074 .update_val = 0x08, 1075 .mode_bank = 0x01, 1076 .mode_reg = 0x54, 1077 .mode_mask = 0x04, 1078 .mode_val_idle = 0x04, 1079 .mode_val_normal = 0x00, 1080 }, 1081 [AB8505_LDO_ANAMIC2] = { 1082 .desc = { 1083 .name = "LDO-ANAMIC2", 1084 .ops = &ab8500_regulator_anamic_mode_ops, 1085 .type = REGULATOR_VOLTAGE, 1086 .id = AB8505_LDO_ANAMIC2, 1087 .owner = THIS_MODULE, 1088 .n_voltages = 1, 1089 .volt_table = fixed_2050000_voltage, 1090 }, 1091 .shared_mode = &ldo_anamic2_shared, 1092 .update_bank = 0x03, 1093 .update_reg = 0x83, 1094 .update_mask = 0x10, 1095 .update_val = 0x10, 1096 .mode_bank = 0x01, 1097 .mode_reg = 0x54, 1098 .mode_mask = 0x04, 1099 .mode_val_idle = 0x04, 1100 .mode_val_normal = 0x00, 1101 }, 1102 [AB8505_LDO_AUX8] = { 1103 .desc = { 1104 .name = "LDO-AUX8", 1105 .ops = &ab8500_regulator_ops, 1106 .type = REGULATOR_VOLTAGE, 1107 .id = AB8505_LDO_AUX8, 1108 .owner = THIS_MODULE, 1109 .n_voltages = 1, 1110 .volt_table = fixed_1800000_voltage, 1111 }, 1112 .update_bank = 0x03, 1113 .update_reg = 0x83, 1114 .update_mask = 0x04, 1115 .update_val = 0x04, 1116 }, 1117 /* 1118 * Regulators with fixed voltage and normal/idle modes 1119 */ 1120 [AB8505_LDO_ANA] = { 1121 .desc = { 1122 .name = "LDO-ANA", 1123 .ops = &ab8500_regulator_volt_mode_ops, 1124 .type = REGULATOR_VOLTAGE, 1125 .id = AB8505_LDO_ANA, 1126 .owner = THIS_MODULE, 1127 .n_voltages = ARRAY_SIZE(ldo_vana_voltages), 1128 .volt_table = ldo_vana_voltages, 1129 }, 1130 .load_lp_uA = 1000, 1131 .update_bank = 0x04, 1132 .update_reg = 0x06, 1133 .update_mask = 0x0c, 1134 .update_val = 0x04, 1135 .update_val_idle = 0x0c, 1136 .update_val_normal = 0x04, 1137 .voltage_bank = 0x04, 1138 .voltage_reg = 0x29, 1139 .voltage_mask = 0x7, 1140 }, 1141 }; 1142 1143 static struct ab8500_shared_mode ldo_anamic1_shared = { 1144 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2], 1145 }; 1146 1147 static struct ab8500_shared_mode ldo_anamic2_shared = { 1148 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1], 1149 }; 1150 1151 struct ab8500_reg_init { 1152 u8 bank; 1153 u8 addr; 1154 u8 mask; 1155 }; 1156 1157 #define REG_INIT(_id, _bank, _addr, _mask) \ 1158 [_id] = { \ 1159 .bank = _bank, \ 1160 .addr = _addr, \ 1161 .mask = _mask, \ 1162 } 1163 1164 /* AB8500 register init */ 1165 static struct ab8500_reg_init ab8500_reg_init[] = { 1166 /* 1167 * 0x30, VanaRequestCtrl 1168 * 0xc0, VextSupply1RequestCtrl 1169 */ 1170 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0), 1171 /* 1172 * 0x03, VextSupply2RequestCtrl 1173 * 0x0c, VextSupply3RequestCtrl 1174 * 0x30, Vaux1RequestCtrl 1175 * 0xc0, Vaux2RequestCtrl 1176 */ 1177 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff), 1178 /* 1179 * 0x03, Vaux3RequestCtrl 1180 * 0x04, SwHPReq 1181 */ 1182 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), 1183 /* 1184 * 0x08, VanaSysClkReq1HPValid 1185 * 0x20, Vaux1SysClkReq1HPValid 1186 * 0x40, Vaux2SysClkReq1HPValid 1187 * 0x80, Vaux3SysClkReq1HPValid 1188 */ 1189 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8), 1190 /* 1191 * 0x10, VextSupply1SysClkReq1HPValid 1192 * 0x20, VextSupply2SysClkReq1HPValid 1193 * 0x40, VextSupply3SysClkReq1HPValid 1194 */ 1195 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70), 1196 /* 1197 * 0x08, VanaHwHPReq1Valid 1198 * 0x20, Vaux1HwHPReq1Valid 1199 * 0x40, Vaux2HwHPReq1Valid 1200 * 0x80, Vaux3HwHPReq1Valid 1201 */ 1202 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8), 1203 /* 1204 * 0x01, VextSupply1HwHPReq1Valid 1205 * 0x02, VextSupply2HwHPReq1Valid 1206 * 0x04, VextSupply3HwHPReq1Valid 1207 */ 1208 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07), 1209 /* 1210 * 0x08, VanaHwHPReq2Valid 1211 * 0x20, Vaux1HwHPReq2Valid 1212 * 0x40, Vaux2HwHPReq2Valid 1213 * 0x80, Vaux3HwHPReq2Valid 1214 */ 1215 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8), 1216 /* 1217 * 0x01, VextSupply1HwHPReq2Valid 1218 * 0x02, VextSupply2HwHPReq2Valid 1219 * 0x04, VextSupply3HwHPReq2Valid 1220 */ 1221 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07), 1222 /* 1223 * 0x20, VanaSwHPReqValid 1224 * 0x80, Vaux1SwHPReqValid 1225 */ 1226 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0), 1227 /* 1228 * 0x01, Vaux2SwHPReqValid 1229 * 0x02, Vaux3SwHPReqValid 1230 * 0x04, VextSupply1SwHPReqValid 1231 * 0x08, VextSupply2SwHPReqValid 1232 * 0x10, VextSupply3SwHPReqValid 1233 */ 1234 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f), 1235 /* 1236 * 0x02, SysClkReq2Valid1 1237 * 0x04, SysClkReq3Valid1 1238 * 0x08, SysClkReq4Valid1 1239 * 0x10, SysClkReq5Valid1 1240 * 0x20, SysClkReq6Valid1 1241 * 0x40, SysClkReq7Valid1 1242 * 0x80, SysClkReq8Valid1 1243 */ 1244 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe), 1245 /* 1246 * 0x02, SysClkReq2Valid2 1247 * 0x04, SysClkReq3Valid2 1248 * 0x08, SysClkReq4Valid2 1249 * 0x10, SysClkReq5Valid2 1250 * 0x20, SysClkReq6Valid2 1251 * 0x40, SysClkReq7Valid2 1252 * 0x80, SysClkReq8Valid2 1253 */ 1254 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe), 1255 /* 1256 * 0x02, VTVoutEna 1257 * 0x04, Vintcore12Ena 1258 * 0x38, Vintcore12Sel 1259 * 0x40, Vintcore12LP 1260 * 0x80, VTVoutLP 1261 */ 1262 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe), 1263 /* 1264 * 0x02, VaudioEna 1265 * 0x04, VdmicEna 1266 * 0x08, Vamic1Ena 1267 * 0x10, Vamic2Ena 1268 */ 1269 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e), 1270 /* 1271 * 0x01, Vamic1_dzout 1272 * 0x02, Vamic2_dzout 1273 */ 1274 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), 1275 /* 1276 * 0x03, VpllRegu (NOTE! PRCMU register bits) 1277 * 0x0c, VanaRegu 1278 */ 1279 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f), 1280 /* 1281 * 0x01, VrefDDREna 1282 * 0x02, VrefDDRSleepMode 1283 */ 1284 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03), 1285 /* 1286 * 0x03, VextSupply1Regu 1287 * 0x0c, VextSupply2Regu 1288 * 0x30, VextSupply3Regu 1289 * 0x40, ExtSupply2Bypass 1290 * 0x80, ExtSupply3Bypass 1291 */ 1292 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff), 1293 /* 1294 * 0x03, Vaux1Regu 1295 * 0x0c, Vaux2Regu 1296 */ 1297 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f), 1298 /* 1299 * 0x03, Vaux3Regu 1300 */ 1301 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03), 1302 /* 1303 * 0x0f, Vaux1Sel 1304 */ 1305 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f), 1306 /* 1307 * 0x0f, Vaux2Sel 1308 */ 1309 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f), 1310 /* 1311 * 0x07, Vaux3Sel 1312 */ 1313 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07), 1314 /* 1315 * 0x01, VextSupply12LP 1316 */ 1317 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01), 1318 /* 1319 * 0x04, Vaux1Disch 1320 * 0x08, Vaux2Disch 1321 * 0x10, Vaux3Disch 1322 * 0x20, Vintcore12Disch 1323 * 0x40, VTVoutDisch 1324 * 0x80, VaudioDisch 1325 */ 1326 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc), 1327 /* 1328 * 0x02, VanaDisch 1329 * 0x04, VdmicPullDownEna 1330 * 0x10, VdmicDisch 1331 */ 1332 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16), 1333 }; 1334 1335 /* AB8505 register init */ 1336 static struct ab8500_reg_init ab8505_reg_init[] = { 1337 /* 1338 * 0x03, VarmRequestCtrl 1339 * 0x0c, VsmpsCRequestCtrl 1340 * 0x30, VsmpsARequestCtrl 1341 * 0xc0, VsmpsBRequestCtrl 1342 */ 1343 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff), 1344 /* 1345 * 0x03, VsafeRequestCtrl 1346 * 0x0c, VpllRequestCtrl 1347 * 0x30, VanaRequestCtrl 1348 */ 1349 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f), 1350 /* 1351 * 0x30, Vaux1RequestCtrl 1352 * 0xc0, Vaux2RequestCtrl 1353 */ 1354 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0), 1355 /* 1356 * 0x03, Vaux3RequestCtrl 1357 * 0x04, SwHPReq 1358 */ 1359 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), 1360 /* 1361 * 0x01, VsmpsASysClkReq1HPValid 1362 * 0x02, VsmpsBSysClkReq1HPValid 1363 * 0x04, VsafeSysClkReq1HPValid 1364 * 0x08, VanaSysClkReq1HPValid 1365 * 0x10, VpllSysClkReq1HPValid 1366 * 0x20, Vaux1SysClkReq1HPValid 1367 * 0x40, Vaux2SysClkReq1HPValid 1368 * 0x80, Vaux3SysClkReq1HPValid 1369 */ 1370 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff), 1371 /* 1372 * 0x01, VsmpsCSysClkReq1HPValid 1373 * 0x02, VarmSysClkReq1HPValid 1374 * 0x04, VbbSysClkReq1HPValid 1375 * 0x08, VsmpsMSysClkReq1HPValid 1376 */ 1377 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f), 1378 /* 1379 * 0x01, VsmpsAHwHPReq1Valid 1380 * 0x02, VsmpsBHwHPReq1Valid 1381 * 0x04, VsafeHwHPReq1Valid 1382 * 0x08, VanaHwHPReq1Valid 1383 * 0x10, VpllHwHPReq1Valid 1384 * 0x20, Vaux1HwHPReq1Valid 1385 * 0x40, Vaux2HwHPReq1Valid 1386 * 0x80, Vaux3HwHPReq1Valid 1387 */ 1388 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff), 1389 /* 1390 * 0x08, VsmpsMHwHPReq1Valid 1391 */ 1392 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08), 1393 /* 1394 * 0x01, VsmpsAHwHPReq2Valid 1395 * 0x02, VsmpsBHwHPReq2Valid 1396 * 0x04, VsafeHwHPReq2Valid 1397 * 0x08, VanaHwHPReq2Valid 1398 * 0x10, VpllHwHPReq2Valid 1399 * 0x20, Vaux1HwHPReq2Valid 1400 * 0x40, Vaux2HwHPReq2Valid 1401 * 0x80, Vaux3HwHPReq2Valid 1402 */ 1403 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff), 1404 /* 1405 * 0x08, VsmpsMHwHPReq2Valid 1406 */ 1407 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08), 1408 /* 1409 * 0x01, VsmpsCSwHPReqValid 1410 * 0x02, VarmSwHPReqValid 1411 * 0x04, VsmpsASwHPReqValid 1412 * 0x08, VsmpsBSwHPReqValid 1413 * 0x10, VsafeSwHPReqValid 1414 * 0x20, VanaSwHPReqValid 1415 * 0x40, VpllSwHPReqValid 1416 * 0x80, Vaux1SwHPReqValid 1417 */ 1418 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff), 1419 /* 1420 * 0x01, Vaux2SwHPReqValid 1421 * 0x02, Vaux3SwHPReqValid 1422 * 0x20, VsmpsMSwHPReqValid 1423 */ 1424 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23), 1425 /* 1426 * 0x02, SysClkReq2Valid1 1427 * 0x04, SysClkReq3Valid1 1428 * 0x08, SysClkReq4Valid1 1429 */ 1430 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e), 1431 /* 1432 * 0x02, SysClkReq2Valid2 1433 * 0x04, SysClkReq3Valid2 1434 * 0x08, SysClkReq4Valid2 1435 */ 1436 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e), 1437 /* 1438 * 0x01, Vaux4SwHPReqValid 1439 * 0x02, Vaux4HwHPReq2Valid 1440 * 0x04, Vaux4HwHPReq1Valid 1441 * 0x08, Vaux4SysClkReq1HPValid 1442 */ 1443 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f), 1444 /* 1445 * 0x02, VadcEna 1446 * 0x04, VintCore12Ena 1447 * 0x38, VintCore12Sel 1448 * 0x40, VintCore12LP 1449 * 0x80, VadcLP 1450 */ 1451 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe), 1452 /* 1453 * 0x02, VaudioEna 1454 * 0x04, VdmicEna 1455 * 0x08, Vamic1Ena 1456 * 0x10, Vamic2Ena 1457 */ 1458 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e), 1459 /* 1460 * 0x01, Vamic1_dzout 1461 * 0x02, Vamic2_dzout 1462 */ 1463 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), 1464 /* 1465 * 0x03, VsmpsARegu 1466 * 0x0c, VsmpsASelCtrl 1467 * 0x10, VsmpsAAutoMode 1468 * 0x20, VsmpsAPWMMode 1469 */ 1470 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f), 1471 /* 1472 * 0x03, VsmpsBRegu 1473 * 0x0c, VsmpsBSelCtrl 1474 * 0x10, VsmpsBAutoMode 1475 * 0x20, VsmpsBPWMMode 1476 */ 1477 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f), 1478 /* 1479 * 0x03, VsafeRegu 1480 * 0x0c, VsafeSelCtrl 1481 * 0x10, VsafeAutoMode 1482 * 0x20, VsafePWMMode 1483 */ 1484 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f), 1485 /* 1486 * 0x03, VpllRegu (NOTE! PRCMU register bits) 1487 * 0x0c, VanaRegu 1488 */ 1489 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f), 1490 /* 1491 * 0x03, VextSupply1Regu 1492 * 0x0c, VextSupply2Regu 1493 * 0x30, VextSupply3Regu 1494 * 0x40, ExtSupply2Bypass 1495 * 0x80, ExtSupply3Bypass 1496 */ 1497 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff), 1498 /* 1499 * 0x03, Vaux1Regu 1500 * 0x0c, Vaux2Regu 1501 */ 1502 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f), 1503 /* 1504 * 0x0f, Vaux3Regu 1505 */ 1506 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f), 1507 /* 1508 * 0x3f, VsmpsASel1 1509 */ 1510 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f), 1511 /* 1512 * 0x3f, VsmpsASel2 1513 */ 1514 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f), 1515 /* 1516 * 0x3f, VsmpsASel3 1517 */ 1518 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f), 1519 /* 1520 * 0x3f, VsmpsBSel1 1521 */ 1522 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f), 1523 /* 1524 * 0x3f, VsmpsBSel2 1525 */ 1526 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f), 1527 /* 1528 * 0x3f, VsmpsBSel3 1529 */ 1530 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f), 1531 /* 1532 * 0x7f, VsafeSel1 1533 */ 1534 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f), 1535 /* 1536 * 0x3f, VsafeSel2 1537 */ 1538 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f), 1539 /* 1540 * 0x3f, VsafeSel3 1541 */ 1542 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f), 1543 /* 1544 * 0x0f, Vaux1Sel 1545 */ 1546 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f), 1547 /* 1548 * 0x0f, Vaux2Sel 1549 */ 1550 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f), 1551 /* 1552 * 0x07, Vaux3Sel 1553 * 0x30, VRF1Sel 1554 */ 1555 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37), 1556 /* 1557 * 0x03, Vaux4RequestCtrl 1558 */ 1559 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03), 1560 /* 1561 * 0x03, Vaux4Regu 1562 */ 1563 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03), 1564 /* 1565 * 0x0f, Vaux4Sel 1566 */ 1567 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f), 1568 /* 1569 * 0x04, Vaux1Disch 1570 * 0x08, Vaux2Disch 1571 * 0x10, Vaux3Disch 1572 * 0x20, Vintcore12Disch 1573 * 0x40, VTVoutDisch 1574 * 0x80, VaudioDisch 1575 */ 1576 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc), 1577 /* 1578 * 0x02, VanaDisch 1579 * 0x04, VdmicPullDownEna 1580 * 0x10, VdmicDisch 1581 */ 1582 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16), 1583 /* 1584 * 0x01, Vaux4Disch 1585 */ 1586 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01), 1587 /* 1588 * 0x07, Vaux5Sel 1589 * 0x08, Vaux5LP 1590 * 0x10, Vaux5Ena 1591 * 0x20, Vaux5Disch 1592 * 0x40, Vaux5DisSfst 1593 * 0x80, Vaux5DisPulld 1594 */ 1595 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff), 1596 /* 1597 * 0x07, Vaux6Sel 1598 * 0x08, Vaux6LP 1599 * 0x10, Vaux6Ena 1600 * 0x80, Vaux6DisPulld 1601 */ 1602 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f), 1603 }; 1604 1605 static struct of_regulator_match ab8500_regulator_match[] = { 1606 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, }, 1607 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, }, 1608 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, }, 1609 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, }, 1610 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, }, 1611 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, }, 1612 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, }, 1613 { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, }, 1614 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, }, 1615 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, }, 1616 }; 1617 1618 static struct of_regulator_match ab8505_regulator_match[] = { 1619 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, }, 1620 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, }, 1621 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, }, 1622 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, }, 1623 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, }, 1624 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, }, 1625 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, }, 1626 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, }, 1627 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, }, 1628 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, }, 1629 { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, }, 1630 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, }, 1631 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, }, 1632 }; 1633 1634 static struct { 1635 struct ab8500_regulator_info *info; 1636 int info_size; 1637 struct ab8500_reg_init *init; 1638 int init_size; 1639 struct of_regulator_match *match; 1640 int match_size; 1641 } abx500_regulator; 1642 1643 static void abx500_get_regulator_info(struct ab8500 *ab8500) 1644 { 1645 if (is_ab8505(ab8500)) { 1646 abx500_regulator.info = ab8505_regulator_info; 1647 abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info); 1648 abx500_regulator.init = ab8505_reg_init; 1649 abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS; 1650 abx500_regulator.match = ab8505_regulator_match; 1651 abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match); 1652 } else { 1653 abx500_regulator.info = ab8500_regulator_info; 1654 abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info); 1655 abx500_regulator.init = ab8500_reg_init; 1656 abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS; 1657 abx500_regulator.match = ab8500_regulator_match; 1658 abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match); 1659 } 1660 } 1661 1662 static int ab8500_regulator_register(struct platform_device *pdev, 1663 struct regulator_init_data *init_data, 1664 int id, struct device_node *np) 1665 { 1666 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); 1667 struct ab8500_regulator_info *info = NULL; 1668 struct regulator_config config = { }; 1669 struct regulator_dev *rdev; 1670 1671 /* assign per-regulator data */ 1672 info = &abx500_regulator.info[id]; 1673 info->dev = &pdev->dev; 1674 1675 config.dev = &pdev->dev; 1676 config.init_data = init_data; 1677 config.driver_data = info; 1678 config.of_node = np; 1679 1680 /* fix for hardware before ab8500v2.0 */ 1681 if (is_ab8500_1p1_or_earlier(ab8500)) { 1682 if (info->desc.id == AB8500_LDO_AUX3) { 1683 info->desc.n_voltages = 1684 ARRAY_SIZE(ldo_vauxn_voltages); 1685 info->desc.volt_table = ldo_vauxn_voltages; 1686 info->voltage_mask = 0xf; 1687 } 1688 } 1689 1690 /* register regulator with framework */ 1691 rdev = devm_regulator_register(&pdev->dev, &info->desc, &config); 1692 if (IS_ERR(rdev)) { 1693 dev_err(&pdev->dev, "failed to register regulator %s\n", 1694 info->desc.name); 1695 return PTR_ERR(rdev); 1696 } 1697 1698 return 0; 1699 } 1700 1701 static int ab8500_regulator_probe(struct platform_device *pdev) 1702 { 1703 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); 1704 struct device_node *np = pdev->dev.of_node; 1705 struct of_regulator_match *match; 1706 int err, i; 1707 1708 if (!ab8500) { 1709 dev_err(&pdev->dev, "null mfd parent\n"); 1710 return -EINVAL; 1711 } 1712 1713 abx500_get_regulator_info(ab8500); 1714 1715 err = of_regulator_match(&pdev->dev, np, 1716 abx500_regulator.match, 1717 abx500_regulator.match_size); 1718 if (err < 0) { 1719 dev_err(&pdev->dev, 1720 "Error parsing regulator init data: %d\n", err); 1721 return err; 1722 } 1723 1724 match = abx500_regulator.match; 1725 for (i = 0; i < abx500_regulator.info_size; i++) { 1726 err = ab8500_regulator_register(pdev, match[i].init_data, i, 1727 match[i].of_node); 1728 if (err) 1729 return err; 1730 } 1731 1732 return 0; 1733 } 1734 1735 static struct platform_driver ab8500_regulator_driver = { 1736 .probe = ab8500_regulator_probe, 1737 .driver = { 1738 .name = "ab8500-regulator", 1739 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1740 }, 1741 }; 1742 1743 static int __init ab8500_regulator_init(void) 1744 { 1745 int ret; 1746 1747 ret = platform_driver_register(&ab8500_regulator_driver); 1748 if (ret != 0) 1749 pr_err("Failed to register ab8500 regulator: %d\n", ret); 1750 1751 return ret; 1752 } 1753 subsys_initcall(ab8500_regulator_init); 1754 1755 static void __exit ab8500_regulator_exit(void) 1756 { 1757 platform_driver_unregister(&ab8500_regulator_driver); 1758 } 1759 module_exit(ab8500_regulator_exit); 1760 1761 MODULE_LICENSE("GPL v2"); 1762 MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>"); 1763 MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>"); 1764 MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>"); 1765 MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC"); 1766 MODULE_ALIAS("platform:ab8500-regulator"); 1767