1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2021 Sean Anderson <sean.anderson@seco.com> 4 * 5 * Limitations: 6 * - When changing both duty cycle and period, we may end up with one cycle 7 * with the old duty cycle and the new period. This is because the counters 8 * may only be reloaded by first stopping them, or by letting them be 9 * automatically reloaded at the end of a cycle. If this automatic reload 10 * happens after we set TLR0 but before we set TLR1 then we will have a 11 * bad cycle. This could probably be fixed by reading TCR0 just before 12 * reprogramming, but I think it would add complexity for little gain. 13 * - Cannot produce 100% duty cycle by configuring the TLRs. This might be 14 * possible by stopping the counters at an appropriate point in the cycle, 15 * but this is not (yet) implemented. 16 * - Only produces "normal" output. 17 * - Always produces low output if disabled. 18 */ 19 20 #include <clocksource/timer-xilinx.h> 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 #include <linux/device.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/platform_device.h> 27 #include <linux/pwm.h> 28 #include <linux/regmap.h> 29 30 /* 31 * The following functions are "common" to drivers for this device, and may be 32 * exported at a future date. 33 */ 34 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr, 35 u64 cycles) 36 { 37 WARN_ON(cycles < 2 || cycles - 2 > priv->max); 38 39 if (tcsr & TCSR_UDT) 40 return cycles - 2; 41 return priv->max - cycles + 2; 42 } 43 44 unsigned int xilinx_timer_get_period(struct xilinx_timer_priv *priv, 45 u32 tlr, u32 tcsr) 46 { 47 u64 cycles; 48 49 if (tcsr & TCSR_UDT) 50 cycles = tlr + 2; 51 else 52 cycles = (u64)priv->max - tlr + 2; 53 54 /* cycles has a max of 2^32 + 2, so we can't overflow */ 55 return DIV64_U64_ROUND_UP(cycles * NSEC_PER_SEC, 56 clk_get_rate(priv->clk)); 57 } 58 59 /* 60 * The idea here is to capture whether the PWM is actually running (e.g. 61 * because we or the bootloader set it up) and we need to be careful to ensure 62 * we don't cause a glitch. According to the data sheet, to enable the PWM we 63 * need to 64 * 65 * - Set both timers to generate mode (MDT=1) 66 * - Set both timers to PWM mode (PWMA=1) 67 * - Enable the generate out signals (GENT=1) 68 * 69 * In addition, 70 * 71 * - The timer must be running (ENT=1) 72 * - The timer must auto-reload TLR into TCR (ARHT=1) 73 * - We must not be in the process of loading TLR into TCR (LOAD=0) 74 * - Cascade mode must be disabled (CASC=0) 75 * 76 * If any of these differ from usual, then the PWM is either disabled, or is 77 * running in a mode that this driver does not support. 78 */ 79 #define TCSR_PWM_SET (TCSR_GENT | TCSR_ARHT | TCSR_ENT | TCSR_PWMA) 80 #define TCSR_PWM_CLEAR (TCSR_MDT | TCSR_LOAD) 81 #define TCSR_PWM_MASK (TCSR_PWM_SET | TCSR_PWM_CLEAR) 82 83 static inline struct xilinx_timer_priv 84 *xilinx_pwm_chip_to_priv(struct pwm_chip *chip) 85 { 86 return pwmchip_get_drvdata(chip); 87 } 88 89 static bool xilinx_timer_pwm_enabled(u32 tcsr0, u32 tcsr1) 90 { 91 return ((TCSR_PWM_MASK | TCSR_CASC) & tcsr0) == TCSR_PWM_SET && 92 (TCSR_PWM_MASK & tcsr1) == TCSR_PWM_SET; 93 } 94 95 static int xilinx_pwm_apply(struct pwm_chip *chip, struct pwm_device *unused, 96 const struct pwm_state *state) 97 { 98 struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip); 99 u32 tlr0, tlr1, tcsr0, tcsr1; 100 u64 period_cycles, duty_cycles; 101 unsigned long rate; 102 103 if (state->polarity != PWM_POLARITY_NORMAL) 104 return -EINVAL; 105 106 /* 107 * To be representable by TLR, cycles must be between 2 and 108 * priv->max + 2. To enforce this we can reduce the cycles, but we may 109 * not increase them. Caveat emptor: while this does result in more 110 * predictable rounding, it may also result in a completely different 111 * duty cycle (% high time) than what was requested. 112 */ 113 rate = clk_get_rate(priv->clk); 114 /* Avoid overflow */ 115 period_cycles = min_t(u64, state->period, U32_MAX * NSEC_PER_SEC); 116 period_cycles = mul_u64_u32_div(period_cycles, rate, NSEC_PER_SEC); 117 period_cycles = min_t(u64, period_cycles, priv->max + 2); 118 if (period_cycles < 2) 119 return -ERANGE; 120 121 /* Same thing for duty cycles */ 122 duty_cycles = min_t(u64, state->duty_cycle, U32_MAX * NSEC_PER_SEC); 123 duty_cycles = mul_u64_u32_div(duty_cycles, rate, NSEC_PER_SEC); 124 duty_cycles = min_t(u64, duty_cycles, priv->max + 2); 125 126 /* 127 * If we specify 100% duty cycle, we will get 0% instead, so decrease 128 * the duty cycle count by one. 129 */ 130 if (duty_cycles >= period_cycles) 131 duty_cycles = period_cycles - 1; 132 133 /* Round down to 0% duty cycle for unrepresentable duty cycles */ 134 if (duty_cycles < 2) 135 duty_cycles = period_cycles; 136 137 regmap_read(priv->map, TCSR0, &tcsr0); 138 regmap_read(priv->map, TCSR1, &tcsr1); 139 tlr0 = xilinx_timer_tlr_cycles(priv, tcsr0, period_cycles); 140 tlr1 = xilinx_timer_tlr_cycles(priv, tcsr1, duty_cycles); 141 regmap_write(priv->map, TLR0, tlr0); 142 regmap_write(priv->map, TLR1, tlr1); 143 144 if (state->enabled) { 145 /* 146 * If the PWM is already running, then the counters will be 147 * reloaded at the end of the current cycle. 148 */ 149 if (!xilinx_timer_pwm_enabled(tcsr0, tcsr1)) { 150 /* Load TLR into TCR */ 151 regmap_write(priv->map, TCSR0, tcsr0 | TCSR_LOAD); 152 regmap_write(priv->map, TCSR1, tcsr1 | TCSR_LOAD); 153 /* Enable timers all at once with ENALL */ 154 tcsr0 = (TCSR_PWM_SET & ~TCSR_ENT) | (tcsr0 & TCSR_UDT); 155 tcsr1 = TCSR_PWM_SET | TCSR_ENALL | (tcsr1 & TCSR_UDT); 156 regmap_write(priv->map, TCSR0, tcsr0); 157 regmap_write(priv->map, TCSR1, tcsr1); 158 } 159 } else { 160 regmap_write(priv->map, TCSR0, 0); 161 regmap_write(priv->map, TCSR1, 0); 162 } 163 164 return 0; 165 } 166 167 static int xilinx_pwm_get_state(struct pwm_chip *chip, 168 struct pwm_device *unused, 169 struct pwm_state *state) 170 { 171 struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip); 172 u32 tlr0, tlr1, tcsr0, tcsr1; 173 174 regmap_read(priv->map, TLR0, &tlr0); 175 regmap_read(priv->map, TLR1, &tlr1); 176 regmap_read(priv->map, TCSR0, &tcsr0); 177 regmap_read(priv->map, TCSR1, &tcsr1); 178 state->period = xilinx_timer_get_period(priv, tlr0, tcsr0); 179 state->duty_cycle = xilinx_timer_get_period(priv, tlr1, tcsr1); 180 state->enabled = xilinx_timer_pwm_enabled(tcsr0, tcsr1); 181 state->polarity = PWM_POLARITY_NORMAL; 182 183 /* 184 * 100% duty cycle results in constant low output. This may be (very) 185 * wrong if rate > 1 GHz, so fix this if you have such hardware :) 186 */ 187 if (state->period == state->duty_cycle) 188 state->duty_cycle = 0; 189 190 return 0; 191 } 192 193 static const struct pwm_ops xilinx_pwm_ops = { 194 .apply = xilinx_pwm_apply, 195 .get_state = xilinx_pwm_get_state, 196 }; 197 198 static const struct regmap_config xilinx_pwm_regmap_config = { 199 .reg_bits = 32, 200 .reg_stride = 4, 201 .val_bits = 32, 202 .val_format_endian = REGMAP_ENDIAN_LITTLE, 203 .max_register = TCR1, 204 }; 205 206 static int xilinx_pwm_probe(struct platform_device *pdev) 207 { 208 int ret; 209 struct device *dev = &pdev->dev; 210 struct device_node *np = dev->of_node; 211 struct xilinx_timer_priv *priv; 212 struct pwm_chip *chip; 213 u32 pwm_cells, one_timer, width; 214 void __iomem *regs; 215 216 /* If there are no PWM cells, this binding is for a timer */ 217 ret = of_property_read_u32(np, "#pwm-cells", &pwm_cells); 218 if (ret == -EINVAL) 219 return -ENODEV; 220 if (ret) 221 return dev_err_probe(dev, ret, "could not read #pwm-cells\n"); 222 223 chip = devm_pwmchip_alloc(dev, 1, sizeof(*priv)); 224 if (IS_ERR(chip)) 225 return PTR_ERR(chip); 226 priv = xilinx_pwm_chip_to_priv(chip); 227 platform_set_drvdata(pdev, chip); 228 229 regs = devm_platform_ioremap_resource(pdev, 0); 230 if (IS_ERR(regs)) 231 return PTR_ERR(regs); 232 233 priv->map = devm_regmap_init_mmio(dev, regs, 234 &xilinx_pwm_regmap_config); 235 if (IS_ERR(priv->map)) 236 return dev_err_probe(dev, PTR_ERR(priv->map), 237 "Could not create regmap\n"); 238 239 ret = of_property_read_u32(np, "xlnx,one-timer-only", &one_timer); 240 if (ret) 241 return dev_err_probe(dev, ret, 242 "Could not read xlnx,one-timer-only\n"); 243 244 if (one_timer) 245 return dev_err_probe(dev, -EINVAL, 246 "Two timers required for PWM mode\n"); 247 248 ret = of_property_read_u32(np, "xlnx,count-width", &width); 249 if (ret == -EINVAL) 250 width = 32; 251 else if (ret) 252 return dev_err_probe(dev, ret, 253 "Could not read xlnx,count-width\n"); 254 255 if (width != 8 && width != 16 && width != 32) 256 return dev_err_probe(dev, -EINVAL, 257 "Invalid counter width %d\n", width); 258 priv->max = BIT_ULL(width) - 1; 259 260 /* 261 * The polarity of the Generate Out signals must be active high for PWM 262 * mode to work. We could determine this from the device tree, but 263 * alas, such properties are not allowed to be used. 264 */ 265 266 priv->clk = devm_clk_get(dev, "s_axi_aclk"); 267 if (IS_ERR(priv->clk)) 268 return dev_err_probe(dev, PTR_ERR(priv->clk), 269 "Could not get clock\n"); 270 271 ret = clk_prepare_enable(priv->clk); 272 if (ret) 273 return dev_err_probe(dev, ret, "Clock enable failed\n"); 274 clk_rate_exclusive_get(priv->clk); 275 276 chip->ops = &xilinx_pwm_ops; 277 ret = pwmchip_add(chip); 278 if (ret) { 279 clk_rate_exclusive_put(priv->clk); 280 clk_disable_unprepare(priv->clk); 281 return dev_err_probe(dev, ret, "Could not register PWM chip\n"); 282 } 283 284 return 0; 285 } 286 287 static void xilinx_pwm_remove(struct platform_device *pdev) 288 { 289 struct pwm_chip *chip = platform_get_drvdata(pdev); 290 struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip); 291 292 pwmchip_remove(chip); 293 clk_rate_exclusive_put(priv->clk); 294 clk_disable_unprepare(priv->clk); 295 } 296 297 static const struct of_device_id xilinx_pwm_of_match[] = { 298 { .compatible = "xlnx,xps-timer-1.00.a", }, 299 {}, 300 }; 301 MODULE_DEVICE_TABLE(of, xilinx_pwm_of_match); 302 303 static struct platform_driver xilinx_pwm_driver = { 304 .probe = xilinx_pwm_probe, 305 .remove_new = xilinx_pwm_remove, 306 .driver = { 307 .name = "xilinx-pwm", 308 .of_match_table = of_match_ptr(xilinx_pwm_of_match), 309 }, 310 }; 311 module_platform_driver(xilinx_pwm_driver); 312 313 MODULE_ALIAS("platform:xilinx-pwm"); 314 MODULE_DESCRIPTION("PWM driver for Xilinx LogiCORE IP AXI Timer"); 315 MODULE_LICENSE("GPL"); 316