1 /* 2 * ECAP PWM driver 3 * 4 * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/io.h> 24 #include <linux/err.h> 25 #include <linux/clk.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pwm.h> 28 #include <linux/of_device.h> 29 30 #include "pwm-tipwmss.h" 31 32 /* ECAP registers and bits definitions */ 33 #define CAP1 0x08 34 #define CAP2 0x0C 35 #define CAP3 0x10 36 #define CAP4 0x14 37 #define ECCTL2 0x2A 38 #define ECCTL2_APWM_POL_LOW BIT(10) 39 #define ECCTL2_APWM_MODE BIT(9) 40 #define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6)) 41 #define ECCTL2_TSCTR_FREERUN BIT(4) 42 43 struct ecap_context { 44 u32 cap3; 45 u32 cap4; 46 u16 ecctl2; 47 }; 48 49 struct ecap_pwm_chip { 50 struct pwm_chip chip; 51 unsigned int clk_rate; 52 void __iomem *mmio_base; 53 struct ecap_context ctx; 54 }; 55 56 static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip) 57 { 58 return container_of(chip, struct ecap_pwm_chip, chip); 59 } 60 61 /* 62 * period_ns = 10^9 * period_cycles / PWM_CLK_RATE 63 * duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE 64 */ 65 static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 66 int duty_ns, int period_ns) 67 { 68 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); 69 unsigned long long c; 70 unsigned long period_cycles, duty_cycles; 71 unsigned int reg_val; 72 73 if (period_ns > NSEC_PER_SEC) 74 return -ERANGE; 75 76 c = pc->clk_rate; 77 c = c * period_ns; 78 do_div(c, NSEC_PER_SEC); 79 period_cycles = (unsigned long)c; 80 81 if (period_cycles < 1) { 82 period_cycles = 1; 83 duty_cycles = 1; 84 } else { 85 c = pc->clk_rate; 86 c = c * duty_ns; 87 do_div(c, NSEC_PER_SEC); 88 duty_cycles = (unsigned long)c; 89 } 90 91 pm_runtime_get_sync(pc->chip.dev); 92 93 reg_val = readw(pc->mmio_base + ECCTL2); 94 95 /* Configure APWM mode & disable sync option */ 96 reg_val |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA; 97 98 writew(reg_val, pc->mmio_base + ECCTL2); 99 100 if (!test_bit(PWMF_ENABLED, &pwm->flags)) { 101 /* Update active registers if not running */ 102 writel(duty_cycles, pc->mmio_base + CAP2); 103 writel(period_cycles, pc->mmio_base + CAP1); 104 } else { 105 /* 106 * Update shadow registers to configure period and 107 * compare values. This helps current PWM period to 108 * complete on reconfiguring 109 */ 110 writel(duty_cycles, pc->mmio_base + CAP4); 111 writel(period_cycles, pc->mmio_base + CAP3); 112 } 113 114 if (!test_bit(PWMF_ENABLED, &pwm->flags)) { 115 reg_val = readw(pc->mmio_base + ECCTL2); 116 /* Disable APWM mode to put APWM output Low */ 117 reg_val &= ~ECCTL2_APWM_MODE; 118 writew(reg_val, pc->mmio_base + ECCTL2); 119 } 120 121 pm_runtime_put_sync(pc->chip.dev); 122 return 0; 123 } 124 125 static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, 126 enum pwm_polarity polarity) 127 { 128 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); 129 unsigned short reg_val; 130 131 pm_runtime_get_sync(pc->chip.dev); 132 reg_val = readw(pc->mmio_base + ECCTL2); 133 if (polarity == PWM_POLARITY_INVERSED) 134 /* Duty cycle defines LOW period of PWM */ 135 reg_val |= ECCTL2_APWM_POL_LOW; 136 else 137 /* Duty cycle defines HIGH period of PWM */ 138 reg_val &= ~ECCTL2_APWM_POL_LOW; 139 140 writew(reg_val, pc->mmio_base + ECCTL2); 141 pm_runtime_put_sync(pc->chip.dev); 142 return 0; 143 } 144 145 static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 146 { 147 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); 148 unsigned int reg_val; 149 150 /* Leave clock enabled on enabling PWM */ 151 pm_runtime_get_sync(pc->chip.dev); 152 153 /* 154 * Enable 'Free run Time stamp counter mode' to start counter 155 * and 'APWM mode' to enable APWM output 156 */ 157 reg_val = readw(pc->mmio_base + ECCTL2); 158 reg_val |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE; 159 writew(reg_val, pc->mmio_base + ECCTL2); 160 return 0; 161 } 162 163 static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 164 { 165 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); 166 unsigned int reg_val; 167 168 /* 169 * Disable 'Free run Time stamp counter mode' to stop counter 170 * and 'APWM mode' to put APWM output to low 171 */ 172 reg_val = readw(pc->mmio_base + ECCTL2); 173 reg_val &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE); 174 writew(reg_val, pc->mmio_base + ECCTL2); 175 176 /* Disable clock on PWM disable */ 177 pm_runtime_put_sync(pc->chip.dev); 178 } 179 180 static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 181 { 182 if (test_bit(PWMF_ENABLED, &pwm->flags)) { 183 dev_warn(chip->dev, "Removing PWM device without disabling\n"); 184 pm_runtime_put_sync(chip->dev); 185 } 186 } 187 188 static const struct pwm_ops ecap_pwm_ops = { 189 .free = ecap_pwm_free, 190 .config = ecap_pwm_config, 191 .set_polarity = ecap_pwm_set_polarity, 192 .enable = ecap_pwm_enable, 193 .disable = ecap_pwm_disable, 194 .owner = THIS_MODULE, 195 }; 196 197 static const struct of_device_id ecap_of_match[] = { 198 { .compatible = "ti,am33xx-ecap" }, 199 {}, 200 }; 201 MODULE_DEVICE_TABLE(of, ecap_of_match); 202 203 static int ecap_pwm_probe(struct platform_device *pdev) 204 { 205 int ret; 206 struct resource *r; 207 struct clk *clk; 208 struct ecap_pwm_chip *pc; 209 u16 status; 210 211 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 212 if (!pc) 213 return -ENOMEM; 214 215 clk = devm_clk_get(&pdev->dev, "fck"); 216 if (IS_ERR(clk)) { 217 dev_err(&pdev->dev, "failed to get clock\n"); 218 return PTR_ERR(clk); 219 } 220 221 pc->clk_rate = clk_get_rate(clk); 222 if (!pc->clk_rate) { 223 dev_err(&pdev->dev, "failed to get clock rate\n"); 224 return -EINVAL; 225 } 226 227 pc->chip.dev = &pdev->dev; 228 pc->chip.ops = &ecap_pwm_ops; 229 pc->chip.of_xlate = of_pwm_xlate_with_flags; 230 pc->chip.of_pwm_n_cells = 3; 231 pc->chip.base = -1; 232 pc->chip.npwm = 1; 233 234 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 235 pc->mmio_base = devm_ioremap_resource(&pdev->dev, r); 236 if (IS_ERR(pc->mmio_base)) 237 return PTR_ERR(pc->mmio_base); 238 239 ret = pwmchip_add(&pc->chip); 240 if (ret < 0) { 241 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 242 return ret; 243 } 244 245 pm_runtime_enable(&pdev->dev); 246 pm_runtime_get_sync(&pdev->dev); 247 248 status = pwmss_submodule_state_change(pdev->dev.parent, 249 PWMSS_ECAPCLK_EN); 250 if (!(status & PWMSS_ECAPCLK_EN_ACK)) { 251 dev_err(&pdev->dev, "PWMSS config space clock enable failed\n"); 252 ret = -EINVAL; 253 goto pwmss_clk_failure; 254 } 255 256 pm_runtime_put_sync(&pdev->dev); 257 258 platform_set_drvdata(pdev, pc); 259 return 0; 260 261 pwmss_clk_failure: 262 pm_runtime_put_sync(&pdev->dev); 263 pm_runtime_disable(&pdev->dev); 264 pwmchip_remove(&pc->chip); 265 return ret; 266 } 267 268 static int ecap_pwm_remove(struct platform_device *pdev) 269 { 270 struct ecap_pwm_chip *pc = platform_get_drvdata(pdev); 271 272 pm_runtime_get_sync(&pdev->dev); 273 /* 274 * Due to hardware misbehaviour, acknowledge of the stop_req 275 * is missing. Hence checking of the status bit skipped. 276 */ 277 pwmss_submodule_state_change(pdev->dev.parent, PWMSS_ECAPCLK_STOP_REQ); 278 pm_runtime_put_sync(&pdev->dev); 279 280 pm_runtime_disable(&pdev->dev); 281 return pwmchip_remove(&pc->chip); 282 } 283 284 #ifdef CONFIG_PM_SLEEP 285 static void ecap_pwm_save_context(struct ecap_pwm_chip *pc) 286 { 287 pm_runtime_get_sync(pc->chip.dev); 288 pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2); 289 pc->ctx.cap4 = readl(pc->mmio_base + CAP4); 290 pc->ctx.cap3 = readl(pc->mmio_base + CAP3); 291 pm_runtime_put_sync(pc->chip.dev); 292 } 293 294 static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc) 295 { 296 writel(pc->ctx.cap3, pc->mmio_base + CAP3); 297 writel(pc->ctx.cap4, pc->mmio_base + CAP4); 298 writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2); 299 } 300 301 static int ecap_pwm_suspend(struct device *dev) 302 { 303 struct ecap_pwm_chip *pc = dev_get_drvdata(dev); 304 struct pwm_device *pwm = pc->chip.pwms; 305 306 ecap_pwm_save_context(pc); 307 308 /* Disable explicitly if PWM is running */ 309 if (test_bit(PWMF_ENABLED, &pwm->flags)) 310 pm_runtime_put_sync(dev); 311 312 return 0; 313 } 314 315 static int ecap_pwm_resume(struct device *dev) 316 { 317 struct ecap_pwm_chip *pc = dev_get_drvdata(dev); 318 struct pwm_device *pwm = pc->chip.pwms; 319 320 /* Enable explicitly if PWM was running */ 321 if (test_bit(PWMF_ENABLED, &pwm->flags)) 322 pm_runtime_get_sync(dev); 323 324 ecap_pwm_restore_context(pc); 325 return 0; 326 } 327 #endif 328 329 static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume); 330 331 static struct platform_driver ecap_pwm_driver = { 332 .driver = { 333 .name = "ecap", 334 .of_match_table = ecap_of_match, 335 .pm = &ecap_pwm_pm_ops, 336 }, 337 .probe = ecap_pwm_probe, 338 .remove = ecap_pwm_remove, 339 }; 340 341 module_platform_driver(ecap_pwm_driver); 342 343 MODULE_DESCRIPTION("ECAP PWM driver"); 344 MODULE_AUTHOR("Texas Instruments"); 345 MODULE_LICENSE("GPL"); 346