1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/pwm/pwm-tegra.c 4 * 5 * Tegra pulse-width-modulation controller driver 6 * 7 * Copyright (c) 2010-2020, NVIDIA Corporation. 8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de> 9 * 10 * Overview of Tegra Pulse Width Modulator Register: 11 * 1. 13-bit: Frequency division (SCALE) 12 * 2. 8-bit : Pulse division (DUTY) 13 * 3. 1-bit : Enable bit 14 * 15 * The PWM clock frequency is divided by 256 before subdividing it based 16 * on the programmable frequency division value to generate the required 17 * frequency for PWM output. The maximum output frequency that can be 18 * achieved is (max rate of source clock) / 256. 19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be: 20 * 408 MHz/256 = 1.6 MHz. 21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM. 22 * 23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width. 24 * To achieve 100% duty cycle, program Bit [24] of this register to 25 * 1’b1. In which case the other bits [23:16] are set to don't care. 26 * 27 * Limitations: 28 * - When PWM is disabled, the output is driven to inactive. 29 * - It does not allow the current PWM period to complete and 30 * stops abruptly. 31 * 32 * - If the register is reconfigured while PWM is running, 33 * it does not complete the currently running period. 34 * 35 * - If the user input duty is beyond acceptible limits, 36 * -EINVAL is returned. 37 */ 38 39 #include <linux/clk.h> 40 #include <linux/err.h> 41 #include <linux/io.h> 42 #include <linux/module.h> 43 #include <linux/of.h> 44 #include <linux/of_device.h> 45 #include <linux/pwm.h> 46 #include <linux/platform_device.h> 47 #include <linux/pinctrl/consumer.h> 48 #include <linux/slab.h> 49 #include <linux/reset.h> 50 51 #define PWM_ENABLE (1 << 31) 52 #define PWM_DUTY_WIDTH 8 53 #define PWM_DUTY_SHIFT 16 54 #define PWM_SCALE_WIDTH 13 55 #define PWM_SCALE_SHIFT 0 56 57 struct tegra_pwm_soc { 58 unsigned int num_channels; 59 60 /* Maximum IP frequency for given SoCs */ 61 unsigned long max_frequency; 62 }; 63 64 struct tegra_pwm_chip { 65 struct pwm_chip chip; 66 struct device *dev; 67 68 struct clk *clk; 69 struct reset_control*rst; 70 71 unsigned long clk_rate; 72 unsigned long min_period_ns; 73 74 void __iomem *regs; 75 76 const struct tegra_pwm_soc *soc; 77 }; 78 79 static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) 80 { 81 return container_of(chip, struct tegra_pwm_chip, chip); 82 } 83 84 static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num) 85 { 86 return readl(chip->regs + (num << 4)); 87 } 88 89 static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num, 90 unsigned long val) 91 { 92 writel(val, chip->regs + (num << 4)); 93 } 94 95 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 96 int duty_ns, int period_ns) 97 { 98 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 99 unsigned long long c = duty_ns, hz; 100 unsigned long rate, required_clk_rate; 101 u32 val = 0; 102 int err; 103 104 /* 105 * Convert from duty_ns / period_ns to a fixed number of duty ticks 106 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the 107 * nearest integer during division. 108 */ 109 c *= (1 << PWM_DUTY_WIDTH); 110 c = DIV_ROUND_CLOSEST_ULL(c, period_ns); 111 112 val = (u32)c << PWM_DUTY_SHIFT; 113 114 /* 115 * min period = max clock limit >> PWM_DUTY_WIDTH 116 */ 117 if (period_ns < pc->min_period_ns) 118 return -EINVAL; 119 120 /* 121 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) 122 * cycles at the PWM clock rate will take period_ns nanoseconds. 123 * 124 * num_channels: If single instance of PWM controller has multiple 125 * channels (e.g. Tegra210 or older) then it is not possible to 126 * configure separate clock rates to each of the channels, in such 127 * case the value stored during probe will be referred. 128 * 129 * If every PWM controller instance has one channel respectively, i.e. 130 * nums_channels == 1 then only the clock rate can be modified 131 * dynamically (e.g. Tegra186 or Tegra194). 132 */ 133 if (pc->soc->num_channels == 1) { 134 /* 135 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches 136 * with the maximum possible rate that the controller can 137 * provide. Any further lower value can be derived by setting 138 * PFM bits[0:12]. 139 * 140 * required_clk_rate is a reference rate for source clock and 141 * it is derived based on user requested period. By setting the 142 * source clock rate as required_clk_rate, PWM controller will 143 * be able to configure the requested period. 144 */ 145 required_clk_rate = 146 (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH; 147 148 err = clk_set_rate(pc->clk, required_clk_rate); 149 if (err < 0) 150 return -EINVAL; 151 152 /* Store the new rate for further references */ 153 pc->clk_rate = clk_get_rate(pc->clk); 154 } 155 156 rate = pc->clk_rate >> PWM_DUTY_WIDTH; 157 158 /* Consider precision in PWM_SCALE_WIDTH rate calculation */ 159 hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns); 160 rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz); 161 162 /* 163 * Since the actual PWM divider is the register's frequency divider 164 * field plus 1, we need to decrement to get the correct value to 165 * write to the register. 166 */ 167 if (rate > 0) 168 rate--; 169 170 /* 171 * Make sure that the rate will fit in the register's frequency 172 * divider field. 173 */ 174 if (rate >> PWM_SCALE_WIDTH) 175 return -EINVAL; 176 177 val |= rate << PWM_SCALE_SHIFT; 178 179 /* 180 * If the PWM channel is disabled, make sure to turn on the clock 181 * before writing the register. Otherwise, keep it enabled. 182 */ 183 if (!pwm_is_enabled(pwm)) { 184 err = clk_prepare_enable(pc->clk); 185 if (err < 0) 186 return err; 187 } else 188 val |= PWM_ENABLE; 189 190 pwm_writel(pc, pwm->hwpwm, val); 191 192 /* 193 * If the PWM is not enabled, turn the clock off again to save power. 194 */ 195 if (!pwm_is_enabled(pwm)) 196 clk_disable_unprepare(pc->clk); 197 198 return 0; 199 } 200 201 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 202 { 203 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 204 int rc = 0; 205 u32 val; 206 207 rc = clk_prepare_enable(pc->clk); 208 if (rc < 0) 209 return rc; 210 211 val = pwm_readl(pc, pwm->hwpwm); 212 val |= PWM_ENABLE; 213 pwm_writel(pc, pwm->hwpwm, val); 214 215 return 0; 216 } 217 218 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 219 { 220 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 221 u32 val; 222 223 val = pwm_readl(pc, pwm->hwpwm); 224 val &= ~PWM_ENABLE; 225 pwm_writel(pc, pwm->hwpwm, val); 226 227 clk_disable_unprepare(pc->clk); 228 } 229 230 static const struct pwm_ops tegra_pwm_ops = { 231 .config = tegra_pwm_config, 232 .enable = tegra_pwm_enable, 233 .disable = tegra_pwm_disable, 234 .owner = THIS_MODULE, 235 }; 236 237 static int tegra_pwm_probe(struct platform_device *pdev) 238 { 239 struct tegra_pwm_chip *pwm; 240 int ret; 241 242 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); 243 if (!pwm) 244 return -ENOMEM; 245 246 pwm->soc = of_device_get_match_data(&pdev->dev); 247 pwm->dev = &pdev->dev; 248 249 pwm->regs = devm_platform_ioremap_resource(pdev, 0); 250 if (IS_ERR(pwm->regs)) 251 return PTR_ERR(pwm->regs); 252 253 platform_set_drvdata(pdev, pwm); 254 255 pwm->clk = devm_clk_get(&pdev->dev, NULL); 256 if (IS_ERR(pwm->clk)) 257 return PTR_ERR(pwm->clk); 258 259 /* Set maximum frequency of the IP */ 260 ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency); 261 if (ret < 0) { 262 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); 263 return ret; 264 } 265 266 /* 267 * The requested and configured frequency may differ due to 268 * clock register resolutions. Get the configured frequency 269 * so that PWM period can be calculated more accurately. 270 */ 271 pwm->clk_rate = clk_get_rate(pwm->clk); 272 273 /* Set minimum limit of PWM period for the IP */ 274 pwm->min_period_ns = 275 (NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1; 276 277 pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); 278 if (IS_ERR(pwm->rst)) { 279 ret = PTR_ERR(pwm->rst); 280 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret); 281 return ret; 282 } 283 284 reset_control_deassert(pwm->rst); 285 286 pwm->chip.dev = &pdev->dev; 287 pwm->chip.ops = &tegra_pwm_ops; 288 pwm->chip.npwm = pwm->soc->num_channels; 289 290 ret = pwmchip_add(&pwm->chip); 291 if (ret < 0) { 292 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 293 reset_control_assert(pwm->rst); 294 return ret; 295 } 296 297 return 0; 298 } 299 300 static int tegra_pwm_remove(struct platform_device *pdev) 301 { 302 struct tegra_pwm_chip *pc = platform_get_drvdata(pdev); 303 unsigned int i; 304 int err; 305 306 if (WARN_ON(!pc)) 307 return -ENODEV; 308 309 err = clk_prepare_enable(pc->clk); 310 if (err < 0) 311 return err; 312 313 for (i = 0; i < pc->chip.npwm; i++) { 314 struct pwm_device *pwm = &pc->chip.pwms[i]; 315 316 if (!pwm_is_enabled(pwm)) 317 if (clk_prepare_enable(pc->clk) < 0) 318 continue; 319 320 pwm_writel(pc, i, 0); 321 322 clk_disable_unprepare(pc->clk); 323 } 324 325 reset_control_assert(pc->rst); 326 clk_disable_unprepare(pc->clk); 327 328 return pwmchip_remove(&pc->chip); 329 } 330 331 #ifdef CONFIG_PM_SLEEP 332 static int tegra_pwm_suspend(struct device *dev) 333 { 334 return pinctrl_pm_select_sleep_state(dev); 335 } 336 337 static int tegra_pwm_resume(struct device *dev) 338 { 339 return pinctrl_pm_select_default_state(dev); 340 } 341 #endif 342 343 static const struct tegra_pwm_soc tegra20_pwm_soc = { 344 .num_channels = 4, 345 .max_frequency = 48000000UL, 346 }; 347 348 static const struct tegra_pwm_soc tegra186_pwm_soc = { 349 .num_channels = 1, 350 .max_frequency = 102000000UL, 351 }; 352 353 static const struct tegra_pwm_soc tegra194_pwm_soc = { 354 .num_channels = 1, 355 .max_frequency = 408000000UL, 356 }; 357 358 static const struct of_device_id tegra_pwm_of_match[] = { 359 { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc }, 360 { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc }, 361 { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc }, 362 { } 363 }; 364 MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); 365 366 static const struct dev_pm_ops tegra_pwm_pm_ops = { 367 SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume) 368 }; 369 370 static struct platform_driver tegra_pwm_driver = { 371 .driver = { 372 .name = "tegra-pwm", 373 .of_match_table = tegra_pwm_of_match, 374 .pm = &tegra_pwm_pm_ops, 375 }, 376 .probe = tegra_pwm_probe, 377 .remove = tegra_pwm_remove, 378 }; 379 380 module_platform_driver(tegra_pwm_driver); 381 382 MODULE_LICENSE("GPL"); 383 MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>"); 384 MODULE_DESCRIPTION("Tegra PWM controller driver"); 385 MODULE_ALIAS("platform:tegra-pwm"); 386