1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/pwm/pwm-tegra.c 4 * 5 * Tegra pulse-width-modulation controller driver 6 * 7 * Copyright (c) 2010-2020, NVIDIA Corporation. 8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de> 9 * 10 * Overview of Tegra Pulse Width Modulator Register: 11 * 1. 13-bit: Frequency division (SCALE) 12 * 2. 8-bit : Pulse division (DUTY) 13 * 3. 1-bit : Enable bit 14 * 15 * The PWM clock frequency is divided by 256 before subdividing it based 16 * on the programmable frequency division value to generate the required 17 * frequency for PWM output. The maximum output frequency that can be 18 * achieved is (max rate of source clock) / 256. 19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be: 20 * 408 MHz/256 = 1.6 MHz. 21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM. 22 * 23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width. 24 * To achieve 100% duty cycle, program Bit [24] of this register to 25 * 1’b1. In which case the other bits [23:16] are set to don't care. 26 * 27 * Limitations: 28 * - When PWM is disabled, the output is driven to inactive. 29 * - It does not allow the current PWM period to complete and 30 * stops abruptly. 31 * 32 * - If the register is reconfigured while PWM is running, 33 * it does not complete the currently running period. 34 * 35 * - If the user input duty is beyond acceptible limits, 36 * -EINVAL is returned. 37 */ 38 39 #include <linux/clk.h> 40 #include <linux/err.h> 41 #include <linux/io.h> 42 #include <linux/module.h> 43 #include <linux/of.h> 44 #include <linux/pm_opp.h> 45 #include <linux/pwm.h> 46 #include <linux/platform_device.h> 47 #include <linux/pinctrl/consumer.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/slab.h> 50 #include <linux/reset.h> 51 52 #include <soc/tegra/common.h> 53 54 #define PWM_ENABLE (1 << 31) 55 #define PWM_DUTY_WIDTH 8 56 #define PWM_DUTY_SHIFT 16 57 #define PWM_SCALE_WIDTH 13 58 #define PWM_SCALE_SHIFT 0 59 60 struct tegra_pwm_soc { 61 unsigned int num_channels; 62 63 /* Maximum IP frequency for given SoCs */ 64 unsigned long max_frequency; 65 }; 66 67 struct tegra_pwm_chip { 68 struct pwm_chip chip; 69 struct device *dev; 70 71 struct clk *clk; 72 struct reset_control*rst; 73 74 unsigned long clk_rate; 75 unsigned long min_period_ns; 76 77 void __iomem *regs; 78 79 const struct tegra_pwm_soc *soc; 80 }; 81 82 static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) 83 { 84 return container_of(chip, struct tegra_pwm_chip, chip); 85 } 86 87 static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset) 88 { 89 return readl(pc->regs + (offset << 4)); 90 } 91 92 static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value) 93 { 94 writel(value, pc->regs + (offset << 4)); 95 } 96 97 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 98 int duty_ns, int period_ns) 99 { 100 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 101 unsigned long long c = duty_ns; 102 unsigned long rate, required_clk_rate; 103 u32 val = 0; 104 int err; 105 106 /* 107 * Convert from duty_ns / period_ns to a fixed number of duty ticks 108 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the 109 * nearest integer during division. 110 */ 111 c *= (1 << PWM_DUTY_WIDTH); 112 c = DIV_ROUND_CLOSEST_ULL(c, period_ns); 113 114 val = (u32)c << PWM_DUTY_SHIFT; 115 116 /* 117 * min period = max clock limit >> PWM_DUTY_WIDTH 118 */ 119 if (period_ns < pc->min_period_ns) 120 return -EINVAL; 121 122 /* 123 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) 124 * cycles at the PWM clock rate will take period_ns nanoseconds. 125 * 126 * num_channels: If single instance of PWM controller has multiple 127 * channels (e.g. Tegra210 or older) then it is not possible to 128 * configure separate clock rates to each of the channels, in such 129 * case the value stored during probe will be referred. 130 * 131 * If every PWM controller instance has one channel respectively, i.e. 132 * nums_channels == 1 then only the clock rate can be modified 133 * dynamically (e.g. Tegra186 or Tegra194). 134 */ 135 if (pc->soc->num_channels == 1) { 136 /* 137 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches 138 * with the maximum possible rate that the controller can 139 * provide. Any further lower value can be derived by setting 140 * PFM bits[0:12]. 141 * 142 * required_clk_rate is a reference rate for source clock and 143 * it is derived based on user requested period. By setting the 144 * source clock rate as required_clk_rate, PWM controller will 145 * be able to configure the requested period. 146 */ 147 required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH, 148 period_ns); 149 150 if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate)) 151 /* 152 * required_clk_rate is a lower bound for the input 153 * rate; for lower rates there is no value for PWM_SCALE 154 * that yields a period less than or equal to the 155 * requested period. Hence, for lower rates, double the 156 * required_clk_rate to get a clock rate that can meet 157 * the requested period. 158 */ 159 required_clk_rate *= 2; 160 161 err = dev_pm_opp_set_rate(pc->dev, required_clk_rate); 162 if (err < 0) 163 return -EINVAL; 164 165 /* Store the new rate for further references */ 166 pc->clk_rate = clk_get_rate(pc->clk); 167 } 168 169 /* Consider precision in PWM_SCALE_WIDTH rate calculation */ 170 rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns, 171 (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH); 172 173 /* 174 * Since the actual PWM divider is the register's frequency divider 175 * field plus 1, we need to decrement to get the correct value to 176 * write to the register. 177 */ 178 if (rate > 0) 179 rate--; 180 else 181 return -EINVAL; 182 183 /* 184 * Make sure that the rate will fit in the register's frequency 185 * divider field. 186 */ 187 if (rate >> PWM_SCALE_WIDTH) 188 return -EINVAL; 189 190 val |= rate << PWM_SCALE_SHIFT; 191 192 /* 193 * If the PWM channel is disabled, make sure to turn on the clock 194 * before writing the register. Otherwise, keep it enabled. 195 */ 196 if (!pwm_is_enabled(pwm)) { 197 err = pm_runtime_resume_and_get(pc->dev); 198 if (err) 199 return err; 200 } else 201 val |= PWM_ENABLE; 202 203 pwm_writel(pc, pwm->hwpwm, val); 204 205 /* 206 * If the PWM is not enabled, turn the clock off again to save power. 207 */ 208 if (!pwm_is_enabled(pwm)) 209 pm_runtime_put(pc->dev); 210 211 return 0; 212 } 213 214 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 215 { 216 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 217 int rc = 0; 218 u32 val; 219 220 rc = pm_runtime_resume_and_get(pc->dev); 221 if (rc) 222 return rc; 223 224 val = pwm_readl(pc, pwm->hwpwm); 225 val |= PWM_ENABLE; 226 pwm_writel(pc, pwm->hwpwm, val); 227 228 return 0; 229 } 230 231 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 232 { 233 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 234 u32 val; 235 236 val = pwm_readl(pc, pwm->hwpwm); 237 val &= ~PWM_ENABLE; 238 pwm_writel(pc, pwm->hwpwm, val); 239 240 pm_runtime_put_sync(pc->dev); 241 } 242 243 static int tegra_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 244 const struct pwm_state *state) 245 { 246 int err; 247 bool enabled = pwm->state.enabled; 248 249 if (state->polarity != PWM_POLARITY_NORMAL) 250 return -EINVAL; 251 252 if (!state->enabled) { 253 if (enabled) 254 tegra_pwm_disable(chip, pwm); 255 256 return 0; 257 } 258 259 err = tegra_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period); 260 if (err) 261 return err; 262 263 if (!enabled) 264 err = tegra_pwm_enable(chip, pwm); 265 266 return err; 267 } 268 269 static const struct pwm_ops tegra_pwm_ops = { 270 .apply = tegra_pwm_apply, 271 }; 272 273 static int tegra_pwm_probe(struct platform_device *pdev) 274 { 275 struct tegra_pwm_chip *pc; 276 int ret; 277 278 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 279 if (!pc) 280 return -ENOMEM; 281 282 pc->soc = of_device_get_match_data(&pdev->dev); 283 pc->dev = &pdev->dev; 284 285 pc->regs = devm_platform_ioremap_resource(pdev, 0); 286 if (IS_ERR(pc->regs)) 287 return PTR_ERR(pc->regs); 288 289 platform_set_drvdata(pdev, pc); 290 291 pc->clk = devm_clk_get(&pdev->dev, NULL); 292 if (IS_ERR(pc->clk)) 293 return PTR_ERR(pc->clk); 294 295 ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 296 if (ret) 297 return ret; 298 299 pm_runtime_enable(&pdev->dev); 300 ret = pm_runtime_resume_and_get(&pdev->dev); 301 if (ret) 302 return ret; 303 304 /* Set maximum frequency of the IP */ 305 ret = dev_pm_opp_set_rate(pc->dev, pc->soc->max_frequency); 306 if (ret < 0) { 307 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); 308 goto put_pm; 309 } 310 311 /* 312 * The requested and configured frequency may differ due to 313 * clock register resolutions. Get the configured frequency 314 * so that PWM period can be calculated more accurately. 315 */ 316 pc->clk_rate = clk_get_rate(pc->clk); 317 318 /* Set minimum limit of PWM period for the IP */ 319 pc->min_period_ns = 320 (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1; 321 322 pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); 323 if (IS_ERR(pc->rst)) { 324 ret = PTR_ERR(pc->rst); 325 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret); 326 goto put_pm; 327 } 328 329 reset_control_deassert(pc->rst); 330 331 pc->chip.dev = &pdev->dev; 332 pc->chip.ops = &tegra_pwm_ops; 333 pc->chip.npwm = pc->soc->num_channels; 334 335 ret = pwmchip_add(&pc->chip); 336 if (ret < 0) { 337 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 338 reset_control_assert(pc->rst); 339 goto put_pm; 340 } 341 342 pm_runtime_put(&pdev->dev); 343 344 return 0; 345 put_pm: 346 pm_runtime_put_sync_suspend(&pdev->dev); 347 pm_runtime_force_suspend(&pdev->dev); 348 return ret; 349 } 350 351 static void tegra_pwm_remove(struct platform_device *pdev) 352 { 353 struct tegra_pwm_chip *pc = platform_get_drvdata(pdev); 354 355 pwmchip_remove(&pc->chip); 356 357 reset_control_assert(pc->rst); 358 359 pm_runtime_force_suspend(&pdev->dev); 360 } 361 362 static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev) 363 { 364 struct tegra_pwm_chip *pc = dev_get_drvdata(dev); 365 int err; 366 367 clk_disable_unprepare(pc->clk); 368 369 err = pinctrl_pm_select_sleep_state(dev); 370 if (err) { 371 clk_prepare_enable(pc->clk); 372 return err; 373 } 374 375 return 0; 376 } 377 378 static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev) 379 { 380 struct tegra_pwm_chip *pc = dev_get_drvdata(dev); 381 int err; 382 383 err = pinctrl_pm_select_default_state(dev); 384 if (err) 385 return err; 386 387 err = clk_prepare_enable(pc->clk); 388 if (err) { 389 pinctrl_pm_select_sleep_state(dev); 390 return err; 391 } 392 393 return 0; 394 } 395 396 static const struct tegra_pwm_soc tegra20_pwm_soc = { 397 .num_channels = 4, 398 .max_frequency = 48000000UL, 399 }; 400 401 static const struct tegra_pwm_soc tegra186_pwm_soc = { 402 .num_channels = 1, 403 .max_frequency = 102000000UL, 404 }; 405 406 static const struct tegra_pwm_soc tegra194_pwm_soc = { 407 .num_channels = 1, 408 .max_frequency = 408000000UL, 409 }; 410 411 static const struct of_device_id tegra_pwm_of_match[] = { 412 { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc }, 413 { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc }, 414 { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc }, 415 { } 416 }; 417 MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); 418 419 static const struct dev_pm_ops tegra_pwm_pm_ops = { 420 SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume, 421 NULL) 422 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 423 pm_runtime_force_resume) 424 }; 425 426 static struct platform_driver tegra_pwm_driver = { 427 .driver = { 428 .name = "tegra-pwm", 429 .of_match_table = tegra_pwm_of_match, 430 .pm = &tegra_pwm_pm_ops, 431 }, 432 .probe = tegra_pwm_probe, 433 .remove_new = tegra_pwm_remove, 434 }; 435 436 module_platform_driver(tegra_pwm_driver); 437 438 MODULE_LICENSE("GPL"); 439 MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>"); 440 MODULE_DESCRIPTION("Tegra PWM controller driver"); 441 MODULE_ALIAS("platform:tegra-pwm"); 442