1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/pwm/pwm-tegra.c 4 * 5 * Tegra pulse-width-modulation controller driver 6 * 7 * Copyright (c) 2010-2020, NVIDIA Corporation. 8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de> 9 * 10 * Overview of Tegra Pulse Width Modulator Register: 11 * 1. 13-bit: Frequency division (SCALE) 12 * 2. 8-bit : Pulse division (DUTY) 13 * 3. 1-bit : Enable bit 14 * 15 * The PWM clock frequency is divided by 256 before subdividing it based 16 * on the programmable frequency division value to generate the required 17 * frequency for PWM output. The maximum output frequency that can be 18 * achieved is (max rate of source clock) / 256. 19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be: 20 * 408 MHz/256 = 1.6 MHz. 21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM. 22 * 23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width. 24 * To achieve 100% duty cycle, program Bit [24] of this register to 25 * 1’b1. In which case the other bits [23:16] are set to don't care. 26 * 27 * Limitations: 28 * - When PWM is disabled, the output is driven to inactive. 29 * - It does not allow the current PWM period to complete and 30 * stops abruptly. 31 * 32 * - If the register is reconfigured while PWM is running, 33 * it does not complete the currently running period. 34 * 35 * - If the user input duty is beyond acceptible limits, 36 * -EINVAL is returned. 37 */ 38 39 #include <linux/clk.h> 40 #include <linux/err.h> 41 #include <linux/io.h> 42 #include <linux/module.h> 43 #include <linux/of.h> 44 #include <linux/of_device.h> 45 #include <linux/pm_opp.h> 46 #include <linux/pwm.h> 47 #include <linux/platform_device.h> 48 #include <linux/pinctrl/consumer.h> 49 #include <linux/pm_runtime.h> 50 #include <linux/slab.h> 51 #include <linux/reset.h> 52 53 #include <soc/tegra/common.h> 54 55 #define PWM_ENABLE (1 << 31) 56 #define PWM_DUTY_WIDTH 8 57 #define PWM_DUTY_SHIFT 16 58 #define PWM_SCALE_WIDTH 13 59 #define PWM_SCALE_SHIFT 0 60 61 struct tegra_pwm_soc { 62 unsigned int num_channels; 63 64 /* Maximum IP frequency for given SoCs */ 65 unsigned long max_frequency; 66 }; 67 68 struct tegra_pwm_chip { 69 struct pwm_chip chip; 70 struct device *dev; 71 72 struct clk *clk; 73 struct reset_control*rst; 74 75 unsigned long clk_rate; 76 unsigned long min_period_ns; 77 78 void __iomem *regs; 79 80 const struct tegra_pwm_soc *soc; 81 }; 82 83 static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) 84 { 85 return container_of(chip, struct tegra_pwm_chip, chip); 86 } 87 88 static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset) 89 { 90 return readl(pc->regs + (offset << 4)); 91 } 92 93 static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value) 94 { 95 writel(value, pc->regs + (offset << 4)); 96 } 97 98 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 99 int duty_ns, int period_ns) 100 { 101 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 102 unsigned long long c = duty_ns; 103 unsigned long rate, required_clk_rate; 104 u32 val = 0; 105 int err; 106 107 /* 108 * Convert from duty_ns / period_ns to a fixed number of duty ticks 109 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the 110 * nearest integer during division. 111 */ 112 c *= (1 << PWM_DUTY_WIDTH); 113 c = DIV_ROUND_CLOSEST_ULL(c, period_ns); 114 115 val = (u32)c << PWM_DUTY_SHIFT; 116 117 /* 118 * min period = max clock limit >> PWM_DUTY_WIDTH 119 */ 120 if (period_ns < pc->min_period_ns) 121 return -EINVAL; 122 123 /* 124 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) 125 * cycles at the PWM clock rate will take period_ns nanoseconds. 126 * 127 * num_channels: If single instance of PWM controller has multiple 128 * channels (e.g. Tegra210 or older) then it is not possible to 129 * configure separate clock rates to each of the channels, in such 130 * case the value stored during probe will be referred. 131 * 132 * If every PWM controller instance has one channel respectively, i.e. 133 * nums_channels == 1 then only the clock rate can be modified 134 * dynamically (e.g. Tegra186 or Tegra194). 135 */ 136 if (pc->soc->num_channels == 1) { 137 /* 138 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches 139 * with the maximum possible rate that the controller can 140 * provide. Any further lower value can be derived by setting 141 * PFM bits[0:12]. 142 * 143 * required_clk_rate is a reference rate for source clock and 144 * it is derived based on user requested period. By setting the 145 * source clock rate as required_clk_rate, PWM controller will 146 * be able to configure the requested period. 147 */ 148 required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH, 149 period_ns); 150 151 if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate)) 152 /* 153 * required_clk_rate is a lower bound for the input 154 * rate; for lower rates there is no value for PWM_SCALE 155 * that yields a period less than or equal to the 156 * requested period. Hence, for lower rates, double the 157 * required_clk_rate to get a clock rate that can meet 158 * the requested period. 159 */ 160 required_clk_rate *= 2; 161 162 err = dev_pm_opp_set_rate(pc->dev, required_clk_rate); 163 if (err < 0) 164 return -EINVAL; 165 166 /* Store the new rate for further references */ 167 pc->clk_rate = clk_get_rate(pc->clk); 168 } 169 170 /* Consider precision in PWM_SCALE_WIDTH rate calculation */ 171 rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns, 172 (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH); 173 174 /* 175 * Since the actual PWM divider is the register's frequency divider 176 * field plus 1, we need to decrement to get the correct value to 177 * write to the register. 178 */ 179 if (rate > 0) 180 rate--; 181 else 182 return -EINVAL; 183 184 /* 185 * Make sure that the rate will fit in the register's frequency 186 * divider field. 187 */ 188 if (rate >> PWM_SCALE_WIDTH) 189 return -EINVAL; 190 191 val |= rate << PWM_SCALE_SHIFT; 192 193 /* 194 * If the PWM channel is disabled, make sure to turn on the clock 195 * before writing the register. Otherwise, keep it enabled. 196 */ 197 if (!pwm_is_enabled(pwm)) { 198 err = pm_runtime_resume_and_get(pc->dev); 199 if (err) 200 return err; 201 } else 202 val |= PWM_ENABLE; 203 204 pwm_writel(pc, pwm->hwpwm, val); 205 206 /* 207 * If the PWM is not enabled, turn the clock off again to save power. 208 */ 209 if (!pwm_is_enabled(pwm)) 210 pm_runtime_put(pc->dev); 211 212 return 0; 213 } 214 215 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 216 { 217 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 218 int rc = 0; 219 u32 val; 220 221 rc = pm_runtime_resume_and_get(pc->dev); 222 if (rc) 223 return rc; 224 225 val = pwm_readl(pc, pwm->hwpwm); 226 val |= PWM_ENABLE; 227 pwm_writel(pc, pwm->hwpwm, val); 228 229 return 0; 230 } 231 232 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 233 { 234 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 235 u32 val; 236 237 val = pwm_readl(pc, pwm->hwpwm); 238 val &= ~PWM_ENABLE; 239 pwm_writel(pc, pwm->hwpwm, val); 240 241 pm_runtime_put_sync(pc->dev); 242 } 243 244 static int tegra_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 245 const struct pwm_state *state) 246 { 247 int err; 248 bool enabled = pwm->state.enabled; 249 250 if (state->polarity != PWM_POLARITY_NORMAL) 251 return -EINVAL; 252 253 if (!state->enabled) { 254 if (enabled) 255 tegra_pwm_disable(chip, pwm); 256 257 return 0; 258 } 259 260 err = tegra_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period); 261 if (err) 262 return err; 263 264 if (!enabled) 265 err = tegra_pwm_enable(chip, pwm); 266 267 return err; 268 } 269 270 static const struct pwm_ops tegra_pwm_ops = { 271 .apply = tegra_pwm_apply, 272 .owner = THIS_MODULE, 273 }; 274 275 static int tegra_pwm_probe(struct platform_device *pdev) 276 { 277 struct tegra_pwm_chip *pc; 278 int ret; 279 280 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 281 if (!pc) 282 return -ENOMEM; 283 284 pc->soc = of_device_get_match_data(&pdev->dev); 285 pc->dev = &pdev->dev; 286 287 pc->regs = devm_platform_ioremap_resource(pdev, 0); 288 if (IS_ERR(pc->regs)) 289 return PTR_ERR(pc->regs); 290 291 platform_set_drvdata(pdev, pc); 292 293 pc->clk = devm_clk_get(&pdev->dev, NULL); 294 if (IS_ERR(pc->clk)) 295 return PTR_ERR(pc->clk); 296 297 ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 298 if (ret) 299 return ret; 300 301 pm_runtime_enable(&pdev->dev); 302 ret = pm_runtime_resume_and_get(&pdev->dev); 303 if (ret) 304 return ret; 305 306 /* Set maximum frequency of the IP */ 307 ret = dev_pm_opp_set_rate(pc->dev, pc->soc->max_frequency); 308 if (ret < 0) { 309 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); 310 goto put_pm; 311 } 312 313 /* 314 * The requested and configured frequency may differ due to 315 * clock register resolutions. Get the configured frequency 316 * so that PWM period can be calculated more accurately. 317 */ 318 pc->clk_rate = clk_get_rate(pc->clk); 319 320 /* Set minimum limit of PWM period for the IP */ 321 pc->min_period_ns = 322 (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1; 323 324 pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); 325 if (IS_ERR(pc->rst)) { 326 ret = PTR_ERR(pc->rst); 327 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret); 328 goto put_pm; 329 } 330 331 reset_control_deassert(pc->rst); 332 333 pc->chip.dev = &pdev->dev; 334 pc->chip.ops = &tegra_pwm_ops; 335 pc->chip.npwm = pc->soc->num_channels; 336 337 ret = pwmchip_add(&pc->chip); 338 if (ret < 0) { 339 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 340 reset_control_assert(pc->rst); 341 goto put_pm; 342 } 343 344 pm_runtime_put(&pdev->dev); 345 346 return 0; 347 put_pm: 348 pm_runtime_put_sync_suspend(&pdev->dev); 349 pm_runtime_force_suspend(&pdev->dev); 350 return ret; 351 } 352 353 static void tegra_pwm_remove(struct platform_device *pdev) 354 { 355 struct tegra_pwm_chip *pc = platform_get_drvdata(pdev); 356 357 pwmchip_remove(&pc->chip); 358 359 reset_control_assert(pc->rst); 360 361 pm_runtime_force_suspend(&pdev->dev); 362 } 363 364 static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev) 365 { 366 struct tegra_pwm_chip *pc = dev_get_drvdata(dev); 367 int err; 368 369 clk_disable_unprepare(pc->clk); 370 371 err = pinctrl_pm_select_sleep_state(dev); 372 if (err) { 373 clk_prepare_enable(pc->clk); 374 return err; 375 } 376 377 return 0; 378 } 379 380 static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev) 381 { 382 struct tegra_pwm_chip *pc = dev_get_drvdata(dev); 383 int err; 384 385 err = pinctrl_pm_select_default_state(dev); 386 if (err) 387 return err; 388 389 err = clk_prepare_enable(pc->clk); 390 if (err) { 391 pinctrl_pm_select_sleep_state(dev); 392 return err; 393 } 394 395 return 0; 396 } 397 398 static const struct tegra_pwm_soc tegra20_pwm_soc = { 399 .num_channels = 4, 400 .max_frequency = 48000000UL, 401 }; 402 403 static const struct tegra_pwm_soc tegra186_pwm_soc = { 404 .num_channels = 1, 405 .max_frequency = 102000000UL, 406 }; 407 408 static const struct tegra_pwm_soc tegra194_pwm_soc = { 409 .num_channels = 1, 410 .max_frequency = 408000000UL, 411 }; 412 413 static const struct of_device_id tegra_pwm_of_match[] = { 414 { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc }, 415 { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc }, 416 { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc }, 417 { } 418 }; 419 MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); 420 421 static const struct dev_pm_ops tegra_pwm_pm_ops = { 422 SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume, 423 NULL) 424 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 425 pm_runtime_force_resume) 426 }; 427 428 static struct platform_driver tegra_pwm_driver = { 429 .driver = { 430 .name = "tegra-pwm", 431 .of_match_table = tegra_pwm_of_match, 432 .pm = &tegra_pwm_pm_ops, 433 }, 434 .probe = tegra_pwm_probe, 435 .remove_new = tegra_pwm_remove, 436 }; 437 438 module_platform_driver(tegra_pwm_driver); 439 440 MODULE_LICENSE("GPL"); 441 MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>"); 442 MODULE_DESCRIPTION("Tegra PWM controller driver"); 443 MODULE_ALIAS("platform:tegra-pwm"); 444