1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for Allwinner sun4i Pulse Width Modulation Controller 4 * 5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> 6 * 7 * Limitations: 8 * - When outputing the source clock directly, the PWM logic will be bypassed 9 * and the currently running period is not guaranteed to be completed 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/jiffies.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/pwm.h> 22 #include <linux/reset.h> 23 #include <linux/slab.h> 24 #include <linux/time.h> 25 26 #define PWM_CTRL_REG 0x0 27 28 #define PWM_CH_PRD_BASE 0x4 29 #define PWM_CH_PRD_OFFSET 0x4 30 #define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch)) 31 32 #define PWMCH_OFFSET 15 33 #define PWM_PRESCAL_MASK GENMASK(3, 0) 34 #define PWM_PRESCAL_OFF 0 35 #define PWM_EN BIT(4) 36 #define PWM_ACT_STATE BIT(5) 37 #define PWM_CLK_GATING BIT(6) 38 #define PWM_MODE BIT(7) 39 #define PWM_PULSE BIT(8) 40 #define PWM_BYPASS BIT(9) 41 42 #define PWM_RDY_BASE 28 43 #define PWM_RDY_OFFSET 1 44 #define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch)) 45 46 #define PWM_PRD(prd) (((prd) - 1) << 16) 47 #define PWM_PRD_MASK GENMASK(15, 0) 48 49 #define PWM_DTY_MASK GENMASK(15, 0) 50 51 #define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1) 52 #define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK) 53 #define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK) 54 55 #define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET)) 56 57 static const u32 prescaler_table[] = { 58 120, 59 180, 60 240, 61 360, 62 480, 63 0, 64 0, 65 0, 66 12000, 67 24000, 68 36000, 69 48000, 70 72000, 71 0, 72 0, 73 0, /* Actually 1 but tested separately */ 74 }; 75 76 struct sun4i_pwm_data { 77 bool has_prescaler_bypass; 78 bool has_direct_mod_clk_output; 79 unsigned int npwm; 80 }; 81 82 struct sun4i_pwm_chip { 83 struct clk *bus_clk; 84 struct clk *clk; 85 struct reset_control *rst; 86 void __iomem *base; 87 const struct sun4i_pwm_data *data; 88 }; 89 90 static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip) 91 { 92 return pwmchip_get_drvdata(chip); 93 } 94 95 static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *sun4ichip, 96 unsigned long offset) 97 { 98 return readl(sun4ichip->base + offset); 99 } 100 101 static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *sun4ichip, 102 u32 val, unsigned long offset) 103 { 104 writel(val, sun4ichip->base + offset); 105 } 106 107 static int sun4i_pwm_get_state(struct pwm_chip *chip, 108 struct pwm_device *pwm, 109 struct pwm_state *state) 110 { 111 struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip); 112 u64 clk_rate, tmp; 113 u32 val; 114 unsigned int prescaler; 115 116 clk_rate = clk_get_rate(sun4ichip->clk); 117 if (!clk_rate) 118 return -EINVAL; 119 120 val = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG); 121 122 /* 123 * PWM chapter in H6 manual has a diagram which explains that if bypass 124 * bit is set, no other setting has any meaning. Even more, experiment 125 * proved that also enable bit is ignored in this case. 126 */ 127 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && 128 sun4ichip->data->has_direct_mod_clk_output) { 129 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); 130 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); 131 state->polarity = PWM_POLARITY_NORMAL; 132 state->enabled = true; 133 return 0; 134 } 135 136 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && 137 sun4ichip->data->has_prescaler_bypass) 138 prescaler = 1; 139 else 140 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; 141 142 if (prescaler == 0) 143 return -EINVAL; 144 145 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) 146 state->polarity = PWM_POLARITY_NORMAL; 147 else 148 state->polarity = PWM_POLARITY_INVERSED; 149 150 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == 151 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) 152 state->enabled = true; 153 else 154 state->enabled = false; 155 156 val = sun4i_pwm_readl(sun4ichip, PWM_CH_PRD(pwm->hwpwm)); 157 158 tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val); 159 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 160 161 tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val); 162 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 163 164 return 0; 165 } 166 167 static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4ichip, 168 const struct pwm_state *state, 169 u32 *dty, u32 *prd, unsigned int *prsclr, 170 bool *bypass) 171 { 172 u64 clk_rate, div = 0; 173 unsigned int prescaler = 0; 174 175 clk_rate = clk_get_rate(sun4ichip->clk); 176 177 *bypass = sun4ichip->data->has_direct_mod_clk_output && 178 state->enabled && 179 (state->period * clk_rate >= NSEC_PER_SEC) && 180 (state->period * clk_rate < 2 * NSEC_PER_SEC) && 181 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); 182 183 /* Skip calculation of other parameters if we bypass them */ 184 if (*bypass) 185 return 0; 186 187 if (sun4ichip->data->has_prescaler_bypass) { 188 /* First, test without any prescaler when available */ 189 prescaler = PWM_PRESCAL_MASK; 190 /* 191 * When not using any prescaler, the clock period in nanoseconds 192 * is not an integer so round it half up instead of 193 * truncating to get less surprising values. 194 */ 195 div = clk_rate * state->period + NSEC_PER_SEC / 2; 196 do_div(div, NSEC_PER_SEC); 197 if (div - 1 > PWM_PRD_MASK) 198 prescaler = 0; 199 } 200 201 if (prescaler == 0) { 202 /* Go up from the first divider */ 203 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) { 204 unsigned int pval = prescaler_table[prescaler]; 205 206 if (!pval) 207 continue; 208 209 div = clk_rate; 210 do_div(div, pval); 211 div = div * state->period; 212 do_div(div, NSEC_PER_SEC); 213 if (div - 1 <= PWM_PRD_MASK) 214 break; 215 } 216 217 if (div - 1 > PWM_PRD_MASK) 218 return -EINVAL; 219 } 220 221 *prd = div; 222 div *= state->duty_cycle; 223 do_div(div, state->period); 224 *dty = div; 225 *prsclr = prescaler; 226 227 return 0; 228 } 229 230 static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 231 const struct pwm_state *state) 232 { 233 struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip); 234 struct pwm_state cstate; 235 u32 ctrl, duty = 0, period = 0, val; 236 int ret; 237 unsigned int delay_us, prescaler = 0; 238 bool bypass; 239 240 pwm_get_state(pwm, &cstate); 241 242 if (!cstate.enabled) { 243 ret = clk_prepare_enable(sun4ichip->clk); 244 if (ret) { 245 dev_err(pwmchip_parent(chip), "failed to enable PWM clock\n"); 246 return ret; 247 } 248 } 249 250 ret = sun4i_pwm_calculate(sun4ichip, state, &duty, &period, &prescaler, 251 &bypass); 252 if (ret) { 253 dev_err(pwmchip_parent(chip), "period exceeds the maximum value\n"); 254 if (!cstate.enabled) 255 clk_disable_unprepare(sun4ichip->clk); 256 return ret; 257 } 258 259 ctrl = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG); 260 261 if (sun4ichip->data->has_direct_mod_clk_output) { 262 if (bypass) { 263 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); 264 /* We can skip other parameter */ 265 sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG); 266 return 0; 267 } 268 269 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); 270 } 271 272 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { 273 /* Prescaler changed, the clock has to be gated */ 274 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); 275 sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG); 276 277 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); 278 ctrl |= BIT_CH(prescaler, pwm->hwpwm); 279 } 280 281 val = (duty & PWM_DTY_MASK) | PWM_PRD(period); 282 sun4i_pwm_writel(sun4ichip, val, PWM_CH_PRD(pwm->hwpwm)); 283 284 if (state->polarity != PWM_POLARITY_NORMAL) 285 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); 286 else 287 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); 288 289 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); 290 291 if (state->enabled) 292 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); 293 294 sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG); 295 296 if (state->enabled) 297 return 0; 298 299 /* We need a full period to elapse before disabling the channel. */ 300 delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC); 301 if ((delay_us / 500) > MAX_UDELAY_MS) 302 msleep(delay_us / 1000 + 1); 303 else 304 usleep_range(delay_us, delay_us * 2); 305 306 ctrl = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG); 307 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); 308 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm); 309 sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG); 310 311 clk_disable_unprepare(sun4ichip->clk); 312 313 return 0; 314 } 315 316 static const struct pwm_ops sun4i_pwm_ops = { 317 .apply = sun4i_pwm_apply, 318 .get_state = sun4i_pwm_get_state, 319 }; 320 321 static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = { 322 .has_prescaler_bypass = false, 323 .npwm = 2, 324 }; 325 326 static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = { 327 .has_prescaler_bypass = true, 328 .npwm = 2, 329 }; 330 331 static const struct sun4i_pwm_data sun4i_pwm_single_bypass = { 332 .has_prescaler_bypass = true, 333 .npwm = 1, 334 }; 335 336 static const struct sun4i_pwm_data sun50i_a64_pwm_data = { 337 .has_prescaler_bypass = true, 338 .has_direct_mod_clk_output = true, 339 .npwm = 1, 340 }; 341 342 static const struct sun4i_pwm_data sun50i_h6_pwm_data = { 343 .has_prescaler_bypass = true, 344 .has_direct_mod_clk_output = true, 345 .npwm = 2, 346 }; 347 348 static const struct of_device_id sun4i_pwm_dt_ids[] = { 349 { 350 .compatible = "allwinner,sun4i-a10-pwm", 351 .data = &sun4i_pwm_dual_nobypass, 352 }, { 353 .compatible = "allwinner,sun5i-a10s-pwm", 354 .data = &sun4i_pwm_dual_bypass, 355 }, { 356 .compatible = "allwinner,sun5i-a13-pwm", 357 .data = &sun4i_pwm_single_bypass, 358 }, { 359 .compatible = "allwinner,sun7i-a20-pwm", 360 .data = &sun4i_pwm_dual_bypass, 361 }, { 362 .compatible = "allwinner,sun8i-h3-pwm", 363 .data = &sun4i_pwm_single_bypass, 364 }, { 365 .compatible = "allwinner,sun50i-a64-pwm", 366 .data = &sun50i_a64_pwm_data, 367 }, { 368 .compatible = "allwinner,sun50i-h6-pwm", 369 .data = &sun50i_h6_pwm_data, 370 }, { 371 /* sentinel */ 372 }, 373 }; 374 MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids); 375 376 static int sun4i_pwm_probe(struct platform_device *pdev) 377 { 378 struct pwm_chip *chip; 379 const struct sun4i_pwm_data *data; 380 struct sun4i_pwm_chip *sun4ichip; 381 int ret; 382 383 data = of_device_get_match_data(&pdev->dev); 384 if (!data) 385 return -ENODEV; 386 387 chip = devm_pwmchip_alloc(&pdev->dev, data->npwm, sizeof(*sun4ichip)); 388 if (IS_ERR(chip)) 389 return PTR_ERR(chip); 390 sun4ichip = to_sun4i_pwm_chip(chip); 391 392 sun4ichip->data = data; 393 sun4ichip->base = devm_platform_ioremap_resource(pdev, 0); 394 if (IS_ERR(sun4ichip->base)) 395 return PTR_ERR(sun4ichip->base); 396 397 /* 398 * All hardware variants need a source clock that is divided and 399 * then feeds the counter that defines the output wave form. In the 400 * device tree this clock is either unnamed or called "mod". 401 * Some variants (e.g. H6) need another clock to access the 402 * hardware registers; this is called "bus". 403 * So we request "mod" first (and ignore the corner case that a 404 * parent provides a "mod" clock while the right one would be the 405 * unnamed one of the PWM device) and if this is not found we fall 406 * back to the first clock of the PWM. 407 */ 408 sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod"); 409 if (IS_ERR(sun4ichip->clk)) 410 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk), 411 "get mod clock failed\n"); 412 413 if (!sun4ichip->clk) { 414 sun4ichip->clk = devm_clk_get(&pdev->dev, NULL); 415 if (IS_ERR(sun4ichip->clk)) 416 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk), 417 "get unnamed clock failed\n"); 418 } 419 420 sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); 421 if (IS_ERR(sun4ichip->bus_clk)) 422 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk), 423 "get bus clock failed\n"); 424 425 sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); 426 if (IS_ERR(sun4ichip->rst)) 427 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst), 428 "get reset failed\n"); 429 430 /* Deassert reset */ 431 ret = reset_control_deassert(sun4ichip->rst); 432 if (ret) { 433 dev_err(&pdev->dev, "cannot deassert reset control: %pe\n", 434 ERR_PTR(ret)); 435 return ret; 436 } 437 438 /* 439 * We're keeping the bus clock on for the sake of simplicity. 440 * Actually it only needs to be on for hardware register accesses. 441 */ 442 ret = clk_prepare_enable(sun4ichip->bus_clk); 443 if (ret) { 444 dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n", 445 ERR_PTR(ret)); 446 goto err_bus; 447 } 448 449 chip->ops = &sun4i_pwm_ops; 450 451 ret = pwmchip_add(chip); 452 if (ret < 0) { 453 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); 454 goto err_pwm_add; 455 } 456 457 platform_set_drvdata(pdev, chip); 458 459 return 0; 460 461 err_pwm_add: 462 clk_disable_unprepare(sun4ichip->bus_clk); 463 err_bus: 464 reset_control_assert(sun4ichip->rst); 465 466 return ret; 467 } 468 469 static void sun4i_pwm_remove(struct platform_device *pdev) 470 { 471 struct pwm_chip *chip = platform_get_drvdata(pdev); 472 struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip); 473 474 pwmchip_remove(chip); 475 476 clk_disable_unprepare(sun4ichip->bus_clk); 477 reset_control_assert(sun4ichip->rst); 478 } 479 480 static struct platform_driver sun4i_pwm_driver = { 481 .driver = { 482 .name = "sun4i-pwm", 483 .of_match_table = sun4i_pwm_dt_ids, 484 }, 485 .probe = sun4i_pwm_probe, 486 .remove = sun4i_pwm_remove, 487 }; 488 module_platform_driver(sun4i_pwm_driver); 489 490 MODULE_ALIAS("platform:sun4i-pwm"); 491 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>"); 492 MODULE_DESCRIPTION("Allwinner sun4i PWM driver"); 493 MODULE_LICENSE("GPL v2"); 494