1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2016 4 * 5 * Author: Gerald Baeza <gerald.baeza@st.com> 6 * 7 * Inspired by timer-stm32.c from Maxime Coquelin 8 * pwm-atmel.c from Bo Shen 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/mfd/stm32-timers.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/platform_device.h> 17 #include <linux/pwm.h> 18 19 #define CCMR_CHANNEL_SHIFT 8 20 #define CCMR_CHANNEL_MASK 0xFF 21 #define MAX_BREAKINPUT 2 22 23 struct stm32_breakinput { 24 u32 index; 25 u32 level; 26 u32 filter; 27 }; 28 29 struct stm32_pwm { 30 struct mutex lock; /* protect pwm config/enable */ 31 struct clk *clk; 32 struct regmap *regmap; 33 u32 max_arr; 34 bool have_complementary_output; 35 struct stm32_breakinput breakinputs[MAX_BREAKINPUT]; 36 unsigned int num_breakinputs; 37 u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */ 38 }; 39 40 static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip) 41 { 42 return pwmchip_get_drvdata(chip); 43 } 44 45 static u32 active_channels(struct stm32_pwm *dev) 46 { 47 u32 ccer; 48 49 regmap_read(dev->regmap, TIM_CCER, &ccer); 50 51 return ccer & TIM_CCER_CCXE; 52 } 53 54 #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P) 55 #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E) 56 #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P) 57 #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E) 58 59 /* 60 * Capture using PWM input mode: 61 * ___ ___ 62 * TI[1, 2, 3 or 4]: ........._| |________| 63 * ^0 ^1 ^2 64 * . . . 65 * . . XXXXX 66 * . . XXXXX | 67 * . XXXXX . | 68 * XXXXX . . | 69 * COUNTER: ______XXXXX . . . |_XXX 70 * start^ . . . ^stop 71 * . . . . 72 * v v . v 73 * v 74 * CCR1/CCR3: tx..........t0...........t2 75 * CCR2/CCR4: tx..............t1......... 76 * 77 * DMA burst transfer: | | 78 * v v 79 * DMA buffer: { t0, tx } { t2, t1 } 80 * DMA done: ^ 81 * 82 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 83 * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care) 84 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4 85 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 86 * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1) 87 * 88 * DMA done, compute: 89 * - Period = t2 - t0 90 * - Duty cycle = t1 - t0 91 */ 92 static int stm32_pwm_raw_capture(struct pwm_chip *chip, struct pwm_device *pwm, 93 unsigned long tmo_ms, u32 *raw_prd, 94 u32 *raw_dty) 95 { 96 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 97 struct device *parent = pwmchip_parent(chip)->parent; 98 enum stm32_timers_dmas dma_id; 99 u32 ccen, ccr; 100 int ret; 101 102 /* Ensure registers have been updated, enable counter and capture */ 103 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); 104 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 105 106 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */ 107 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; 108 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; 109 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; 110 regmap_set_bits(priv->regmap, TIM_CCER, ccen); 111 112 /* 113 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both 114 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event. 115 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 } 116 * or { CCR3, CCR4 }, { CCR3, CCR4 } 117 */ 118 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2, 119 2, tmo_ms); 120 if (ret) 121 goto stop; 122 123 /* Period: t2 - t0 (take care of counter overflow) */ 124 if (priv->capture[0] <= priv->capture[2]) 125 *raw_prd = priv->capture[2] - priv->capture[0]; 126 else 127 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2]; 128 129 /* Duty cycle capture requires at least two capture units */ 130 if (pwm->chip->npwm < 2) 131 *raw_dty = 0; 132 else if (priv->capture[0] <= priv->capture[3]) 133 *raw_dty = priv->capture[3] - priv->capture[0]; 134 else 135 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3]; 136 137 if (*raw_dty > *raw_prd) { 138 /* 139 * Race beetween PWM input and DMA: it may happen 140 * falling edge triggers new capture on TI2/4 before DMA 141 * had a chance to read CCR2/4. It means capture[1] 142 * contains period + duty_cycle. So, subtract period. 143 */ 144 *raw_dty -= *raw_prd; 145 } 146 147 stop: 148 regmap_clear_bits(priv->regmap, TIM_CCER, ccen); 149 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 150 151 return ret; 152 } 153 154 static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, 155 struct pwm_capture *result, unsigned long tmo_ms) 156 { 157 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 158 unsigned long long prd, div, dty; 159 unsigned long rate; 160 unsigned int psc = 0, icpsc, scale; 161 u32 raw_prd = 0, raw_dty = 0; 162 int ret = 0; 163 164 mutex_lock(&priv->lock); 165 166 if (active_channels(priv)) { 167 ret = -EBUSY; 168 goto unlock; 169 } 170 171 ret = clk_enable(priv->clk); 172 if (ret) { 173 dev_err(pwmchip_parent(chip), "failed to enable counter clock\n"); 174 goto unlock; 175 } 176 177 rate = clk_get_rate(priv->clk); 178 if (!rate) { 179 ret = -EINVAL; 180 goto clk_dis; 181 } 182 183 /* prescaler: fit timeout window provided by upper layer */ 184 div = (unsigned long long)rate * (unsigned long long)tmo_ms; 185 do_div(div, MSEC_PER_SEC); 186 prd = div; 187 while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) { 188 psc++; 189 div = prd; 190 do_div(div, psc + 1); 191 } 192 regmap_write(priv->regmap, TIM_ARR, priv->max_arr); 193 regmap_write(priv->regmap, TIM_PSC, psc); 194 195 /* Reset input selector to its default input and disable slave mode */ 196 regmap_write(priv->regmap, TIM_TISEL, 0x0); 197 regmap_write(priv->regmap, TIM_SMCR, 0x0); 198 199 /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */ 200 regmap_update_bits(priv->regmap, 201 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 202 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ? 203 TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 : 204 TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1); 205 206 /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */ 207 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ? 208 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ? 209 TIM_CCER_CC2P : TIM_CCER_CC4P); 210 211 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty); 212 if (ret) 213 goto stop; 214 215 /* 216 * Got a capture. Try to improve accuracy at high rates: 217 * - decrease counter clock prescaler, scale up to max rate. 218 * - use input prescaler, capture once every /2 /4 or /8 edges. 219 */ 220 if (raw_prd) { 221 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */ 222 223 scale = max_arr / min(max_arr, raw_prd); 224 } else { 225 scale = priv->max_arr; /* bellow resolution, use max scale */ 226 } 227 228 if (psc && scale > 1) { 229 /* 2nd measure with new scale */ 230 psc /= scale; 231 regmap_write(priv->regmap, TIM_PSC, psc); 232 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, 233 &raw_dty); 234 if (ret) 235 goto stop; 236 } 237 238 /* Compute intermediate period not to exceed timeout at low rates */ 239 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; 240 do_div(prd, rate); 241 242 for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) { 243 /* input prescaler: also keep arbitrary margin */ 244 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1)) 245 break; 246 if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2)) 247 break; 248 } 249 250 if (!icpsc) 251 goto done; 252 253 /* Last chance to improve period accuracy, using input prescaler */ 254 regmap_update_bits(priv->regmap, 255 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 256 TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC, 257 FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) | 258 FIELD_PREP(TIM_CCMR_IC2PSC, icpsc)); 259 260 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty); 261 if (ret) 262 goto stop; 263 264 if (raw_dty >= (raw_prd >> icpsc)) { 265 /* 266 * We may fall here using input prescaler, when input 267 * capture starts on high side (before falling edge). 268 * Example with icpsc to capture on each 4 events: 269 * 270 * start 1st capture 2nd capture 271 * v v v 272 * ___ _____ _____ _____ _____ ____ 273 * TI1..4 |__| |__| |__| |__| |__| 274 * v v . . . . . v v 275 * icpsc1/3: . 0 . 1 . 2 . 3 . 0 276 * icpsc2/4: 0 1 2 3 0 277 * v v v v 278 * CCR1/3 ......t0..............................t2 279 * CCR2/4 ..t1..............................t1'... 280 * . . . 281 * Capture0: .<----------------------------->. 282 * Capture1: .<-------------------------->. . 283 * . . . 284 * Period: .<------> . . 285 * Low side: .<>. 286 * 287 * Result: 288 * - Period = Capture0 / icpsc 289 * - Duty = Period - Low side = Period - (Capture0 - Capture1) 290 */ 291 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty); 292 } 293 294 done: 295 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; 296 result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc); 297 dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC; 298 result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); 299 stop: 300 regmap_write(priv->regmap, TIM_CCER, 0); 301 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0); 302 regmap_write(priv->regmap, TIM_PSC, 0); 303 clk_dis: 304 clk_disable(priv->clk); 305 unlock: 306 mutex_unlock(&priv->lock); 307 308 return ret; 309 } 310 311 static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch, 312 u64 duty_ns, u64 period_ns) 313 { 314 unsigned long long prd, dty; 315 unsigned long long prescaler; 316 u32 ccmr, mask, shift; 317 318 /* 319 * .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so 320 * the calculations here won't overflow. 321 * First we need to find the minimal value for prescaler such that 322 * 323 * period_ns * clkrate 324 * ------------------------------ < max_arr + 1 325 * NSEC_PER_SEC * (prescaler + 1) 326 * 327 * This equation is equivalent to 328 * 329 * period_ns * clkrate 330 * ---------------------------- < prescaler + 1 331 * NSEC_PER_SEC * (max_arr + 1) 332 * 333 * Using integer division and knowing that the right hand side is 334 * integer, this is further equivalent to 335 * 336 * (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler 337 */ 338 339 prescaler = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk), 340 (u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1)); 341 if (prescaler > MAX_TIM_PSC) 342 return -EINVAL; 343 344 prd = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk), 345 (u64)NSEC_PER_SEC * (prescaler + 1)); 346 if (!prd) 347 return -EINVAL; 348 349 /* 350 * All channels share the same prescaler and counter so when two 351 * channels are active at the same time we can't change them 352 */ 353 if (active_channels(priv) & ~(1 << ch * 4)) { 354 u32 psc, arr; 355 356 regmap_read(priv->regmap, TIM_PSC, &psc); 357 regmap_read(priv->regmap, TIM_ARR, &arr); 358 359 if ((psc != prescaler) || (arr != prd - 1)) 360 return -EBUSY; 361 } 362 363 regmap_write(priv->regmap, TIM_PSC, prescaler); 364 regmap_write(priv->regmap, TIM_ARR, prd - 1); 365 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); 366 367 /* Calculate the duty cycles */ 368 dty = mul_u64_u64_div_u64(duty_ns, clk_get_rate(priv->clk), 369 (u64)NSEC_PER_SEC * (prescaler + 1)); 370 371 regmap_write(priv->regmap, TIM_CCR1 + 4 * ch, dty); 372 373 /* Configure output mode */ 374 shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT; 375 ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift; 376 mask = CCMR_CHANNEL_MASK << shift; 377 378 if (ch < 2) 379 regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr); 380 else 381 regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); 382 383 regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE); 384 385 return 0; 386 } 387 388 static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch, 389 enum pwm_polarity polarity) 390 { 391 u32 mask; 392 393 mask = TIM_CCER_CC1P << (ch * 4); 394 if (priv->have_complementary_output) 395 mask |= TIM_CCER_CC1NP << (ch * 4); 396 397 regmap_update_bits(priv->regmap, TIM_CCER, mask, 398 polarity == PWM_POLARITY_NORMAL ? 0 : mask); 399 400 return 0; 401 } 402 403 static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch) 404 { 405 u32 mask; 406 int ret; 407 408 ret = clk_enable(priv->clk); 409 if (ret) 410 return ret; 411 412 /* Enable channel */ 413 mask = TIM_CCER_CC1E << (ch * 4); 414 if (priv->have_complementary_output) 415 mask |= TIM_CCER_CC1NE << (ch * 4); 416 417 regmap_set_bits(priv->regmap, TIM_CCER, mask); 418 419 /* Make sure that registers are updated */ 420 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); 421 422 /* Enable controller */ 423 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 424 425 return 0; 426 } 427 428 static void stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch) 429 { 430 u32 mask; 431 432 /* Disable channel */ 433 mask = TIM_CCER_CC1E << (ch * 4); 434 if (priv->have_complementary_output) 435 mask |= TIM_CCER_CC1NE << (ch * 4); 436 437 regmap_clear_bits(priv->regmap, TIM_CCER, mask); 438 439 /* When all channels are disabled, we can disable the controller */ 440 if (!active_channels(priv)) 441 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 442 443 clk_disable(priv->clk); 444 } 445 446 static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 447 const struct pwm_state *state) 448 { 449 bool enabled; 450 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 451 int ret; 452 453 enabled = pwm->state.enabled; 454 455 if (enabled && !state->enabled) { 456 stm32_pwm_disable(priv, pwm->hwpwm); 457 return 0; 458 } 459 460 if (state->polarity != pwm->state.polarity) 461 stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity); 462 463 ret = stm32_pwm_config(priv, pwm->hwpwm, 464 state->duty_cycle, state->period); 465 if (ret) 466 return ret; 467 468 if (!enabled && state->enabled) 469 ret = stm32_pwm_enable(priv, pwm->hwpwm); 470 471 return ret; 472 } 473 474 static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm, 475 const struct pwm_state *state) 476 { 477 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 478 int ret; 479 480 /* protect common prescaler for all active channels */ 481 mutex_lock(&priv->lock); 482 ret = stm32_pwm_apply(chip, pwm, state); 483 mutex_unlock(&priv->lock); 484 485 return ret; 486 } 487 488 static int stm32_pwm_get_state(struct pwm_chip *chip, 489 struct pwm_device *pwm, struct pwm_state *state) 490 { 491 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 492 int ch = pwm->hwpwm; 493 unsigned long rate; 494 u32 ccer, psc, arr, ccr; 495 u64 dty, prd; 496 int ret; 497 498 mutex_lock(&priv->lock); 499 500 ret = regmap_read(priv->regmap, TIM_CCER, &ccer); 501 if (ret) 502 goto out; 503 504 state->enabled = ccer & (TIM_CCER_CC1E << (ch * 4)); 505 state->polarity = (ccer & (TIM_CCER_CC1P << (ch * 4))) ? 506 PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; 507 ret = regmap_read(priv->regmap, TIM_PSC, &psc); 508 if (ret) 509 goto out; 510 ret = regmap_read(priv->regmap, TIM_ARR, &arr); 511 if (ret) 512 goto out; 513 ret = regmap_read(priv->regmap, TIM_CCR1 + 4 * ch, &ccr); 514 if (ret) 515 goto out; 516 517 rate = clk_get_rate(priv->clk); 518 519 prd = (u64)NSEC_PER_SEC * (psc + 1) * (arr + 1); 520 state->period = DIV_ROUND_UP_ULL(prd, rate); 521 dty = (u64)NSEC_PER_SEC * (psc + 1) * ccr; 522 state->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); 523 524 out: 525 mutex_unlock(&priv->lock); 526 return ret; 527 } 528 529 static const struct pwm_ops stm32pwm_ops = { 530 .apply = stm32_pwm_apply_locked, 531 .get_state = stm32_pwm_get_state, 532 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL, 533 }; 534 535 static int stm32_pwm_set_breakinput(struct stm32_pwm *priv, 536 const struct stm32_breakinput *bi) 537 { 538 u32 shift = TIM_BDTR_BKF_SHIFT(bi->index); 539 u32 bke = TIM_BDTR_BKE(bi->index); 540 u32 bkp = TIM_BDTR_BKP(bi->index); 541 u32 bkf = TIM_BDTR_BKF(bi->index); 542 u32 mask = bkf | bkp | bke; 543 u32 bdtr; 544 545 bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke; 546 547 if (bi->level) 548 bdtr |= bkp; 549 550 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr); 551 552 regmap_read(priv->regmap, TIM_BDTR, &bdtr); 553 554 return (bdtr & bke) ? 0 : -EINVAL; 555 } 556 557 static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv) 558 { 559 unsigned int i; 560 int ret; 561 562 for (i = 0; i < priv->num_breakinputs; i++) { 563 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]); 564 if (ret < 0) 565 return ret; 566 } 567 568 return 0; 569 } 570 571 static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv, 572 struct device_node *np) 573 { 574 int nb, ret, array_size; 575 unsigned int i; 576 577 nb = of_property_count_elems_of_size(np, "st,breakinput", 578 sizeof(struct stm32_breakinput)); 579 580 /* 581 * Because "st,breakinput" parameter is optional do not make probe 582 * failed if it doesn't exist. 583 */ 584 if (nb <= 0) 585 return 0; 586 587 if (nb > MAX_BREAKINPUT) 588 return -EINVAL; 589 590 priv->num_breakinputs = nb; 591 array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32); 592 ret = of_property_read_u32_array(np, "st,breakinput", 593 (u32 *)priv->breakinputs, array_size); 594 if (ret) 595 return ret; 596 597 for (i = 0; i < priv->num_breakinputs; i++) { 598 if (priv->breakinputs[i].index > 1 || 599 priv->breakinputs[i].level > 1 || 600 priv->breakinputs[i].filter > 15) 601 return -EINVAL; 602 } 603 604 return stm32_pwm_apply_breakinputs(priv); 605 } 606 607 static void stm32_pwm_detect_complementary(struct stm32_pwm *priv) 608 { 609 u32 ccer; 610 611 /* 612 * If complementary bit doesn't exist writing 1 will have no 613 * effect so we can detect it. 614 */ 615 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE); 616 regmap_read(priv->regmap, TIM_CCER, &ccer); 617 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE); 618 619 priv->have_complementary_output = (ccer != 0); 620 } 621 622 static unsigned int stm32_pwm_detect_channels(struct regmap *regmap, 623 unsigned int *num_enabled) 624 { 625 u32 ccer, ccer_backup; 626 627 /* 628 * If channels enable bits don't exist writing 1 will have no 629 * effect so we can detect and count them. 630 */ 631 regmap_read(regmap, TIM_CCER, &ccer_backup); 632 regmap_set_bits(regmap, TIM_CCER, TIM_CCER_CCXE); 633 regmap_read(regmap, TIM_CCER, &ccer); 634 regmap_write(regmap, TIM_CCER, ccer_backup); 635 636 *num_enabled = hweight32(ccer_backup & TIM_CCER_CCXE); 637 638 return hweight32(ccer & TIM_CCER_CCXE); 639 } 640 641 static int stm32_pwm_probe(struct platform_device *pdev) 642 { 643 struct device *dev = &pdev->dev; 644 struct device_node *np = dev->of_node; 645 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); 646 struct pwm_chip *chip; 647 struct stm32_pwm *priv; 648 unsigned int npwm, num_enabled; 649 unsigned int i; 650 int ret; 651 652 npwm = stm32_pwm_detect_channels(ddata->regmap, &num_enabled); 653 654 chip = devm_pwmchip_alloc(dev, npwm, sizeof(*priv)); 655 if (IS_ERR(chip)) 656 return PTR_ERR(chip); 657 priv = to_stm32_pwm_dev(chip); 658 659 mutex_init(&priv->lock); 660 priv->regmap = ddata->regmap; 661 priv->clk = ddata->clk; 662 priv->max_arr = ddata->max_arr; 663 664 if (!priv->regmap || !priv->clk) 665 return dev_err_probe(dev, -EINVAL, "Failed to get %s\n", 666 priv->regmap ? "clk" : "regmap"); 667 668 ret = stm32_pwm_probe_breakinputs(priv, np); 669 if (ret) 670 return dev_err_probe(dev, ret, 671 "Failed to configure breakinputs\n"); 672 673 stm32_pwm_detect_complementary(priv); 674 675 ret = devm_clk_rate_exclusive_get(dev, priv->clk); 676 if (ret) 677 return dev_err_probe(dev, ret, "Failed to lock clock\n"); 678 679 /* 680 * With the clk running with not more than 1 GHz the calculations in 681 * .apply() won't overflow. 682 */ 683 if (clk_get_rate(priv->clk) > 1000000000) 684 return dev_err_probe(dev, -EINVAL, "Clock freq too high (%lu)\n", 685 clk_get_rate(priv->clk)); 686 687 chip->ops = &stm32pwm_ops; 688 689 /* Initialize clock refcount to number of enabled PWM channels. */ 690 for (i = 0; i < num_enabled; i++) 691 clk_enable(priv->clk); 692 693 ret = devm_pwmchip_add(dev, chip); 694 if (ret < 0) 695 return dev_err_probe(dev, ret, 696 "Failed to register pwmchip\n"); 697 698 platform_set_drvdata(pdev, chip); 699 700 return 0; 701 } 702 703 static int stm32_pwm_suspend(struct device *dev) 704 { 705 struct pwm_chip *chip = dev_get_drvdata(dev); 706 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 707 unsigned int i; 708 u32 ccer, mask; 709 710 /* Look for active channels */ 711 ccer = active_channels(priv); 712 713 for (i = 0; i < chip->npwm; i++) { 714 mask = TIM_CCER_CC1E << (i * 4); 715 if (ccer & mask) { 716 dev_err(dev, "PWM %u still in use by consumer %s\n", 717 i, chip->pwms[i].label); 718 return -EBUSY; 719 } 720 } 721 722 return pinctrl_pm_select_sleep_state(dev); 723 } 724 725 static int stm32_pwm_resume(struct device *dev) 726 { 727 struct pwm_chip *chip = dev_get_drvdata(dev); 728 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 729 int ret; 730 731 ret = pinctrl_pm_select_default_state(dev); 732 if (ret) 733 return ret; 734 735 /* restore breakinput registers that may have been lost in low power */ 736 return stm32_pwm_apply_breakinputs(priv); 737 } 738 739 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume); 740 741 static const struct of_device_id stm32_pwm_of_match[] = { 742 { .compatible = "st,stm32-pwm", }, 743 { /* end node */ }, 744 }; 745 MODULE_DEVICE_TABLE(of, stm32_pwm_of_match); 746 747 static struct platform_driver stm32_pwm_driver = { 748 .probe = stm32_pwm_probe, 749 .driver = { 750 .name = "stm32-pwm", 751 .of_match_table = stm32_pwm_of_match, 752 .pm = pm_ptr(&stm32_pwm_pm_ops), 753 }, 754 }; 755 module_platform_driver(stm32_pwm_driver); 756 757 MODULE_ALIAS("platform:stm32-pwm"); 758 MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver"); 759 MODULE_LICENSE("GPL v2"); 760