1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2019 Spreadtrum Communications Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/err.h> 8 #include <linux/io.h> 9 #include <linux/math64.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pwm.h> 14 15 #define SPRD_PWM_PRESCALE 0x0 16 #define SPRD_PWM_MOD 0x4 17 #define SPRD_PWM_DUTY 0x8 18 #define SPRD_PWM_ENABLE 0x18 19 20 #define SPRD_PWM_MOD_MAX GENMASK(7, 0) 21 #define SPRD_PWM_DUTY_MSK GENMASK(15, 0) 22 #define SPRD_PWM_PRESCALE_MSK GENMASK(7, 0) 23 #define SPRD_PWM_ENABLE_BIT BIT(0) 24 25 #define SPRD_PWM_CHN_NUM 4 26 #define SPRD_PWM_REGS_SHIFT 5 27 #define SPRD_PWM_CHN_CLKS_NUM 2 28 #define SPRD_PWM_CHN_OUTPUT_CLK 1 29 30 struct sprd_pwm_chn { 31 struct clk_bulk_data clks[SPRD_PWM_CHN_CLKS_NUM]; 32 u32 clk_rate; 33 }; 34 35 struct sprd_pwm_chip { 36 void __iomem *base; 37 struct device *dev; 38 struct pwm_chip chip; 39 int num_pwms; 40 struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM]; 41 }; 42 43 static inline struct sprd_pwm_chip* sprd_pwm_from_chip(struct pwm_chip *chip) 44 { 45 return container_of(chip, struct sprd_pwm_chip, chip); 46 } 47 48 /* 49 * The list of clocks required by PWM channels, and each channel has 2 clocks: 50 * enable clock and pwm clock. 51 */ 52 static const char * const sprd_pwm_clks[] = { 53 "enable0", "pwm0", 54 "enable1", "pwm1", 55 "enable2", "pwm2", 56 "enable3", "pwm3", 57 }; 58 59 static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg) 60 { 61 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); 62 63 return readl_relaxed(spc->base + offset); 64 } 65 66 static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid, 67 u32 reg, u32 val) 68 { 69 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); 70 71 writel_relaxed(val, spc->base + offset); 72 } 73 74 static int sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 75 struct pwm_state *state) 76 { 77 struct sprd_pwm_chip *spc = sprd_pwm_from_chip(chip); 78 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 79 u32 val, duty, prescale; 80 u64 tmp; 81 int ret; 82 83 /* 84 * The clocks to PWM channel has to be enabled first before 85 * reading to the registers. 86 */ 87 ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, chn->clks); 88 if (ret) { 89 dev_err(spc->dev, "failed to enable pwm%u clocks\n", 90 pwm->hwpwm); 91 return ret; 92 } 93 94 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); 95 if (val & SPRD_PWM_ENABLE_BIT) 96 state->enabled = true; 97 else 98 state->enabled = false; 99 100 /* 101 * The hardware provides a counter that is feed by the source clock. 102 * The period length is (PRESCALE + 1) * MOD counter steps. 103 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. 104 * Thus the period_ns and duty_ns calculation formula should be: 105 * period_ns = NSEC_PER_SEC * (prescale + 1) * mod / clk_rate 106 * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate 107 */ 108 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); 109 prescale = val & SPRD_PWM_PRESCALE_MSK; 110 tmp = (prescale + 1) * NSEC_PER_SEC * SPRD_PWM_MOD_MAX; 111 state->period = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); 112 113 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); 114 duty = val & SPRD_PWM_DUTY_MSK; 115 tmp = (prescale + 1) * NSEC_PER_SEC * duty; 116 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); 117 state->polarity = PWM_POLARITY_NORMAL; 118 119 /* Disable PWM clocks if the PWM channel is not in enable state. */ 120 if (!state->enabled) 121 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks); 122 123 return 0; 124 } 125 126 static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm, 127 int duty_ns, int period_ns) 128 { 129 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 130 u32 prescale, duty; 131 u64 tmp; 132 133 /* 134 * The hardware provides a counter that is feed by the source clock. 135 * The period length is (PRESCALE + 1) * MOD counter steps. 136 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. 137 * 138 * To keep the maths simple we're always using MOD = SPRD_PWM_MOD_MAX. 139 * The value for PRESCALE is selected such that the resulting period 140 * gets the maximal length not bigger than the requested one with the 141 * given settings (MOD = SPRD_PWM_MOD_MAX and input clock). 142 */ 143 duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns; 144 145 tmp = (u64)chn->clk_rate * period_ns; 146 do_div(tmp, NSEC_PER_SEC); 147 prescale = DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1; 148 if (prescale > SPRD_PWM_PRESCALE_MSK) 149 prescale = SPRD_PWM_PRESCALE_MSK; 150 151 /* 152 * Note: Writing DUTY triggers the hardware to actually apply the 153 * values written to MOD and DUTY to the output, so must keep writing 154 * DUTY last. 155 * 156 * The hardware can ensures that current running period is completed 157 * before changing a new configuration to avoid mixed settings. 158 */ 159 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); 160 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); 161 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); 162 163 return 0; 164 } 165 166 static int sprd_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 167 const struct pwm_state *state) 168 { 169 struct sprd_pwm_chip *spc = sprd_pwm_from_chip(chip); 170 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 171 struct pwm_state *cstate = &pwm->state; 172 int ret; 173 174 if (state->polarity != PWM_POLARITY_NORMAL) 175 return -EINVAL; 176 177 if (state->enabled) { 178 if (!cstate->enabled) { 179 /* 180 * The clocks to PWM channel has to be enabled first 181 * before writing to the registers. 182 */ 183 ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, 184 chn->clks); 185 if (ret) { 186 dev_err(spc->dev, 187 "failed to enable pwm%u clocks\n", 188 pwm->hwpwm); 189 return ret; 190 } 191 } 192 193 ret = sprd_pwm_config(spc, pwm, state->duty_cycle, 194 state->period); 195 if (ret) 196 return ret; 197 198 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1); 199 } else if (cstate->enabled) { 200 /* 201 * Note: After setting SPRD_PWM_ENABLE to zero, the controller 202 * will not wait for current period to be completed, instead it 203 * will stop the PWM channel immediately. 204 */ 205 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0); 206 207 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks); 208 } 209 210 return 0; 211 } 212 213 static const struct pwm_ops sprd_pwm_ops = { 214 .apply = sprd_pwm_apply, 215 .get_state = sprd_pwm_get_state, 216 }; 217 218 static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc) 219 { 220 struct clk *clk_pwm; 221 int ret, i; 222 223 for (i = 0; i < SPRD_PWM_CHN_NUM; i++) { 224 struct sprd_pwm_chn *chn = &spc->chn[i]; 225 int j; 226 227 for (j = 0; j < SPRD_PWM_CHN_CLKS_NUM; ++j) 228 chn->clks[j].id = 229 sprd_pwm_clks[i * SPRD_PWM_CHN_CLKS_NUM + j]; 230 231 ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_CHN_CLKS_NUM, 232 chn->clks); 233 if (ret) { 234 if (ret == -ENOENT) 235 break; 236 237 return dev_err_probe(spc->dev, ret, 238 "failed to get channel clocks\n"); 239 } 240 241 clk_pwm = chn->clks[SPRD_PWM_CHN_OUTPUT_CLK].clk; 242 chn->clk_rate = clk_get_rate(clk_pwm); 243 } 244 245 if (!i) 246 return dev_err_probe(spc->dev, -ENODEV, "no available PWM channels\n"); 247 248 spc->num_pwms = i; 249 250 return 0; 251 } 252 253 static int sprd_pwm_probe(struct platform_device *pdev) 254 { 255 struct sprd_pwm_chip *spc; 256 int ret; 257 258 spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL); 259 if (!spc) 260 return -ENOMEM; 261 262 spc->base = devm_platform_ioremap_resource(pdev, 0); 263 if (IS_ERR(spc->base)) 264 return PTR_ERR(spc->base); 265 266 spc->dev = &pdev->dev; 267 268 ret = sprd_pwm_clk_init(spc); 269 if (ret) 270 return ret; 271 272 spc->chip.dev = &pdev->dev; 273 spc->chip.ops = &sprd_pwm_ops; 274 spc->chip.npwm = spc->num_pwms; 275 276 ret = devm_pwmchip_add(&pdev->dev, &spc->chip); 277 if (ret) 278 dev_err(&pdev->dev, "failed to add PWM chip\n"); 279 280 return ret; 281 } 282 283 static const struct of_device_id sprd_pwm_of_match[] = { 284 { .compatible = "sprd,ums512-pwm", }, 285 { }, 286 }; 287 MODULE_DEVICE_TABLE(of, sprd_pwm_of_match); 288 289 static struct platform_driver sprd_pwm_driver = { 290 .driver = { 291 .name = "sprd-pwm", 292 .of_match_table = sprd_pwm_of_match, 293 }, 294 .probe = sprd_pwm_probe, 295 }; 296 297 module_platform_driver(sprd_pwm_driver); 298 299 MODULE_DESCRIPTION("Spreadtrum PWM Driver"); 300 MODULE_LICENSE("GPL v2"); 301