1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * sl28cpld PWM driver 4 * 5 * Copyright (c) 2020 Michael Walle <michael@walle.cc> 6 * 7 * There is no public datasheet available for this PWM core. But it is easy 8 * enough to be briefly explained. It consists of one 8-bit counter. The PWM 9 * supports four distinct frequencies by selecting when to reset the counter. 10 * With the prescaler setting you can select which bit of the counter is used 11 * to reset it. This implies that the higher the frequency the less remaining 12 * bits are available for the actual counter. 13 * 14 * Let cnt[7:0] be the counter, clocked at 32kHz: 15 * +-----------+--------+--------------+-----------+---------------+ 16 * | prescaler | reset | counter bits | frequency | period length | 17 * +-----------+--------+--------------+-----------+---------------+ 18 * | 0 | cnt[7] | cnt[6:0] | 250 Hz | 4000000 ns | 19 * | 1 | cnt[6] | cnt[5:0] | 500 Hz | 2000000 ns | 20 * | 2 | cnt[5] | cnt[4:0] | 1 kHz | 1000000 ns | 21 * | 3 | cnt[4] | cnt[3:0] | 2 kHz | 500000 ns | 22 * +-----------+--------+--------------+-----------+---------------+ 23 * 24 * Limitations: 25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0. 26 * - The hardware cannot atomically set the prescaler and the counter value, 27 * which might lead to glitches and inconsistent states if a write fails. 28 * - The counter is not reset if you switch the prescaler which leads 29 * to glitches, too. 30 * - The duty cycle will switch immediately and not after a complete cycle. 31 * - Depending on the actual implementation, disabling the PWM might have 32 * side effects. For example, if the output pin is shared with a GPIO pin 33 * it will automatically switch back to GPIO mode. 34 */ 35 36 #include <linux/bitfield.h> 37 #include <linux/kernel.h> 38 #include <linux/mod_devicetable.h> 39 #include <linux/module.h> 40 #include <linux/platform_device.h> 41 #include <linux/property.h> 42 #include <linux/pwm.h> 43 #include <linux/regmap.h> 44 45 /* 46 * PWM timer block registers. 47 */ 48 #define SL28CPLD_PWM_CTRL 0x00 49 #define SL28CPLD_PWM_CTRL_ENABLE BIT(7) 50 #define SL28CPLD_PWM_CTRL_PRESCALER_MASK GENMASK(1, 0) 51 #define SL28CPLD_PWM_CYCLE 0x01 52 #define SL28CPLD_PWM_CYCLE_MAX GENMASK(6, 0) 53 54 #define SL28CPLD_PWM_CLK 32000 /* 32 kHz */ 55 #define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler) (1 << (7 - (prescaler))) 56 #define SL28CPLD_PWM_PERIOD(prescaler) \ 57 (NSEC_PER_SEC / SL28CPLD_PWM_CLK * SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)) 58 59 /* 60 * We calculate the duty cycle like this: 61 * duty_cycle_ns = pwm_cycle_reg * max_period_ns / max_duty_cycle 62 * 63 * With 64 * max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC 65 * max_duty_cycle = 1 << (7 - prescaler) 66 * this then simplifies to: 67 * duty_cycle_ns = pwm_cycle_reg / SL28CPLD_PWM_CLK * NSEC_PER_SEC 68 * = NSEC_PER_SEC / SL28CPLD_PWM_CLK * pwm_cycle_reg 69 * 70 * NSEC_PER_SEC is a multiple of SL28CPLD_PWM_CLK, therefore we're not losing 71 * precision by doing the divison first. 72 */ 73 #define SL28CPLD_PWM_TO_DUTY_CYCLE(reg) \ 74 (NSEC_PER_SEC / SL28CPLD_PWM_CLK * (reg)) 75 #define SL28CPLD_PWM_FROM_DUTY_CYCLE(duty_cycle) \ 76 (DIV_ROUND_DOWN_ULL((duty_cycle), NSEC_PER_SEC / SL28CPLD_PWM_CLK)) 77 78 #define sl28cpld_pwm_read(priv, reg, val) \ 79 regmap_read((priv)->regmap, (priv)->offset + (reg), (val)) 80 #define sl28cpld_pwm_write(priv, reg, val) \ 81 regmap_write((priv)->regmap, (priv)->offset + (reg), (val)) 82 83 struct sl28cpld_pwm { 84 struct pwm_chip chip; 85 struct regmap *regmap; 86 u32 offset; 87 }; 88 89 static inline struct sl28cpld_pwm *sl28cpld_pwm_from_chip(struct pwm_chip *chip) 90 { 91 return container_of(chip, struct sl28cpld_pwm, chip); 92 } 93 94 static int sl28cpld_pwm_get_state(struct pwm_chip *chip, 95 struct pwm_device *pwm, 96 struct pwm_state *state) 97 { 98 struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip); 99 unsigned int reg; 100 int prescaler; 101 102 sl28cpld_pwm_read(priv, SL28CPLD_PWM_CTRL, ®); 103 104 state->enabled = reg & SL28CPLD_PWM_CTRL_ENABLE; 105 106 prescaler = FIELD_GET(SL28CPLD_PWM_CTRL_PRESCALER_MASK, reg); 107 state->period = SL28CPLD_PWM_PERIOD(prescaler); 108 109 sl28cpld_pwm_read(priv, SL28CPLD_PWM_CYCLE, ®); 110 state->duty_cycle = SL28CPLD_PWM_TO_DUTY_CYCLE(reg); 111 state->polarity = PWM_POLARITY_NORMAL; 112 113 /* 114 * Sanitize values for the PWM core. Depending on the prescaler it 115 * might happen that we calculate a duty_cycle greater than the actual 116 * period. This might happen if someone (e.g. the bootloader) sets an 117 * invalid combination of values. The behavior of the hardware is 118 * undefined in this case. But we need to report sane values back to 119 * the PWM core. 120 */ 121 state->duty_cycle = min(state->duty_cycle, state->period); 122 123 return 0; 124 } 125 126 static int sl28cpld_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 127 const struct pwm_state *state) 128 { 129 struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip); 130 unsigned int cycle, prescaler; 131 bool write_duty_cycle_first; 132 int ret; 133 u8 ctrl; 134 135 /* Polarity inversion is not supported */ 136 if (state->polarity != PWM_POLARITY_NORMAL) 137 return -EINVAL; 138 139 /* 140 * Calculate the prescaler. Pick the biggest period that isn't 141 * bigger than the requested period. 142 */ 143 prescaler = DIV_ROUND_UP_ULL(SL28CPLD_PWM_PERIOD(0), state->period); 144 prescaler = order_base_2(prescaler); 145 146 if (prescaler > field_max(SL28CPLD_PWM_CTRL_PRESCALER_MASK)) 147 return -ERANGE; 148 149 ctrl = FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, prescaler); 150 if (state->enabled) 151 ctrl |= SL28CPLD_PWM_CTRL_ENABLE; 152 153 cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle); 154 cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)); 155 156 /* 157 * Work around the hardware limitation. See also above. Trap 100% duty 158 * cycle if the prescaler is 0. Set prescaler to 1 instead. We don't 159 * care about the frequency because its "all-one" in either case. 160 * 161 * We don't need to check the actual prescaler setting, because only 162 * if the prescaler is 0 we can have this particular value. 163 */ 164 if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) { 165 ctrl &= ~SL28CPLD_PWM_CTRL_PRESCALER_MASK; 166 ctrl |= FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, 1); 167 cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1); 168 } 169 170 /* 171 * To avoid glitches when we switch the prescaler, we have to make sure 172 * we have a valid duty cycle for the new mode. 173 * 174 * Take the current prescaler (or the current period length) into 175 * account to decide whether we have to write the duty cycle or the new 176 * prescaler first. If the period length is decreasing we have to 177 * write the duty cycle first. 178 */ 179 write_duty_cycle_first = pwm->state.period > state->period; 180 181 if (write_duty_cycle_first) { 182 ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle); 183 if (ret) 184 return ret; 185 } 186 187 ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CTRL, ctrl); 188 if (ret) 189 return ret; 190 191 if (!write_duty_cycle_first) { 192 ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle); 193 if (ret) 194 return ret; 195 } 196 197 return 0; 198 } 199 200 static const struct pwm_ops sl28cpld_pwm_ops = { 201 .apply = sl28cpld_pwm_apply, 202 .get_state = sl28cpld_pwm_get_state, 203 }; 204 205 static int sl28cpld_pwm_probe(struct platform_device *pdev) 206 { 207 struct sl28cpld_pwm *priv; 208 struct pwm_chip *chip; 209 int ret; 210 211 if (!pdev->dev.parent) { 212 dev_err(&pdev->dev, "no parent device\n"); 213 return -ENODEV; 214 } 215 216 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 217 if (!priv) 218 return -ENOMEM; 219 220 priv->regmap = dev_get_regmap(pdev->dev.parent, NULL); 221 if (!priv->regmap) { 222 dev_err(&pdev->dev, "could not get parent regmap\n"); 223 return -ENODEV; 224 } 225 226 ret = device_property_read_u32(&pdev->dev, "reg", &priv->offset); 227 if (ret) { 228 dev_err(&pdev->dev, "no 'reg' property found (%pe)\n", 229 ERR_PTR(ret)); 230 return -EINVAL; 231 } 232 233 /* Initialize the pwm_chip structure */ 234 chip = &priv->chip; 235 chip->dev = &pdev->dev; 236 chip->ops = &sl28cpld_pwm_ops; 237 chip->npwm = 1; 238 239 ret = devm_pwmchip_add(&pdev->dev, chip); 240 if (ret) { 241 dev_err(&pdev->dev, "failed to add PWM chip (%pe)", 242 ERR_PTR(ret)); 243 return ret; 244 } 245 246 return 0; 247 } 248 249 static const struct of_device_id sl28cpld_pwm_of_match[] = { 250 { .compatible = "kontron,sl28cpld-pwm" }, 251 {} 252 }; 253 MODULE_DEVICE_TABLE(of, sl28cpld_pwm_of_match); 254 255 static struct platform_driver sl28cpld_pwm_driver = { 256 .probe = sl28cpld_pwm_probe, 257 .driver = { 258 .name = "sl28cpld-pwm", 259 .of_match_table = sl28cpld_pwm_of_match, 260 }, 261 }; 262 module_platform_driver(sl28cpld_pwm_driver); 263 264 MODULE_DESCRIPTION("sl28cpld PWM Driver"); 265 MODULE_AUTHOR("Michael Walle <michael@walle.cc>"); 266 MODULE_LICENSE("GPL"); 267